Chip packaging structure and radio frequency front-end module

Abstract

The utility model provides a chip packaging structure and a radio frequency front-end module, the chip packaging structure comprises a substrate, a solder mask layer, a filter chip, a non-filter chip, a supporting part, an isolation layer and a plastic packaging layer, and the solder mask layer is provided with a first window and a second window; the filter chip is mounted on the substrate through the first window; the non-filter chip is mounted on the substrate through the second open window; a cavity structure is formed among the filter chip, the supporting part and the substrate; the filter chip and the non-filter chip are packaged on the substrate by the plastic package layer, the plastic package layer is isolated outside the filter chip by the isolation layer, and part of the plastic package layer is arranged in a gap between the non-filter chip and the substrate; the supporting part is at least partially contacted with the bottom surface of the filter chip; and a part of the supporting part is positioned in a spacing region between the filter chip and the non-filter chip. According to the chip packaging structure and the radio frequency front-end module, the probability of failure caused by collapse of the filter chip can be reduced, and the reliability of the chip packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a chip packaging structure and a radio frequency front-end module. Background Art

[0002] Some surface acoustic wave (SAW) chips, bulk acoustic wave (BAW) chips or non-filter chips need to have a cavity structure between the substrate and the chip during the packaging process to meet their functions, performance or other special requirements. When packaging the chip, it is usually necessary to form a plastic layer on the side of the chip away from the substrate through an injection molding process to prevent the external environment from affecting the chip. When forming the plastic layer through the injection molding process, if the injection molding pressure is too small, the plastic material of the plastic layer will not be fully filled; if the injection molding pressure is too high, it may cause the chip (especially the filter chip) to collapse, which will cause the chip to fail and reduce reliability. Utility Model Content

[0003] The present application provides a chip packaging structure and a radio frequency front-end module, which aim to reduce the probability of collapse and failure of the filter chip and improve the reliability of the chip packaging structure.

[0004] The present application provides a chip packaging structure, including:

[0005] substrate;

[0006] A solder resist layer is provided on the substrate and is formed with a first opening and a second opening;

[0007] A filter chip is mounted on the substrate through the first opening;

[0008] a non-filter chip, mounted on the substrate through the second opening, and spaced apart from the filter chip;

[0009] A support portion is provided on a side of the solder resist layer away from the substrate, and a cavity structure is formed between the filter chip, the support portion and the substrate;

[0010] an isolation layer, covering the filter chip, the non-filter chip and the support portion, wherein the isolation layer is formed with a communication port at the periphery of the non-filter chip, and the communication port is connected to the second window;

[0011] A plastic encapsulation layer, wherein the plastic encapsulation layer encapsulates the filter chip and the non-filter chip on the substrate, the isolation layer isolates the plastic encapsulation layer from the filter chip, and a portion of the plastic encapsulation layer is disposed in a gap between the non-filter chip and the substrate;

[0012] The support portion is at least partially in contact with the bottom surface of the filter chip to support the filter chip; and part of the support portion is located in a spacing area between the filter chip and the non-filter chip.

[0013] The present application also provides a chip packaging structure, including:

[0014] substrate;

[0015] A solder resist layer is disposed on the substrate and is formed with a first opening;

[0016] A filter chip is mounted on the substrate through the first opening;

[0017] The support portion is arranged on a side of the solder resist layer away from the substrate, and a cavity structure is formed between the filter chip, the support portion and the substrate; the distance between the surface of the support portion away from the substrate and the substrate is smaller than the distance between the surface of the filter chip close to the substrate and the substrate;

[0018] An isolation layer, covering the filter chip and the support portion;

[0019] A plastic encapsulation layer, wherein the plastic encapsulation layer encapsulates the filter chip on the substrate, and the isolation layer isolates the plastic encapsulation layer from the filter chip;

[0020] Wherein, the supporting portion is in at least partial contact with the bottom surface of the filter chip to support the filter chip; the number of the filter chips includes at least two, and two adjacent filter chips are arranged at intervals; part of the supporting portion is located in the gap area between two adjacent filter chips, the distance from the surface of the filter chip away from the substrate to the surface of the supporting portion away from the substrate is m, the interval distance between two adjacent filter chips is n, and the ratio of m to n is less than 2.

[0021] The present application also provides a chip packaging structure, including:

[0022] substrate;

[0023] A solder resist layer is disposed on the substrate and is formed with a first opening;

[0024] A filter chip is mounted on the substrate through the first opening;

[0025] A support portion is provided on a side of the solder resist layer away from the substrate, and a cavity structure is formed between the filter chip, the support portion and the substrate;

[0026] An isolation layer, covering the filter chip and the support portion;

[0027] A plastic encapsulation layer, wherein the plastic encapsulation layer encapsulates the filter chip on the substrate, and the isolation layer isolates the plastic encapsulation layer from the filter chip;

[0028] Wherein, the support portion is in at least partial contact with the bottom surface of the filter chip to support the filter chip; the number of the filter chips includes at least two, and the two filter chips are arranged at intervals; part of the support portion is located in the gap area between two adjacent filter chips.

[0029] The present application also provides a radio frequency front-end module, comprising a chip packaging structure as described in any of the above items.

[0030] The chip packaging structure and RF front-end module provided by the present application are capable of supporting the filter chip because the support portion is in at least partial contact with the bottom surface of the filter chip, so that the support portion can buffer or release the force exerted on the filter chip to a certain extent, thereby protecting the filter chip, reducing the probability of the filter chip collapsing and causing failure of the filter chip, improving the connection reliability between the filter chip and the substrate, and thereby improving the reliability of the chip packaging structure.

[0031] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and cannot limit the disclosure of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 is a structural schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0034] Figure 2 It is a partial structural schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0035] Figure 3 It is a partial structural schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0036] Figure 4 It is a partial structural schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0037] Figure 5 It is a partial structural schematic diagram of a chip packaging structure provided by an embodiment of the present application;

[0038] Figure 6 is a schematic diagram of a chip packaging structure of a comparative example after processing an isolation layer;

[0039] Figure 7 It is a schematic diagram of a chip packaging structure provided in one embodiment of the present application after processing an isolation layer.

[0040] Description of reference numerals:

[0041] 100. Chip packaging structure;

[0042] 10. Substrate;

[0043] 20. solder resist layer; 21. first window; 22. second window; 23. solder resist sub-area; 24. slot;

[0044] 30. filter chip; 31. first chip body; 32. first convex portion;

[0045] 40. non-filter chip; 41. second chip body; 42. second convex portion;

[0046] 50, support portion; 51, support region; 512, protruding region; 52, extension region; 521, extension sub-region;

[0047] 61. Cavity structure; 62. Gap;

[0048] 70. Isolation layer; 71. Communication port;

[0049] 80. Plastic sealing layer;

[0050] 91. Interval area; 92. Gap area;

[0051] 200. Bubbles. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0054] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, the singular forms "a", "an" and "the" are intended to include plural forms unless the context clearly indicates otherwise.

[0055] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0056] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0057] See also Figure 1 and Figure 2The embodiment of the present application provides a chip packaging structure 100, including a substrate 10, a solder resist layer 20, a filter chip 30, a non-filter chip 40, a support portion 50, an isolation layer 70 and a plastic sealing layer 80, wherein the solder resist layer 20 is disposed on the substrate 10, and the solder resist layer 20 is formed with a first window 21 and a second window 22; the filter chip 30 is mounted on the substrate 10 through the first window 21; the non-filter chip 40 is mounted on the substrate 10 through the second window 22, and the non-filter chip 40 is spaced apart from the filter chip 30; the support portion 50 is disposed on the solder resist layer 20 away from the substrate On one side of the board 10, a cavity structure 61 is formed between the filter chip 30, the support part 50 and the substrate 10; the isolation layer 70 covers the filter chip 30, the non-filter chip 40 and the support part 50, and the isolation layer 70 forms a connecting port 71 on the periphery of the non-filter chip 30, and the connecting port 71 is connected to the second window 22; the plastic sealing layer 80 encapsulates the filter chip 30 and the non-filter chip 40 on the substrate 10, and the isolation layer 70 isolates the plastic sealing layer 80 from the outside of the filter chip 30, and part of the plastic sealing layer 80 is arranged in the gap 62 between the non-filter chip 40 and the substrate 10. Among them, the support part 50 is at least partially in contact with the bottom surface of the filter chip 30 to support the filter chip 30; part of the support part 50 is located in the spacing area 91 between the filter chip 30 and the non-filter chip 40.

[0058] In the chip packaging structure 100 of the above embodiment, since the support portion 50 is at least partially in contact with the bottom surface of the filter chip 30, the support portion 50 can support the filter chip 30, so that the support portion 50 can buffer or release the stress on the filter chip 30 to a certain extent, thereby protecting the filter chip 30, reducing the probability of the filter chip 30 collapsing and causing the filter chip 30 to fail, improving the connection reliability between the filter chip 30 and the substrate 10, and thus improving the reliability of the chip packaging structure 100. Secondly, a cavity structure 61 can be formed between the filter chip 30 and the substrate 10 to achieve a good filtering function. The isolation layer 70 covers the filter chip 30, the non-filter chip 40 and the support part 50, so that during the plastic packaging process, the isolation layer 70 can protect the filter chip 30 and the non-filter chip 40; and can prevent the plastic packaging material of the plastic packaging layer 80 from damaging at least one of the support part 50 and the solder resist layer 20 and entering the cavity structure 61 during the plastic packaging process, and can prevent the plastic packaging material of the plastic packaging layer 80 from entering the cavity structure 61 through the connection between the support part 50 and the filter chip 30, thereby increasing the difficulty of the plastic packaging material used in the plastic packaging layer 80 entering the cavity structure 61, thereby providing a guarantee for the filter chip 30 to achieve a good filtering function.

[0059] In addition, during the plastic encapsulation process, the plastic encapsulation material of the plastic encapsulation layer 80 can enter the gap 62 between the non-filter chip 40 and the substrate 10 through the connecting port 71, so that after the plastic encapsulation is completed, part of the plastic encapsulation layer 80 is arranged in the gap 62 between the non-filter chip 40 and the substrate 10, and the plastic encapsulation layer 80 filled in the gap 62 can support the non-filter chip 40, thereby buffering or releasing the stress on the non-filter chip 40, protecting the non-filter chip 40, reducing the probability of the non-filter chip 40 collapsing and causing the non-filter chip 40 to fail, improving the connection reliability between the non-filter chip 40 and the substrate 10, and thus improving the reliability of the chip packaging structure 100. In addition, since part of the support portion 50 is located in the spacing area 91 between the filter chip 30 and the non-filter chip 40, the support portion 50 located in the spacing area 91 can increase the difficulty of the plastic encapsulation material of the plastic encapsulation layer 80 breaking through the support portion 50 and entering the cavity structure 61 during packaging, thereby further ensuring that the filter chip 30 can achieve a good filtering function.

[0060] It is understandable that in the scenario where the filter chip 30 and the non-filter chip 40 are packaged together, in order to ensure that the plastic encapsulation material used in the plastic encapsulation layer 80 can smoothly fill the gap 62 between the non-filter chip 40 and the substrate 10 during the plastic encapsulation process, the plastic encapsulation pressure will be increased during the plastic encapsulation process. A support portion 50 is provided on the peripheral side of the filter chip 30 so that the support portion 50 is at least partially in contact with the bottom surface of the filter chip 30, thereby ensuring that the plastic encapsulation material used in the plastic encapsulation layer 80 can smoothly fill the bottom of the non-filter chip 40 completely during the plastic encapsulation process, and avoiding the filter chip 30 from easily collapsing or tilting due to excessive plastic encapsulation pressure or excessive pressure during lamination, thereby improving the overall packaging reliability.

[0061] Exemplarily, the substrate 10 only includes metal wiring, but the scope of the present application is not limited thereto. In some embodiments of the present application, according to the need for interconnection of internal and external pins of the filter chip 30 or the non-filter chip 40, one or more metal layer wiring and dielectric layers may be deposited on both sides of the substrate 10 by photolithography, TSV or other substrate 10 technologies.

[0062] Exemplarily, the solder resist layer 20 includes at least one of the following: a resin layer, an ink layer, a dry film, etc. It can be understood that the solder resist layer 20 can protect the substrate 10 and prevent the metal wiring in the substrate 10 from short-circuiting. Exemplarily, in an area on the surface of the substrate 10 where no metal wiring is provided, the solder resist layer 20 is provided between two adjacent metal wirings; in an area on the surface of the substrate 10 where metal wiring is provided, the solder resist layer 20 covers the metal wiring.

[0063] Exemplarily, the filter chip 30 includes a surface acoustic wave filter chip, a bulk acoustic wave filter chip, or other chips with filtering functions. Exemplarily, the filter chip 30 and the non-filter chip 40 can be mounted on the substrate 10 in a flip-chip manner. Of course, the present application can also include other non-filter chips 40, which are mounted on the substrate 10 by bonding wires.

[0064] The number of filter chips 30 can be designed according to actual needs, such as one, two, three or more. When the number of filter chips 30 includes multiple, at least one of the functions, sizes, shapes, structures and distances to the substrate 10 of different filter chips 30 can be different or the same. When the number of filter chips 30 includes multiple, multiple filter chips 30 are arranged at intervals. Different filter chips 30 can be arranged on the same side of the substrate 10, or on different sides of the substrate 10.

[0065] See also Figure 2 , exemplarily, the filter chip 30 includes a first chip body 31 and a first convex portion 32, the first convex portion 32 is convexly arranged on the side of the first chip body 31 facing the substrate 10, the first chip body 31 is electrically connected to the substrate 10 through the first convex portion 32, and a cavity structure 61 is formed between the first chip body 31, the support portion 50 and the substrate 10. The support portion 50 can buffer or release the stress on the first chip body 31 to a certain extent, thereby protecting the first convex portion 32 in the filter chip 30 for connecting with the substrate 10, reducing the probability of the first convex portion 32 collapsing and causing poor contact between the filter chip 30 and the substrate 10, thereby improving the reliability of the chip packaging structure 100.

[0066] Exemplarily, the non-filter chip 40 includes a power amplifier, a low noise amplifier, a radio frequency switch, a capacitor, an inductor or a resistor, etc. The non-filter chip 40 can be mounted on the substrate 10 in a flip-chip manner, or can be mounted on the substrate 10 in a bonding wire manner. It should be noted that during the plastic encapsulation filling process of the plastic encapsulation layer 80, the plastic encapsulation material used in the plastic encapsulation layer 80 needs to enter the gap 62 between the non-filter chip 40 and the substrate 10 to achieve encapsulation to ensure the reliability of the non-filter chip 40 encapsulation. The filter chip 30 and the non-filter chip 40 can be arranged on the same side of the substrate 10; in other embodiments, the filter chip 30 can also be arranged on the same side of the substrate 10 with part of the non-filter chip 40, and another part of the non-filter chip 40 is arranged on the other side of the substrate 10, which is not specifically limited in this application.

[0067] The number of non-filter chips 40 can be designed according to actual needs, such as one, two, three or more. When the number of non-filter chips 40 includes multiple, at least one of the functions, sizes, shapes, structures and distances to the substrate 10 of different non-filter chips 40 may be different or the same. When the number of non-filter chips 40 includes multiple, multiple non-filter chips 40 are arranged at intervals. Different non-filter chips 40 can be arranged on the same side of the substrate 10, or on different sides of the substrate 10. In some embodiments, the non-filter chip 40 can also be omitted.

[0068] See also Figure 2 , illustratively, the non-filter chip 40 includes a second chip body 41 and a second convex portion 42, the second convex portion 42 is convexly arranged on the side of the second chip body 41 facing the substrate 10, and the second chip body 41 is electrically connected to the substrate 10 through the second convex portion 42. The plastic encapsulation layer 80 filled in the gap 62 between the non-filter chip 40 and the substrate 10 can support the non-filter chip 40, thereby buffering or releasing the stress on the non-filter chip 40, protecting the second convex portion 42 in the non-filter chip 40 for connecting with the substrate 10, reducing the probability of the second convex portion 42 collapsing and causing poor contact between the non-filter chip 40 and the substrate 10, and improving the reliability of the chip packaging structure 100.

[0069] In some embodiments, the first window 21 can expose the first electrical connection portion (not shown) of the substrate 10, so that the first protrusion 32 of the filter chip 30 can be connected to the first electrical connection portion of the substrate 10, thereby realizing the connection between the filter chip 30 and the substrate 10; the provision of the first window 21 can also reduce the weight of the solder mask 20, thereby facilitating the lightweight design of the chip packaging structure 100. Exemplarily, the first protrusion 32 includes at least one of the following: a metal bump such as a solder ball or a copper column. The first electrical connection portion includes a pad. Exemplarily, the size of the first window 21 is smaller than the size of the filter chip 30. In other embodiments, the size of the first window 21 may also be greater than or equal to the size of the filter chip 30. It can be understood that the first protrusion 32 of the filter chip 30 is connected to the first pad of the substrate 10. The first opening window 21 may be opened at a position where the first pad needs to be exposed, and the rest of the area in the substrate 10 opposite to the filter chip 30 is covered by the solder resist layer 20. In this case, one filter chip 30 corresponds to a plurality of first opening windows 21, and each first opening window 21 corresponds to a first convex portion 32. The first opening window 21 may also be opened at the bottom of the entire filter chip 30. In this case, one filter chip 30 corresponds to one first opening window 21.

[0070] In some embodiments, the second window 22 can expose the second electrical connection portion (not shown) of the substrate 10, so that the second convex portion 42 of the non-filter chip 40 can be connected to the second electrical connection portion, thereby realizing the connection between the non-filter chip 40 and the substrate 10; in addition, the second window 22 can also reduce the weight of the solder mask 20, thereby facilitating the lightweight design of the chip packaging structure 100. Exemplarily, the second convex portion 42 includes at least one of the following: a solder ball, a metal bump. The second electrical connection portion includes a second pad. Exemplarily, the size of the second window 22 is larger than the size of the non-filter chip 40. If the size of the second window 22 is too small, if the injection pressure is not large enough during plastic sealing, the plastic sealing material of the plastic sealing layer 80 is difficult to completely fill the gap 62 between the non-filter chip 40 and the substrate 10, and bubbles may be easily generated at the bottom of the non-filter chip 40, resulting in insufficient stability and reliability of the non-filter chip 40. The size of the second window 22 is larger than the size of the non-filter chip 40, which can ensure that the plastic sealing material of the plastic sealing layer 80 can fill the gap 62 as much as possible during plastic sealing, reduce the probability of bubbles generated at the bottom of the non-filter chip 40, improve the reliability and stability of the non-filter chip 40, and further improve the reliability of the chip packaging structure 100. In other embodiments, the size of the second window 22 can also be smaller than or equal to the size of the non-filter chip 40. For example, when the distance between the filter chip 30 and the substrate 10 is relatively large, the size of the second window 22 can be smaller than or equal to the size of the non-filter chip 40.

[0071] Exemplarily, a solder resist layer 20 is provided at the bottom of the first chip body 31 (the side of the first chip body 31 facing the substrate 10), that is, part of the solder resist layer 20 is located between the first chip body 31 and the substrate 10 to protect the metal connecting wires at the bottom; no solder resist layer 20 is provided at the bottom of the non-filter chip 40 (the side of the second chip body 41 facing the substrate 10), that is, no solder resist layer 20 is provided in the gap 62 between the non-filter chip 40 and the substrate 10, thereby increasing the gap 62, making it easier for the plastic sealing material used in the plastic sealing layer 80 to more fully fill the bottom of the non-filter chip 40 during plastic sealing.

[0072] Exemplarily, the surface of the filter chip 30 facing away from the substrate 10 is substantially a flush surface, so that the stress is more uniform. The surface of the non-filter chip 40 facing away from the substrate 10 is substantially a flush surface, so that the stress is more uniform.

[0073] In some embodiments, the support portion 50 includes at least one of the following: an ink layer, a deformable support portion 50, etc. Exemplarily, the deformable support portion 50 includes at least one of the following: a support portion 50 made of a thermal expansion material, a support portion 50 having flexibility or elasticity. The deformable support portion 50 can achieve different buffering effects, and can control the spacing distance between the first convex portion 32 of the filter chip 30 and the support portion 50 according to the different forms of the support portion 50, thereby controlling the bonding strength between the first convex portion 32 and the support portion 50. Exemplarily, when the support portion 50 is deformable, the portion of the support portion 50 outside the filter chip 30 (i.e., the extended area 52 of the support portion 50) is slightly higher than the edge position of the bottom of the filter chip 30, so that the extended area 52 can block the molding material of the molding layer 80 during the molding process, increase the difficulty of the molding material used in the molding layer 80 to enter the cavity structure 61, thereby providing a guarantee for the filter chip 30 to achieve a good filtering function.

[0074] Exemplarily, the isolation layer 70 may include a dry film. In other embodiments, the isolation layer 70 may also be made of glue or glue. The glue may cover the entire chip (such as the filter chip 30 or the non-filter chip 40) above and around. The glue may be provided only at the position where the filter chip 30 contacts the support portion 50.

[0075] Exemplarily, the communication port 71 may be formed before the molding process; or, the communication port 71 may be formed during the molding process to form the molding layer 80 when the molding material used in the molding layer 80 breaks through the isolation layer 70 located at the spacing area 91 .

[0076] The plastic packaging layer 80 can be used to isolate the chip packaging structure 100 from the external environment to prevent humidity, temperature, particles, etc. in the external environment from affecting the chip packaging structure 100 , thereby protecting the chip packaging structure 100 .

[0077] The plastic encapsulation material used in the plastic encapsulation layer 80 may include an insulating resin material or other conventional plastic encapsulation materials. Optionally, the plastic encapsulation material is a resin material containing particles; wherein the particles may be silicon dioxide particles or aluminum oxide particles, which is not limited in this embodiment. It is understandable that other insulating materials having good fluidity or being in liquid state at high temperatures may also be used, and other materials that can achieve a sealing function may also be used.

[0078] See also Figure 2In some embodiments, the support portion 50 includes a support area 51 and an extension area 52. The support area 51 contacts the filter chip 30 to support the filter chip 30. The support area 51 is provided with a hollow window (not shown) for forming a cavity structure 61. The projection of the support area 51 on the substrate 10 overlaps with the projection of the filter chip 30 on the substrate 10. The first chip body 31 of the filter chip 30, the support area 51, and the solder resist layer 20 are arranged in sequence along a first direction perpendicular to the substrate 10. The extension area 52 extends from the support area 51 in a direction away from the hollow window. The projection of the extension area 52 on the substrate 10 is located outside the projection of the filter chip 30 on the substrate 10. The support area 51 can buffer or release the stress on the filter chip 30, thereby reducing the probability of the filter chip 30 collapsing and causing the filter chip 30 to fail, and improving the reliability of the chip packaging structure 100. The setting of the extended area 52 enables a part of the support portion 50 to be located on the outside of the filter chip 30, which can act as a height buffer and provide a certain degree of protection for the isolation layer 70, thereby preventing the isolation layer 70 from breaking at the edge of the filter chip 30 due to a large height difference during the formation of the isolation layer 70 or during plastic sealing, thereby causing the plastic sealing material used in the plastic sealing layer 80 to enter the cavity structure 61 of the filter chip 30.

[0079] In some embodiments, the distance that the support region 51 extends toward the cavity structure 61 is greater than or equal to 5 um. If the distance that the support region 51 extends toward the cavity structure 61 is too small, the effect of the support portion 50 supporting the filter chip 30 is not good. If the distance that the support region 51 extends toward the cavity structure 61 is greater than or equal to 5 um, the support portion 50 can well support the filter chip 30, thereby effectively reducing the probability that the filter chip 30 is prone to collapse and causes the filter chip 30 to fail.

[0080] In some embodiments, the spacing distance between the support area 51 and the first chip body 31 of the filter chip 30 is less than or equal to 10um, such as 0mm, 5um, 10um or any other suitable value between 0um-10um, so that it can ensure that the support portion 50 can support the filter chip 30, and it can also allow the filter chip 30, the support portion 50, the solder resist layer 20 and the assembly or processing between the components to have a certain error, which is conducive to reducing the processing difficulty of the chip packaging structure 100. It can be understood that the spacing distance between the support area 51 (or the support portion 50) and the first chip body 31 of the filter chip 30 refers to the spacing distance between the two along the first direction.

[0081] In some embodiments, the filter chip 30 includes a chip element, and the spacing distance between the support area 51 and the chip element in the second direction parallel to the substrate 10 is greater than or equal to 20um. In this way, even if the support portion 50 is offset during processing or use, the support portion 50 is not likely to affect the working performance of the filter chip 30, making the processing of the chip packaging structure 100 easier. For example, in the first direction, Figure 1 The second direction is perpendicular to the first direction.

[0082] See also Figure 3 In some embodiments, when viewed from the top, the support region 51 includes a protruding region 512, and the protruding region 512 extends toward the cavity structure 61. The setting of the protruding region 512 is conducive to increasing the support area of ​​the support region 51 and improving the support effect of the support region 51 on the filter chip 30. Exemplarily, the protruding region 512 is mainly arranged at a position where the chip element is far from the edge of the first chip body 31, and can be specifically arranged according to the shape of the chip element, so as to better support the filter chip 30.

[0083] In some embodiments, the distance that the extension area 52 extends outward from the support area 51 is greater than or equal to 50um, so as to effectively increase the difficulty of the plastic material of the plastic layer 80 breaking through the support part 50 and entering the cavity structure 61 during plastic sealing, thereby effectively ensuring that the filter chip 30 can achieve a good filtering function. Exemplarily, when the number of filter chips 30 includes at least two, two adjacent filter chips 30 are arranged at intervals, and part of the support part 50 is located in the gap area 92 between the two adjacent filter chips 30 (see Figure 5 ), the support portion 50 located in the gap area 92 is conducive to reducing the concave depth of the isolation layer 70 at the gap area 92 along the first direction. When the width of the isolation layer 70 at the gap area 92 (the width along the arrangement direction of two adjacent filter chips 30) or n is constant, the reduction in the concave depth of the isolation layer 70 at the gap area 92 along the first direction can reduce the aspect ratio of the isolation layer 70 at the gap area 92 (the ratio of the concave depth to the width of the isolation layer 70 at the gap area 92), so that when processing the isolation layer 70, it is less likely to generate bubbles or gaps at the bottom of the isolation layer 70 at the gap area 92, thereby ensuring that during the plastic sealing process, the plastic sealing material of the plastic sealing layer 80 is less likely to enter the cavity structure 61 from the connection between the isolation layer 70 and the support portion 50 at the gap area 92, further providing a guarantee for the filter chip 30 to achieve a good filtering function. The distance that the extension area 52 extends outward from the support area 51 is greater than or equal to 50um, which can effectively reduce the aspect ratio of the isolation layer 70 located in the gap area 92, and further make it less likely to generate bubbles or gaps at the bottom of the isolation layer 70 in the gap area 92 when processing the isolation layer 70.

[0084] See also Figure 2 In some embodiments, the extension region 52 includes an extension sub-region 521 located at the spacing region 91, and the extension sub-region 521 is spaced apart from the non-filter chip 40; the solder resist layer 20 includes a solder resist sub-region 23 located at the spacing region 91, and the distance between the extension sub-region 521 and the non-filter chip 40 is greater than the distance between the solder resist sub-region 23 and the non-filter chip 40. That is, the support portion 50 located at the spacing region 91 is farther away from the non-filter chip 40 than the solder resist layer 20 located at the spacing region 91, so that the plastic sealing material of the plastic sealing layer 80 is easier to break through the isolation layer 70 to form the connecting port 71 during the plastic sealing process, so that the plastic sealing material is easier to enter the gap 62 between the non-filter chip 40 and the substrate 10.

[0085] See also Figure 3 and Figure 4 In some embodiments, the number of filter chips 30 includes a plurality, and each filter chip 30 is provided with a corresponding support portion 50; when the spacing distance between two adjacent filter chips 30 is less than or equal to a preset threshold, the support portions 50 of the two adjacent filter chips 30 are connected. That is to say, when the spacing distance between two adjacent filter chips 30 is less than or equal to a preset threshold, the support portions 50 of the two adjacent filter chips 30 are connected together to reduce the concave depth of the portion of the isolation layer 70 at the gap area 92 (i.e., the isolation layer 70 located at the gap area 92) along the first direction, and when processing the isolation layer 70, the probability of bubbles or gaps being generated at the bottom of the isolation layer 70 at the gap area 92 can also be reduced. For example, the support portion 50 corresponding to the filter chip 30a is connected to the support portion 50 corresponding to the filter chip 30b.

[0086] See also Figure 3 and Figure 4In some embodiments, the number of filter chips 30 includes a plurality, and each filter chip 30 is provided with a support portion 50; when the spacing distance between two adjacent filter chips 30 is greater than a preset threshold, the support portions 50 of the two adjacent filter chips 30 are arranged at intervals. Exemplarily, the substrate 10 has a first surface and a second surface opposite to each other, the solder resist layer 20 covers the first surface and the second surface, and the solder resist layer 20 exposes the substrate 10 at a required position; the support portion 50 is arranged on the first surface. The solder resist layer 20 and the support portion 50 on the side where the first surface is located have a first weight, and the solder resist layer 20 on the side where the second surface is located has a second weight. The support portions 50 of the two adjacent filter chips 30 are arranged at intervals, that is, the support portions 50 of the two adjacent filter chips 30 are disconnected, which can reduce the material usage of the support portion 50, which is conducive to minimizing the difference between the first weight and the second weight as much as possible, thereby preventing the substrate 10 from warping as much as possible. For example, the support portion 50 corresponding to the filter chip 30c is arranged at intervals from the support portion 50 corresponding to the filter chip 30d. The preset threshold can be set according to actual needs and is not limited here.

[0087] See also Figure 3 In some embodiments, a portion of the solder resist layer 20 corresponding to the filter chip 30 is formed with a slot 24, and the slot 24 is arranged opposite to the first chip body 31 of the filter chip 30. In this way, even if a part of the material of the support portion 50 or the molding material of the molding layer 80 enters the cavity structure 61 during the molding process when the support portion 50 is set, the setting of the slot 24 can play a blocking or buffering role, and the material entering the cavity structure 61 can flow into the slot 24, thereby minimizing the influence of the material entering the cavity structure 61 on the filter chip 30; the portion of the solder resist layer 20 corresponding to the filter chip 30 is formed with a slot 24, which can also reduce the area and material usage of the solder resist layer 20, which is beneficial to reduce the difference between the first weight and the second weight, thereby facilitating the prevention of warping of the substrate 10. For example, when the material of the support portion 50 includes a glue material, part of the glue material may enter the cavity structure 61 uncontrollably when the support portion 50 is set, and the setting of the slot 24 can play a partial blocking role. For another example, during the plastic encapsulation process, a small amount of the plastic encapsulation material of the plastic encapsulation layer 80 breaks through the isolation layer 70 and enters the cavity structure 61, and the slots 24 can also play a certain buffering role, thereby preventing the plastic encapsulation material from going deeper into the cavity structure 61 and contacting the chip components, causing the filter chip 30 to fail. The number of slots 24 can be designed according to actual needs, such as one, two, three or more. When the number of slots 24 includes multiple, the shapes and / or sizes of different slots 24 can be the same or different.

[0088] See also Figure 5The embodiment of the present application also provides a chip packaging structure 100, including a substrate 10, a solder resist layer 20, a filter chip 30, a support portion 50, an isolation layer 70 and a plastic sealing layer 80, wherein the solder resist layer 20 is arranged on the substrate 10, and the solder resist layer 20 is formed with a first window 21; the filter chip 30 is installed on the substrate 10 through the first window 21; the support portion 50 is arranged on the side of the solder resist layer 20 away from the substrate 10, and a cavity structure 61 is formed between the filter chip 30, the support portion 50 and the substrate 10; the distance between the surface of the support portion 50 away from the substrate 10 and the substrate 10 is smaller than the distance between the surface of the filter chip 30 close to the substrate 10 and the substrate 10; the isolation layer 70 covers the filter chip 30. The filter chip 30 and the support part 50 are provided; the plastic encapsulation layer 80 encapsulates the filter chip 30 on the substrate 10, and the isolation layer 70 isolates the plastic encapsulation layer 80 from the outside of the filter chip 30; wherein the support part 50 can at least partially contact with the bottom surface of the filter chip 30 to support the filter chip 30; the number of the filter chips 30 includes at least two, and the two adjacent filter chips 30 are arranged at intervals; part of the support part 50 is located in the gap area 92 between the two adjacent filter chips 30, the distance from the surface of the filter chip 30 away from the substrate 10 to the surface of the support part 50 away from the substrate 10 is m, the spacing distance between the two adjacent filter chips 30 is n, and the ratio of m to n is less than 2.

[0089] In the chip packaging structure 100 of the above embodiment, since the support portion 50 can at least partially contact the bottom surface of the filter chip 30, the support portion 50 can support the filter chip 30, so that the support portion 50 can buffer or release the stress on the filter chip 30 to a certain extent, thereby protecting the filter chip 30, reducing the probability of the filter chip 30 collapsing and causing the filter chip 30 to fail, improving the connection reliability between the filter chip 30 and the substrate 10, and thus improving the reliability of the chip packaging structure 100. Secondly, a cavity structure 61 can be formed between the filter chip 30 and the substrate 10 to achieve a good filtering function. The isolation layer 70 covers the filter chip 30, the non-filter chip 40 and the support part 50, so that the isolation layer 70 can protect the filter chip 30 and the non-filter chip 40 during the plastic packaging process; and can prevent the plastic packaging material of the plastic packaging layer 80 from damaging at least one of the support part 50 and the solder resist layer 20 and entering the cavity structure 61 during the plastic packaging process, and can prevent the plastic packaging material of the plastic packaging layer 80 from entering the cavity structure 61 through the connection between the support part 50 and the filter chip 30, thereby increasing the difficulty of the plastic packaging material used in the plastic packaging layer 80 entering the cavity structure 61, thereby providing a guarantee for the filter chip 30 to achieve a good filtering function. In addition, since part of the support part 50 is located in the gap area 92 between two adjacent filter chips 30, the support part 50 located in the gap area 92 can increase the difficulty of the plastic packaging material of the plastic packaging layer 80 breaking through the support part 50 and entering the cavity structure 61 during packaging, thereby further ensuring that the filter chip 30 can achieve a good filtering function.

[0090] In addition, since part of the supporting portion 50 is located in the gap area 92 between two adjacent filter chips 30, the distance from the surface of the filter chip 30 away from the substrate 10 to the surface of the supporting portion 50 away from the substrate 10 is m, and the spacing distance between the two adjacent filter chips 30 is n, and the ratio of m to n is less than 2, the depth of the concave portion of the isolation layer 70 along the first direction in the gap area 92 can be effectively reduced. When the width of the isolation layer 70 located in the gap area 92 (the width along the arrangement direction of the two adjacent filter chips 30) or n is constant, the reduction in the concave portion of the isolation layer 70 in the gap area 92 along the first direction can effectively reduce the aspect ratio of the portion of the isolation layer 70 in the gap area 92 (the ratio of the concave portion of the isolation layer 70 located in the gap area 92 to the width), so that when processing the isolation layer 70, it is less likely to produce bubbles or voids at the bottom of the isolation layer 70 in the gap area 92. It can be understood that if there are bubbles or gaps at the bottom of the isolation layer 70 after the isolation layer 70 covers the filter chip 30 and the support part 50, when the ambient temperature or processing temperature of the semi-finished product or the finished product changes, such as during the plastic sealing process or when the temperature of the semi-finished product or the finished product changes during the use of the chip packaging structure 100, the bubbles or gaps at the bottom of the isolation layer 70 will become larger due to thermal expansion and contraction, thereby causing the isolation layer 70 to easily fit poorly with the dielectric layer (such as the support part 50 or the solder resist layer 20) to which it is attached, and thus causing the isolation layer 70 to easily detach.

[0091] See also Figure 6 and Figure 7 , Figure 6 It is a schematic diagram of a chip packaging structure of a comparative example after processing the isolation layer. The chip packaging structure is only provided with a solder resist layer 70 , and no supporting portion 50 is provided. Figure 7 1 is a schematic diagram of a chip packaging structure 100 provided in an embodiment of the present application after processing an isolation layer 70 . The chip packaging structure 100 is provided with both a solder resist layer 20 and a support portion 50 . Figure 6 The width of the gap region between the filter chip 30a and the filter chip 30e in FIG. Figure 7 The width of the gap region 92 (the region between the filter chip 30a and the filter chip 30e) in the filter chip 30a is the same. Figure 6 It can be seen from the figure that after the isolation layer 70 is processed, i.e., after the film is coated, there are obvious bubbles 200 at the bottom of the isolation layer 70 in the gap area E; Figure 7 It can be seen that after the isolation layer 70 is processed, i.e., after lamination, there are no bubbles at the bottom of the isolation layer 70 in the gap area 92. Therefore, it can be seen that the chip packaging structure 100 in the embodiment of the present application, the support portion 50 is provided in the gap area 92, which can reduce the generation of bubbles or gaps at the bottom of the isolation layer 70 in the gap area 92 when processing the isolation layer 70.

[0092] Exemplarily, the substrate 10 includes the substrate 10 of any of the above-mentioned embodiments. The solder resist layer 20 includes the solder resist layer 20 of any of the above-mentioned embodiments. The filter chip 30 includes the filter chip 30 of any of the above-mentioned embodiments. The isolation layer 70 includes the isolation layer 70 of any of the above-mentioned embodiments. The plastic encapsulation layer 80 includes the plastic encapsulation layer 80 of any of the above-mentioned embodiments. The chip packaging structure 100 includes the chip packaging structure 100 of any of the above-mentioned embodiments.

[0093] In some embodiments, the support portion 50 includes a support area 51 and an extension area 52. The support area 51 can contact the filter chip 30 to support the filter chip 30. The support area 51 is provided with a hollow window for forming a cavity structure 61. The projection of the support area 51 on the substrate 10 overlaps with the projection of the filter chip 30 on the substrate 10. The first chip body 31 of the filter chip 30, the support area 51, and the solder resist layer 20 are arranged in sequence along the first direction. The extension area 52 extends from the support area 51 in a direction away from the hollow window. The projection of the extension area 52 on the substrate 10 is located outside the projection of the filter chip 30 on the substrate 10. The support area 51 can buffer or release the stress on the filter chip 30, thereby reducing the probability that the filter chip 30 is prone to collapse and causes the filter chip 30 to fail, and improving the reliability of the chip packaging structure 100. The setting of the extended area 52 enables a part of the support portion 50 to be located on the outside of the filter chip 30, which can act as a height buffer and provide a certain degree of protection for the isolation layer 70, thereby preventing the isolation layer 70 from breaking at the edge of the filter chip 30 due to a large height difference during the formation of the isolation layer 70 or during plastic sealing, thereby causing the plastic sealing material used in the plastic sealing layer 80 to enter the cavity structure 61 of the filter chip 30.

[0094] In some embodiments, the distance that the support region 51 extends toward the cavity structure 61 is greater than or equal to 5 um. If the distance that the support region 51 extends toward the cavity structure 61 is too small, the effect of the support portion 50 supporting the filter chip 30 is not good. If the distance that the support region 51 extends toward the cavity structure 61 is greater than or equal to 5 um, the support portion 50 can well support the filter chip 30, thereby effectively reducing the probability that the filter chip 30 is prone to collapse and causes the filter chip 30 to fail.

[0095] In some embodiments, the filter chip 30 includes a chip element, and the distance between the inner edge of the support area 51 and the chip element in the second direction parallel to the substrate 10 is greater than or equal to 20um. In this way, even if the support portion 50 is offset during processing or use, the support portion 50 is not likely to affect the working performance of the filter chip 30, making the processing of the chip packaging structure 100 easier. For example, in the first direction, Figure 1 The second direction is perpendicular to the first direction.

[0096] In some embodiments, the distance that the extension area 52 extends outward from the supporting area 51 is greater than or equal to 50um, so as to effectively increase the difficulty of the molding material of the molding layer 80 breaking through the supporting part 50 and entering the cavity structure 61 during molding, thereby effectively ensuring that the filter chip 30 can achieve a good filtering function; and can effectively reduce the depth-to-width ratio of the isolation layer 70 located in the gap area 92, further making it less likely to generate bubbles or gaps at the bottom of the isolation layer 70 in the gap area 92 when processing the isolation layer 70.

[0097] In some embodiments, when the spacing distance between two adjacent filter chips 30 is less than or equal to a preset threshold, the support portions 50 of the two adjacent filter chips 30 are connected. That is, when the spacing distance between two adjacent filter chips 30 is less than or equal to a preset threshold, the support portions 50 of the two adjacent filter chips 30 are connected to reduce the concave depth of the portion of the isolation layer 70 at the gap area 92 (i.e., the isolation layer 70 located at the gap area 92) along the first direction, and when processing the isolation layer 70, it can also reduce the probability of bubbles or gaps at the bottom of the isolation layer 70 at the gap area 92. For example, the support portion 50 corresponding to the filter chip 30a is connected to the support portion 50 corresponding to the filter chip 30b.

[0098] In some embodiments, when the spacing distance between two adjacent filter chips 30 is greater than a preset threshold, the support portions 50 of the two adjacent filter chips 30 are spaced apart. Exemplarily, the substrate 10 has a first surface and a second surface relative to each other, the solder resist layer 20 covers the first surface and the second surface, and the solder resist layer 20 exposes the substrate 10 at a desired position; the support portion 50 is provided on the first surface. The solder resist layer 20 and the support portion 50 on the side where the first surface is located have a first weight, and the solder resist layer 20 on the side where the second surface is located has a second weight. The support portions 50 of the two adjacent filter chips 30 are spaced apart, that is, the support portions 50 of the two adjacent filter chips 30 are disconnected, which can reduce the material usage of the support portion 50, which is conducive to minimizing the difference between the first weight and the second weight as much as possible, thereby preventing the substrate 10 from warping as much as possible. For example, the support portion 50 corresponding to the filter chip 30c is spaced apart from the support portion 50 corresponding to the filter chip 30d. The preset threshold can be set according to actual needs and is not limited here.

[0099] The embodiment of the present application also provides a chip packaging structure 100, including a substrate 10, a solder resist layer 20, a filter chip 30, an isolation layer 70 and a plastic sealing layer 80, wherein the solder resist layer 20 is arranged on the substrate 10, and a first window 21 is formed on the solder resist layer 20; the filter chip 30 is installed on the substrate 10 through the first window 21; the support portion 50 is arranged on the side of the solder resist layer 20 away from the substrate 10, and a cavity structure 61 is formed between the filter chip 30, the support portion 50 and the substrate 10; the isolation layer 70 covers the filter chip 30 and the support portion 50; the plastic sealing layer 80 encapsulates the filter chip 30 on the substrate 10, and the isolation layer 70 isolates the plastic sealing layer 80 from the outside of the filter chip 30; wherein the support portion 50 can at least partially contact with the bottom surface of the filter chip 30 to support the filter chip 30; the number of filter chips 30 includes at least two, and the two filter chips 30 are arranged at intervals; part of the support portion 50 is located in the gap area 92 between two adjacent filter chips 30.

[0100] In the chip packaging structure 100 of the above embodiment, since the support portion 50 can at least partially contact the bottom surface of the filter chip 30, the support portion 50 can support the filter chip 30, so that the support portion 50 can buffer or release the stress on the filter chip 30 to a certain extent, thereby protecting the filter chip 30, reducing the probability of the filter chip 30 collapsing and causing the filter chip 30 to fail, improving the connection reliability between the filter chip 30 and the substrate 10, and thus improving the reliability of the chip packaging structure 100. Secondly, a cavity structure 61 can be formed between the filter chip 30 and the substrate 10 to achieve a good filtering function. The isolation layer 70 covers the filter chip 30, the non-filter chip 40 and the support part 50, so that the isolation layer 70 can protect the filter chip 30 and the non-filter chip 40 during the plastic packaging process; and can prevent the plastic packaging material of the plastic packaging layer 80 from damaging at least one of the support part 50 and the solder resist layer 20 and entering the cavity structure 61 during the plastic packaging process, and can prevent the plastic packaging material of the plastic packaging layer 80 from entering the cavity structure 61 through the connection between the support part 50 and the filter chip 30, thereby increasing the difficulty of the plastic packaging material used in the plastic packaging layer 80 entering the cavity structure 61, thereby providing a guarantee for the filter chip 30 to achieve a good filtering function. In addition, since part of the support part 50 is located in the gap area 92 between two adjacent filter chips 30, the support part 50 located in the gap area 92 can increase the difficulty of the plastic packaging material of the plastic packaging layer 80 breaking through the support part 50 and entering the cavity structure 61 during packaging, thereby further ensuring that the filter chip 30 can achieve a good filtering function.

[0101] Exemplarily, the substrate 10 includes the substrate 10 of any of the above-mentioned embodiments. The solder resist layer 20 includes the solder resist layer 20 of any of the above-mentioned embodiments. The filter chip 30 includes the filter chip 30 of any of the above-mentioned embodiments. The isolation layer 70 includes the isolation layer 70 of any of the above-mentioned embodiments. The plastic encapsulation layer 80 includes the plastic encapsulation layer 80 of any of the above-mentioned embodiments. The chip packaging structure 100 includes the chip packaging structure 100 of any of the above-mentioned embodiments.

[0102] An embodiment of the present application also provides a radio frequency front-end module, comprising the chip packaging structure 100 of any one of the above embodiments.

[0103] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "mechanically coupled" and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements. The mechanical coupling or coupling of two components includes direct coupling and indirect coupling, for example, direct fixed connection, connection through a transmission mechanism, etc. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0104] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0105] The disclosure above provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0106] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific method steps, features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific method steps, features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0107] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A solder resist layer is provided on the substrate and is formed with a first opening and a second opening; A filter chip is mounted on the substrate through the first opening; a non-filter chip, mounted on the substrate through the second opening, and spaced apart from the filter chip; A support portion is provided on a side of the solder resist layer away from the substrate, and a cavity structure is formed between the filter chip, the support portion and the substrate; an isolation layer, covering the filter chip, the non-filter chip and the support portion, the isolation layer forming a communication port on the periphery of the non-filter chip, the communication port being connected to the second opening; A plastic encapsulation layer, wherein the plastic encapsulation layer encapsulates the filter chip and the non-filter chip on the substrate, the isolation layer isolates the plastic encapsulation layer from the filter chip, and a portion of the plastic encapsulation layer is disposed in a gap between the non-filter chip and the substrate; The support portion is at least partially in contact with the bottom surface of the filter chip to support the filter chip; and part of the support portion is located in a spacing area between the filter chip and the non-filter chip.

2. The chip packaging structure according to claim 1, characterized in that: The support portion comprises: a support area, contacting the filter chip to support the filter chip, the support area being provided with a hollow window for forming the cavity structure; a projection of the support area on the substrate overlaps with a projection of the filter chip on the substrate, and a first chip body of the filter chip, the support area, and the solder resist layer are arranged in sequence along a first direction perpendicular to the substrate; An extension area extends from the support area in a direction away from the hollow window, and a projection of the extension area on the substrate is located outside a projection of the filter chip on the substrate.

3. The chip packaging structure according to claim 2, characterized in that: The support area extends to the cavity structure by a distance greater than or equal to 5 um.

4. The chip packaging structure according to claim 2, characterized in that: The spacing distance between the supporting area and the first chip body of the filter chip is less than or equal to 10 um.

5. The chip packaging structure according to claim 2, characterized in that: The filter chip includes a chip element, and a spacing distance between the support area and the chip element in a second direction parallel to the substrate is greater than or equal to 20 um.

6. The chip packaging structure according to claim 2, characterized in that: The support region includes a protruding region extending toward the cavity structure.

7. The chip packaging structure according to claim 2, characterized in that: The extension area extends outward from the support area by a distance greater than or equal to 50 um.

8. The chip packaging structure according to claim 2, characterized in that: The extended area includes an extended sub-area located at the spacing area, and the extended sub-area is spaced apart from the non-filter chip; the solder resist layer includes a solder resist sub-area located at the spacing area, and the distance between the extended sub-area and the non-filter chip is greater than the distance between the solder resist sub-area and the non-filter chip.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The support portion includes at least one of the following: an ink layer and a deformable support portion.

10. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The number of the filter chips includes multiple ones, and each of the filter chips is correspondingly provided with the support part; when the interval distance between two adjacent filter chips is less than or equal to a preset threshold, the support parts of the two adjacent filter chips are connected.

11. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The number of the filter chips includes multiple ones, and each of the filter chips is correspondingly provided with the support part; when the interval distance between two adjacent filter chips is greater than a preset threshold, the support parts of the two adjacent filter chips are arranged at intervals.

12. The chip packaging structure according to any one of claims 1 to 8, characterized in that: A groove is formed in a portion of the solder resist layer corresponding to the filter chip.

13. A chip packaging structure, characterized in that: include: substrate; A solder resist layer is disposed on the substrate and is formed with a first opening; A filter chip is mounted on the substrate through the first opening; The support portion is arranged on a side of the solder resist layer away from the substrate, and a cavity structure is formed between the filter chip, the support portion and the substrate; the distance between the surface of the support portion away from the substrate and the substrate is smaller than the distance between the surface of the filter chip close to the substrate and the substrate; An isolation layer, covering the filter chip and the support portion; A plastic encapsulation layer, wherein the plastic encapsulation layer encapsulates the filter chip on the substrate, and the isolation layer isolates the plastic encapsulation layer from the filter chip; Wherein, the supporting portion is in at least partial contact with the bottom surface of the filter chip to support the filter chip; the number of the filter chips includes at least two, and two adjacent filter chips are arranged at intervals; part of the supporting portion is located in the gap area between two adjacent filter chips, the distance from the surface of the filter chip away from the substrate to the surface of the supporting portion away from the substrate is m, the interval distance between two adjacent filter chips is n, and the ratio of m to n is less than 2.

14. The chip packaging structure according to claim 13, characterized in that: The support portion comprises: a support area, contacting the filter chip to support the filter chip, the support area being provided with a hollow window for forming the cavity structure; a projection of the support area on the substrate overlaps with a projection of the filter chip on the substrate, and a first chip body of the filter chip, the support area, and the solder resist layer are arranged in sequence along a first direction; An extension area extends from the support area in a direction away from the hollow window, and a projection of the extension area on the substrate is located outside a projection of the filter chip on the substrate.

15. The chip packaging structure according to claim 14, characterized in that: The support area extends to the cavity structure by a distance greater than or equal to 5 um.

16. The chip packaging structure according to claim 14, characterized in that: The filter chip includes a chip element, and a spacing distance between an inner edge of the support area and the chip element in a second direction parallel to the substrate is greater than or equal to 20 um.

17. The chip packaging structure according to claim 14, characterized in that: The extension area extends outward from the support area by a distance greater than or equal to 50 um.

18. The chip packaging structure according to claim 13, characterized in that: When the spacing distance between two adjacent filter chips is less than or equal to a preset threshold, the support portions of the two adjacent filter chips are connected.

19. The chip packaging structure according to claim 13, characterized in that: When the spacing distance between two adjacent filter chips is greater than a preset threshold, the support portions of the two adjacent filter chips are spaced apart.

20. A chip packaging structure, characterized in that: include: substrate; A solder resist layer is disposed on the substrate and is formed with a first opening; A filter chip is mounted on the substrate through the first opening; A support portion is provided on a side of the solder resist layer away from the substrate, and a cavity structure is formed between the filter chip, the support portion and the substrate; An isolation layer, covering the filter chip and the support portion; A plastic encapsulation layer, wherein the plastic encapsulation layer encapsulates the filter chip on the substrate, and the isolation layer isolates the plastic encapsulation layer from the filter chip; Wherein, the support portion is in at least partial contact with the bottom surface of the filter chip to support the filter chip; the number of the filter chips includes at least two, and the two filter chips are arranged at intervals; part of the support portion is located in the gap area between two adjacent filter chips.

21. A radio frequency front-end module, characterized in that: Comprising the chip packaging structure as described in any one of claims 1-20.

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