Single-mode low-resistance vertical-cavity surface-emitting semiconductor laser

Abstract

The utility model relates to the field of semiconductor lasers, in particular to a single-mode and low-resistance vertical cavity surface emitting semiconductor laser, which comprises a substrate, an epitaxial structure is grown on the substrate, and the epitaxial structure comprises a bottom distributed bragg reflector (DBR) layer, a mode control layer, a spacing layer, a top DBR layer and an ohmic contact layer from bottom to top. A current limiting layer and an active layer are arranged in the spacer layer, a through hole is etched in the position, corresponding to a fundamental mode, of the mode control layer, the mode control layer absorbs a high-order mode through high doping, a bottom contact electrode grows on the mode control layer, and a top contact electrode grows on the ohmic contact layer. According to the VCSEL, the absorption of a high-order mode is realized through the mode control layer, the aperture of the current limiting hole can be properly increased, the series resistance of the VCSEL is reduced, and the output power of the VCSEL is improved. As the internal current of the VCSEL does not pass through the bottom DBR layer, the series resistance of the VCSEL can be further reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductor lasers, and in particular relates to a single-mode, low-resistance vertical cavity surface emitting semiconductor laser. Background Art

[0002] Vertical-Cavity Surface-Emitting Laser (VCSEL) was first proposed by Professor Iga of Tokyo Institute of Technology in Japan in 1977. Different from traditional edge-emitting semiconductor lasers, the epitaxial structure of VCSEL mainly includes upper and lower distributed multilayer Bragg reflectors (Distributed Bragg Reflector, DBR), conductive confinement area, active area and semiconductor substrate, etc. The feedback of the top / bottom DBR makes the laser beam in the cavity emit in the direction perpendicular to the substrate. VCSEL has many advantages such as low threshold current, circular spot, high modulation bandwidth, single longitudinal mode lasing, easy to realize high-density two-dimensional array, and low production cost. VCSEL has a wide range of applications in many fields, such as optical switching, optical storage, all-optical information conversion, three-dimensional sensing, laser printing, laser display, laser lighting, automotive electronics, laser processing, consumer electronics, atomic sensing, lidar, etc.

[0003] The DBR structure of VCSEL is formed by alternating dozens of cycles of two materials with large energy band differences. Due to the low single-photon gain of VCSEL, the top / bottom DBR structure needs to achieve a sufficiently high reflectivity to enable the device to be lasered at low current. Generally, the top DBR structure requires 22~25 cycles, and the bottom DBR structure requires 32~40 cycles. As a result, the series resistance of the VCSEL structure itself is already large (about 80~100Ω), causing serious heating of the VCSEL, thereby reducing the performance of the VCSEL. In order to achieve the lasing characteristics of the fundamental transverse mode, a common method for VCSEL is to suppress high-order modes by making a current limiting hole with a smaller aperture (≤3μm). The current limiting aperture with a smaller aperture will further increase the overall series resistance of the VCSEL, thereby increasing the heat generation of the VCSEL, and the power and efficiency of the VCSEL will decrease, and high-power single-mode output cannot be achieved; at the same time, high resistance causes the operating temperature of the VCSEL to increase, which is not conducive to reliability and reduces the practical life.

[0004] Due to the special circularly symmetric waveguide of VCSEL, the polarization modes in two orthogonal directions are degenerate, and the structure itself does not have an effective polarization mode control structure. Therefore, as the injected carrier concentration, temperature and other conditions change, the polarization of its output will switch, which is not conducive to stability. Generally, an asymmetric (such as rectangular, diamond, dumbbell, etc.) VCSEL table can be defined by etching, and then an internal asymmetric (such as rectangular, diamond, dumbbell, etc.) current limiting hole is formed by oxidation to control the polarization mode. However, the asymmetric current limiting hole will also change the output spot of the VCSEL from a circular shape to an asymmetric shape, which is also not conducive to the later packaging requirements such as beam coupling and shaping. Utility Model Content

[0005] In view of this, the utility model aims to provide a single-mode, low-resistance vertical cavity surface emitting semiconductor laser to solve the technical problem that reducing the aperture of the current limiting hole will increase the VCSEL series resistance and cannot achieve high-power single-mode output.

[0006] In order to achieve the above-mentioned purpose, the technical solution created by the utility model is implemented as follows:

[0007] A single-mode, low-resistance vertical cavity surface emitting semiconductor laser comprises a substrate, an epitaxial structure is grown on the substrate, the epitaxial structure comprises from bottom to top a bottom DBR layer, a mode control layer, a spacer layer, a top DBR layer and an ohmic contact layer, a current limiting layer and an active layer located below the current limiting layer are arranged in the spacer layer, the band gap of the spacer layer is larger than the band gap of the active layer, a through hole is etched at a position corresponding to a base mode in the mode control layer, the mode control layer realizes absorption of a high-order mode by high doping, a bottom contact electrode is grown on the mode control layer, and a top contact electrode is grown on the ohmic contact layer.

[0008] Furthermore, the high doping of the mode control layer is N-type doping with a doping concentration of 1e 19 ~1e 20 / cm 3 .

[0009] Furthermore, the through hole is in a rhombus, rectangle or ellipse shape.

[0010] Furthermore, the aperture of the through hole is smaller than the aperture of the current limiting hole of the current limiting layer.

[0011] Furthermore, the top DBR layer is a P-type doped DBR structure, and the bottom DBR layer is an N-type doped DBR structure or an undoped DBR structure.

[0012] A single-mode, low-resistance vertical cavity surface emitting semiconductor laser comprises a substrate, an epitaxial structure is grown on the substrate, the epitaxial structure comprises from bottom to top a bottom DBR layer, a mode control layer, a spacer layer, and a top DBR layer, a current limiting layer and an active layer located below the current limiting layer are arranged in the spacer layer, the band gap of the spacer layer is larger than the band gap of the active layer, a through hole is etched at a position of the mode control layer corresponding to a base mode, the mode control layer realizes absorption of a high-order mode by high doping, a bottom contact electrode is grown on the mode control layer, an ohmic contact layer is grown on the spacer layer, and a top contact electrode is grown on the ohmic contact layer.

[0013] Furthermore, the high doping of the mode control layer is N-type doping with a doping concentration of 1e 19 ~1e 20 / cm 3 .

[0014] Furthermore, the through hole is in a rhombus, rectangle or ellipse shape.

[0015] Furthermore, the aperture of the through hole is smaller than the aperture of the current limiting hole of the current limiting layer.

[0016] Furthermore, the top DBR layer is a dielectric film structure formed by alternating growth of a high refractive index dielectric film and a low refractive index dielectric film, and the material of the low refractive index dielectric film is SiO 2 or Al 2 O 3 , the material of high refractive index dielectric film is Si, Ta 2 O 5 or Nb 2 O 5 , the bottom DBR layer is an N-type doped DBR structure or an undoped DBR structure.

[0017] Compared with the prior art, the invention can achieve the following beneficial effects:

[0018] (1) By setting a mode control layer to absorb high-order modes, the aperture of the current limiting hole can be appropriately increased, the series resistance of the VCSEL can be reduced, and the upper limit of the output power of the VCSEL can be increased. Since the mode control layer also serves as the contact layer of the bottom contact electrode, the internal current of the VCSEL does not pass through the bottom DBR layer, so the series resistance of the VCSEL can be further reduced.

[0019] (2) The top contact electrode and the top DBR are arranged in the same layer, so that the internal current of the VCSEL does not pass through the top DBR layer and the bottom DBR layer, further reducing the series resistance of the VCSEL.

[0020] (3) Since the current does not pass through the bottom DBR layer, the bottom DBR layer can be an undoped DBR structure, which can further reduce the loss of the VCSEL and help improve efficiency and power.

[0021] (4) The mode control layer can introduce a mode loss difference between the two orthogonal polarization modes in the VCSEL cavity by etching asymmetric through holes, so that one of the polarization modes is always suppressed in the competition, so that the mode output by the VCSEL is a single polarization mode. And because the current limiting hole is still circular, the spot shape of the VCSEL output is still circular, which meets the packaging requirements of later beam coupling, shaping, etc.

[0022] (5) Since the mode control layer is in the resonant cavity of the VCSEL, the mode control layer has a strong coupling efficiency. Compared with the traditional single-polarization VCSEL using surface relief, the utility model can introduce a larger loss difference between the two polarization modes and obtain a higher polarization suppression ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0024] Figure 1 This is a schematic structural diagram of the single-mode, low-resistance vertical cavity surface emitting semiconductor laser described in Example 1 of the utility model;

[0025] Figure 2 Schematic diagrams of three shapes of through holes etched out of the mode control layer described in Example 1 of the utility model;

[0026] Figure 3 This is a schematic structural diagram of the single-mode, low-resistance vertical cavity surface emitting semiconductor laser described in Example 2 of the present utility model.

[0027] Description of reference numerals:

[0028] Substrate 100 , bottom DBR layer 101 , mode control layer 102 , spacer layer 103 , active layer 104 , current confinement layer 105 , top DBR layer 106 , ohmic contact layer 107 , insulating layer 108 , top contact electrode 109 , bottom contact electrode 110 . DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the utility model creation more clear, the utility model creation is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model creation and do not constitute a limitation of the utility model creation.

[0030] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0031] In the description of the invention of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the invention of the utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the invention of the utility model. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the invention of the present utility model, unless otherwise specified, "multiple" means two or more.

[0032] In the description of the invention of the utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention of the utility model can be understood according to specific circumstances.

[0033] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0034] Example 1

[0035] like Figure 1As shown, the utility model invention embodiment 1 provides a single-mode, low-resistance vertical cavity surface emitting semiconductor laser, including a substrate 100 and an epitaxial structure grown on the substrate 100, the epitaxial structure includes a bottom DBR layer 101, a mode control layer 102, a spacer layer 103, a top DBR layer 106, and an ohmic contact layer 107 grown in sequence on the substrate 100, a current limiting layer 105 and an active layer 104 are arranged in the spacer layer 103, the active layer 104 is located below the current limiting layer 105, a bottom contact electrode 110 is grown on the mode control layer, a top contact electrode 109 is grown on the ohmic contact layer 107, a resonant cavity of the VCSEL is formed between the bottom DBR layer 101 and the top DBR layer 106, and an insulating layer 108 is prepared on the side of the resonant cavity.

[0036] The substrate 100 may be a III-V semiconductor material such as GaAs, InP, GaSb, etc., which is specifically selected according to the output wavelength.

[0037] The bottom DBR layer 101 is a multi-period DBR structure in which high / low refractive index semiconductor materials are alternately grown, and the thickness of each layer is grown according to one quarter of the optical thickness.

[0038] The spacer layer 103 is made of a material that matches the lattice of the substrate 100 . The spacer layer 103 is distributed on the upper and lower sides of the active layer 104 to adjust the cavity length of the VCSEL.

[0039] The active layer 104 is an active region structure composed of a multi-quantum well structure, which is used to generate the optical gain required for forming a laser. The band gap of the spacer layer 103 is larger than the band gap of the quantum well, forming a limiting effect on carriers.

[0040] The current limiting layer 105 forms a current limiting hole through lateral oxidation to limit the injected current path and increase the carrier density in the active layer 104 region.

[0041] The top DBR layer 106 is a multi-period DBR structure of alternating high / low refractive index semiconductor materials, and the thickness of each layer is grown according to one-quarter of the optical thickness. The VCSEL provided by the utility model is a top emission structure, so the reflectivity of the top DBR layer 106 is less than the reflectivity of the bottom DBR layer 101, so that the laser is emitted from the top DBR layer 106.

[0042] The ohmic contact layer 107 is a P-type highly doped semiconductor contact layer, which is used to reduce the Schottky barrier between the metal / semiconductor interface to achieve ohmic contact.

[0043] The top contact electrode 109 and the bottom contact electrode 110 serve as the anode and cathode of the VCSEL, respectively.

[0044] The improvement of the present invention lies in the setting of the mode control layer 102. The mode control layer 102 is a highly doped semiconductor material. The higher the doping concentration of the semiconductor material, the better its conductivity, but it also increases its absorption loss of light. Therefore, the central area of ​​the mode control layer 102 is etched to form a through hole to avoid loss to the fundamental mode. The unetched area of ​​the mode control layer 102 is the overlapping area of ​​the high-order mode, which can absorb the high-order mode. The essence of the present invention is to increase the loss difference between the fundamental mode and the high-order mode and filter out the high-order mode. The degree of overlap with the high-order mode is controlled by adjusting the size of the through hole etched in the center of the mode control layer 102.

[0045] The mode control layer 102 is equivalent to an aperture that can absorb light waves, and because the mode control layer 102 is placed in the resonant cavity of the VCSEL, the reciprocating standing waves have a high coupling efficiency with the mode control layer 102. The mode control layer 102 has a strong absorption coefficient for the light waves in the resonant cavity, which increases the loss of high-order modes and makes the high-order modes suppressed in the mode competition with the fundamental mode.

[0046] Since the utility model adds a mode control layer 102 in the resonant cavity, the aperture of the current limiting hole of the current limiting layer 105 of the VCSEL itself can be appropriately enlarged. Increasing the aperture of the current limiting hole can reduce the series resistance of the VCSEL and increase the upper limit of the output power of the VCSEL. Since increasing the aperture of the current limiting hole will also introduce more high-order modes, especially under high current density injection, the device working mode is multi-transverse mode lasing, but through the setting of the mode control layer 102, a strong mode absorption is introduced into the high-order mode to suppress the multi-transverse mode lasing under the condition of large current aperture.

[0047] In addition, the carriers injected through the VCSEL positive electrode (top contact electrode 109) will have an uneven concentration distribution at the current limiting hole, and the carriers accumulated at the edge of the aperture are prone to produce higher-order mode lasing. Due to the addition of the mode control layer 102, it is not necessary to control the aperture of the current limiting hole within a very small range to achieve fundamental mode output. Therefore, the current limiting hole with a larger aperture will greatly weaken the uneven current distribution at the aperture. At the same time, the closer to the edge of the aperture, the stronger the absorption effect of the mode control layer 102 on the high-order mode.

[0048] Since the mode control layer 102 is a highly doped semiconductor material, the mode control layer 102 can also serve as a contact layer for the negative electrode of the VCSEL (ie, the bottom contact electrode 110 ), so that the internal current of the VCSEL does not pass through the bottom DBR layer 101 , thereby greatly reducing the series resistance of the VCSEL.

[0049] Since the current does not pass through the bottom DBR layer 101, the bottom DBR layer 101 can adopt an undoped DBR structure, which can further reduce the loss of the VCSEL and help improve the efficiency and power.

[0050] The utility model customizes the shape of the through hole etched in the mode control layer 102, so that the VCSEL has single-mode, low-resistance characteristics and single-polarization characteristics. Figure 2 As shown, the etched through hole is an asymmetric shape such as a rectangle, a diamond or an ellipse with different lengths in two orthogonal directions of the VCSEL, which can introduce a mode loss difference between the two orthogonal polarization modes in the VCSEL cavity, so that one of the polarization modes is always in a suppressed state in the competition, so that the mode output by the VCSEL is a single polarization mode.

[0051] Since the current limiting hole is still circular, the spot shape of the VCSEL output is still circular, which meets the subsequent packaging requirements such as beam coupling and shaping.

[0052] Since the mode control layer 102 is in the resonant cavity of the VCSEL, the mode control layer 102 has a strong coupling efficiency. Compared with the traditional single-polarization VCSEL using surface relief, the utility model can introduce a larger loss difference between the two polarization modes and obtain a higher polarization suppression ratio.

[0053] The VCSEL structure provided in Example 1 of the present invention is applicable to a variety of semiconductor substrates, such as GaN, InP, GaAs, GaSb, etc., and the wavelength band can cover visible light, near infrared, mid-infrared, etc. Taking the commonly used 850nm VCSEL as an example, its preparation method is described, which specifically includes the following steps:

[0054] S1. AlxGa1-xAs semiconductor materials with high and low Al components are alternately epitaxially grown on an N-type GaAs substrate 100 using MOCVD, wherein the high Al component x=0.9~1, the low Al component x=0.1~0, and the typical number of periods is about 35~40 periods. The thickness of each layer is grown according to one-quarter of the optical thickness of the material, and finally an N-type DBR layer 101 with a reflectivity of more than 99.9% is formed.

[0055] S2. Epitaxially grow the mode control layer 102. The material of the mode control layer 102 is AlxGa1-xAs that matches the GaAs substrate lattice. Considering the problem that high Al components are easily oxidized, the Al component of the mode control layer 102 can be controlled to be x=0~0.1. At the same time, the mode control layer 102 serves as a high-order mode absorption layer and an electrode injection layer. In order to achieve stronger absorption and lower resistance, the doping concentration of this layer can be N-type doped 1e 19 ~1e 20 / cm 3 The middle area of ​​the mode control layer 102 is removed by ICP dry etching or wet etching with a corrosive solution, so that the fundamental mode of the VCSEL is not affected by the absorption of the mode control layer 102, thereby improving the mode gain of the fundamental mode.

[0056] S3 . Epitaxially grow a portion of the spacer layer 103 , the material of the spacer layer 103 being lattice matched with the GaAs substrate 100 .

[0057] S4. Epitaxial growth of active layer 104, 850nm typical quantum well structure with GaAs / Al x Ga 1-x As, x = 0.2 ~ 0.4, by adjusting the thickness of the quantum well or the Al component of the barrier, the light emission band of the active layer 104 can be adjusted to cover 850nm. Continue to grow the remaining part of the spacer layer 103, and when it reaches a specific thickness, epitaxially grow Al with a high aluminum component. x Ga 1-x As the current limiting layer 105, generally the current limiting layer 105 is located at the node of the light wave in the resonant cavity, which can effectively reduce the absorption loss. Typically, x=0.98~1.

[0058] S5. Epitaxially grow the remaining portion of the spacer layer 103 so that the overall optical thickness of the spacer layer 103, the active layer 104 and the current confinement layer 105 is half a wavelength which is an integer multiple of the wavelength of 850 nm, thereby satisfying the standing wave condition of the laser.

[0059] S6. Growth of P-type DBR layer 106, Al with high and low Al components x Ga 1-x The thickness of each layer of As semiconductor material is grown according to one-fourth of the optical thickness of the material. Typically, high Al component x=0.9~1, low Al component x=0.1~0, and the typical number of periods is about 20~25 periods. The reflectivity of the P-type DBR layer 106 is lower than the reflectivity of the bottom N-type DBR layer 101, so that the laser is emitted from the top.

[0060] S7. Grow a P-type highly doped ohmic contact layer 107 to reduce the Schottky barrier generated by the contact between the metal electrode and the semiconductor, form an ohmic contact, and reduce resistance.

[0061] Steps S1 to S7 are the epitaxial growth part of the VCSEL. After the epitaxial growth part of the VCSEL is completed, the next steps are steps S8 to S14 which are the preparation process links.

[0062] S8. First, the sample prepared in steps S1 to S7 is coated, photolithographically processed, and developed to form a VCSEL mask pattern. The VCSEL mesa is dry-etched using an ICP etching device until the sidewall of the current limiting layer 105 is exposed. The typical Cl 2 / BCl 3 / Ar to achieve this.

[0063] S9. Use wet nitrogen oxidation equipment to perform transverse oxidation on the current limiting layer 105. Control the oxidation rate by adjusting parameters such as oxidation temperature, water vapor temperature, pressure, flow rate, and control the transverse oxidation depth by controlling time. Eventually, a current limiting hole that is not oxidized in the center is formed, and the oxidized part forms a high resistance area. The current injected into the laser will be limited to pass through the current limiting hole.

[0064] S10. Perform secondary photolithography on the sample with the current limiting hole, and form the two-table mask pattern of VCSEL after the steps of coating, photolithography and development. Use ICP etching equipment to dry-etch the VCSEL table until the mode control layer is exposed. The etching gas can be a typical GaAs material system gas Cl 2 / BCl 3 / Ar to achieve this.

[0065] S11. Use PECVD equipment to deposit an insulating layer 108 on the side of the sample. A typical material may be SiO 2 Or Si 3 N 4 , thickness is 300~500nm.

[0066] S12. The sample is subjected to three photolithography steps, and the surfaces of the mode control layer 102 and the ohmic contact layer 107 are exposed after the steps of coating, photolithography, and development. The exposed surfaces of the mode control layer 102 and the ohmic contact layer 107 are dry-etched using an RIE device. A typical SiO 2 Or Si 3 N 4 The etching gas can be selected as CF 4 / O 2 .

[0067] S13. The sample is subjected to the fourth photolithography, and after the coating, photolithography, and development steps, a VCSEL is formed, and then the positive electrode is evaporated by electron beam evaporation or magnetron sputtering. The typical positive electrode material is Ti / Pt / Au. The sample after evaporation is subjected to the lift-off process in an acetone solution to remove the electrode portion that is not needed at the light outlet of the half VCSEL, and finally form the top contact electrode 109.

[0068] S14. The sample is subjected to the fifth photolithography, and after the coating, photolithography, and development steps, a VCSEL is formed, and then the negative electrode is evaporated by electron beam evaporation or magnetron sputtering. The typical negative electrode material is Au-Ge / Ni / Au. The sample after evaporation is subjected to a lift-off stripping process in an acetone solution to remove the electrode portion that is not needed at the light outlet of the half VCSEL, and finally form the bottom contact electrode 110.

[0069] After completing steps S1 to S14, the preparation of the base mode and low resistance VCSEL provided in the first embodiment of the present invention is completed.

[0070] Example 2

[0071] like Figure 3 As shown, the utility model invention embodiment 2 provides a single-mode, low-resistance vertical cavity surface emitting semiconductor laser, including a substrate 100 and an epitaxial structure grown on the substrate 100, the epitaxial structure including from bottom to top a bottom DBR layer 101, a mode control layer 102, a spacer layer 103, and a top DBR layer 106, a current limiting layer 105 and an active layer 104 located below the current limiting layer 105 are arranged in the spacer layer 103, a bottom contact electrode 110 is grown on the mode control layer 102, an ohmic contact layer 107 is grown on the spacer layer 103, and a top contact electrode 109 is grown on the ohmic contact layer 107.

[0072] The difference between Example 2 and Example 1 is that the top contact electrode 109 is prepared on the surface of the spacer layer 103, that is, the top contact electrode 109 and the top DBR layer 106 are arranged in the same layer, and the electrode contact of Example 2 is an inner cavity contact. The current is injected from the top contact electrode 109 to the bottom contact electrode 110. The overall current path does not pass through the top DBR layer 106 and the bottom DBR layer 101 of the VCSEL, which can further reduce the series resistance of the VCSEL.

[0073] Since the current does not pass through the top DBR layer 106, the top DBR layer 106 in Example 2 can adopt an insulating dielectric film structure to reduce the resistance of the original top DBR layer 106, thereby reducing the total resistance of the device in disguise. The dielectric film structure is arranged periodically according to two dielectric films with different refractive indices, high and low. The thickness of each layer is grown according to one-quarter of the optical thickness. The dielectric film material with a high refractive index is Si, Ta, 2 O 5 , Nb 2 O 5、 HkDJ 2 The low refractive index dielectric film material is SiO 2 、Al 2 O 3 wait.

[0074] The preparation process of the VCSEL provided in Example 2 is basically similar to that of Example 1. After completing the above steps S1 to S5 and S7, the epitaxial growth part of the VCSEL is completed. The subsequent preparation process of Example 2 is the same as steps S8 to S14 of Example 1. After completing step S14, the top DBR layer 106 is formed by electron beam evaporation of the dielectric film. The dielectric film materials with high and low refractive indices are alternately grown. Each layer is one-quarter of the wavelength optical thickness. The low refractive index dielectric film can be selected such as SiO 2 、Al 2 O 3 Etc.; High refractive index dielectric films such as Si, Ta 2 O 5 , Nb 2 O 5 wait.

[0075] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the utility model disclosure can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the utility model can be achieved, and this document does not limit this.

[0076] The above specific implementations do not constitute a limitation on the protection scope of the present utility model. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. A single-mode, low-resistance vertical cavity surface emitting semiconductor laser, comprising a substrate, characterized in that: An epitaxial structure is grown on the substrate, and the epitaxial structure includes, from bottom to top, a bottom DBR layer, a mode control layer, a spacer layer, a top DBR layer and an ohmic contact layer. A current limiting layer and an active layer located below the current limiting layer are arranged in the spacer layer, the band gap of the spacer layer is larger than the band gap of the active layer, a through hole is etched in the mode control layer at a position corresponding to the base mode, the mode control layer realizes absorption of high-order modes by high doping, a bottom contact electrode is grown on the mode control layer, and a top contact electrode is grown on the ohmic contact layer.

2. The single-mode, low-resistance vertical cavity surface emitting semiconductor laser according to claim 1, characterized in that: The high doping of the mode control layer is N-type doping.

3. The single-mode, low-resistance vertical cavity surface emitting semiconductor laser according to claim 1 or 2, characterized in that: The through hole is in the shape of a rhombus, a rectangle or an ellipse.

4. The single-mode, low-resistance vertical cavity surface emitting semiconductor laser according to claim 3, characterized in that: The aperture of the through hole is smaller than the aperture of the current limiting hole of the current limiting layer.

5. The single-mode, low-resistance vertical cavity surface emitting semiconductor laser according to claim 1, characterized in that: The top DBR layer is a P-type doped DBR structure, and the bottom DBR layer is an N-type doped DBR structure or an undoped DBR structure.

6. A single-mode, low-resistance vertical-cavity surface-emitting semiconductor laser comprising a substrate, characterized in that: An epitaxial structure is grown on the substrate, and the epitaxial structure includes, from bottom to top, a bottom DBR layer, a mode control layer, a spacer layer, and a top DBR layer. A current limiting layer and an active layer located below the current limiting layer are arranged in the spacer layer, the band gap of the spacer layer is larger than the band gap of the active layer, a through hole is etched in the mode control layer at a position corresponding to the base mode, the mode control layer realizes absorption of high-order modes by high doping, a bottom contact electrode is grown on the mode control layer, an ohmic contact layer is grown on the spacer layer, and a top contact electrode is grown on the ohmic contact layer.

7. The single-mode, low-resistance vertical cavity surface emitting semiconductor laser according to claim 6, characterized in that: The high doping of the mode control layer is N-type doping.

8. The single-mode, low-resistance vertical cavity surface emitting semiconductor laser according to claim 6 or 7, characterized in that: The through hole is in the shape of a rhombus, a rectangle or an ellipse.

9. The single-mode, low-resistance vertical cavity surface emitting semiconductor laser according to claim 8, characterized in that: The aperture of the through hole is smaller than the aperture of the current limiting hole of the current limiting layer.

10. The single-mode, low-resistance vertical cavity surface emitting semiconductor laser according to claim 6, characterized in that: The top DBR layer is a dielectric film structure formed by alternating growth of high-refractive index dielectric films and low-refractive index dielectric films, the material of the low-refractive index dielectric film is SiO2 or Al2O3, the material of the high-refractive index dielectric film is Si, Ta2O5 or Nb2O5, and the bottom DBR layer is an N-type doped DBR structure or an undoped DBR structure.

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