CPLD, FCT unlocking circuit of CPLD and control panel of power conversion circuit

Abstract

The utility model discloses a CPLD, an FCT unlocking circuit thereof and a control panel of a power conversion circuit, the CPLD comprises an FCT test circuit, and the FCT test circuit is used for performing an offline function test after unlocking; the FCT unlocking circuit comprises an enabling port, a clock port and a counting module, and the counting module is connected with the enabling port, the clock port and the FCT test circuit; and the counting module is used for starting counting after receiving an enable signal through the enable port and receiving a carrier signal with a preset frequency through the clock port, and transmitting an unlocking signal to the FCT test circuit after a preset value is reached, so that the FCT test circuit is unlocked. According to the application, the possibility of false start of the FCT test circuit can be reduced, so that the stability of the CPLD is improved, and the possibility of failure of the control panel of the power conversion circuit is further reduced.

Description

Technical Field

[0001] The present application relates to the field of FCT testing technology, and in particular to a CPLD and its FCT unlocking circuit and a control board of a power conversion circuit. Background Art

[0002] At present, the control board of the power conversion circuit is mainly composed of a DSP chip (DSP, Digital Signal Processing) and a CPLD chip (CPLD, Complex Programmable Logic Device). Before the control board leaves the factory, it is generally necessary to perform an FCT test (FCT, Functional Circuit Test) on the CPLD chip, that is, perform an offline functional test. The existing CPLD FCT test circuit is easily caused by interference or software misoperation when the CPLD is operating normally, which can easily cause the control board of the power conversion circuit to fail. Utility Model Content

[0003] In view of this, the present application provides a CPLD and its FCT unlocking circuit and a control board of a power conversion circuit, which are used to reduce the possibility of false start of the FCT test circuit caused by interference, software misoperation, etc., thereby improving the stability of the CPLD and further reducing the possibility of failure of the control board of the power conversion circuit. The technical solution of the present application is as follows:

[0004] In a first aspect, the present application provides an FCT unlocking circuit of a CPLD, the CPLD comprising an FCT test circuit, the FCT test circuit being used to perform an offline functional test after unlocking; the FCT unlocking circuit comprising an enable port, a clock port and a counting module, the counting module being connected to the enable port, the clock port and the FCT test circuit; the counting module being used to receive an enable signal through the enable port, and after receiving a carrier signal of a preset frequency through the clock port, start counting, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value, so as to unlock the FCT test circuit.

[0005] In an embodiment of the present application, the counting module is further configured to transmit a locking signal to the FCT test circuit when the enabling signal stops being received, so as to lock the FCT test circuit.

[0006] In one embodiment of the present application, the counting module is also used to start decrementing the count value at a preset time interval when the enable signal is received but the carrier signal is stopped being received, and when the count value is zero, output a lock signal to the FCT test circuit to lock the FCT test circuit.

[0007] In one embodiment of the present application, the counting module includes an AND gate unit and a counter, the first input end of the AND gate unit is connected to the enable port, the second input end of the AND gate unit is connected to the clock port, the output end of the AND gate unit is connected to the counter, and the counter is connected to the FCT test circuit; the AND gate unit is used to receive an enable signal through the enable port, and after receiving a carrier signal of a preset frequency through the clock port, transmit a counting control signal to the counter; the counter is used to start counting when receiving the control signal, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value.

[0008] In one embodiment of the present application, the counter is also used to start decrementing the count value at a preset time interval after the FCT test circuit is unlocked and stops receiving the control signal, and when the count value is zero, output a locking signal to the FCT test circuit to lock the FCT test circuit.

[0009] A second aspect of the present application provides a CPLD, comprising an FCT test circuit and an FCT unlocking circuit, wherein the FCT test circuit is used to perform an offline functional test after unlocking; the FCT unlocking circuit comprises an enable port, a clock port and a counting module, wherein the counting module is connected to the enable port, the clock port and the FCT test circuit; the counting module is used to receive an enable signal through the enable port, and after receiving a carrier signal of a preset frequency through the clock port, start counting, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value, so as to unlock the FCT test circuit.

[0010] In one embodiment of the present application, it also includes a normal working circuit, which is connected to the counting module; the normal working circuit is used to control the CPLD to work normally after startup; the counting module is also used to transmit a locking signal to the FCT test circuit when it stops receiving the enable signal, so that the FCT test circuit is locked, and transmit a start signal to the normal working circuit to start the normal working circuit.

[0011] In one embodiment of the present application, the counting module is also used to start decrementing the count value at a preset time interval when the enable signal is received but the carrier signal is stopped being received, and when the count value is zero, output a lock signal to the FCT test circuit to lock the FCT test circuit, and transmit a start signal to the normal working circuit to start the normal working circuit.

[0012] In one embodiment of the present application, the counting module includes an AND gate unit and a counter, the first input end of the AND gate unit is connected to the enable port, the second input end of the AND gate unit is connected to the clock port, the output end of the AND gate unit is connected to the counter, and the counter is connected to the FCT test circuit; the AND gate unit is used to receive an enable signal through the enable port, and after receiving a carrier signal of a preset frequency through the clock port, transmit a counting control signal to the counter; the counter is used to start counting when receiving the control signal, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value.

[0013] The third aspect of the present application provides a control board of a power conversion circuit, comprising a DSP chip and the CPLD, wherein the DSP chip is used to transmit an enable signal and a carrier signal of a preset frequency to the CPLD upon receiving a test instruction.

[0014] The CPLD of the present application adds an FCT unlocking circuit, which includes an enable port, a clock port and a counting module. The counting module starts counting after receiving an enable signal through the enable port and a carrier signal of a preset frequency through the clock port, and transmits an unlocking signal to the FCT test circuit after reaching a pre-designed value to unlock the FCT test circuit. This can reduce the possibility of false startup of the FCT test circuit due to interference, software misoperation, etc., thereby improving the stability of the CPLD. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic block diagram of an FCT unlocking circuit provided in an embodiment of the present application.

[0016] Figure 2 It is a schematic block diagram of a counting module provided in an embodiment of the present application.

[0017] Figure 3 It is a schematic block diagram of a CPLD provided in an embodiment of the present application.

[0018] Figure 4 It is a schematic block diagram of the second CPLD provided in the embodiment of the present application.

[0019] Figure 5 It is a schematic block diagram of a control board of a power conversion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] It should be noted that in the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and drawings of this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0021] It should also be noted that the method disclosed in the embodiments of the present application or the method shown in the flowchart includes one or more steps for implementing the method. Without departing from the scope of the claims, the execution order of multiple steps can be interchangeable with each other, and some of the steps can also be deleted.

[0022] At present, the control board of the power conversion circuit is mainly composed of DSP chip and CPLD chip. Before the control board leaves the factory, it is generally necessary to perform FCT test on the CPLD chip, that is, perform offline functional test. The existing CPLD FCT test circuit is easily activated due to interference or software misoperation when the CPLD is operating normally, which can easily cause the control board of the power conversion circuit to malfunction.

[0023] Specifically, for example, photovoltaic inverters or energy storage converters equipped with power conversion circuits work in a strong electromagnetic environment, and the control signal of the FCT test circuit of the CPLD chip is a weak electric signal, so it is easily interfered by strong electromagnetic interference and causes the FCT test circuit to start up incorrectly. For another example, the CPLD chip in the control board is controlled by the DSP chip executing the software program. During the power-on reset process of the DSP chip, the communication serial port related to the FCT test circuit may be unstable, or the communication serial port related to the control of the FCT test circuit may be misoperated during the process of the DSP chip running the software program, which may cause the FCT test circuit to start up incorrectly.

[0024] The present application provides a CPLD and its FCT unlocking circuit and a control board of a power conversion circuit, which are used to avoid false start-up of the FCT test circuit caused by interference, software misoperation, etc., thereby ensuring that the CPLD can operate stably and further avoiding failure of the control board of the power conversion circuit.

[0025] Please refer to Figure 1 , Figure 1 The schematic block diagram of an FCT unlocking circuit provided in an embodiment of the present application is as follows: wherein the FCT unlocking circuit 100 comprises an enable port 110 , a clock port 120 and a counting module 130 .

[0026] In the embodiment of the present application, the FCT unlocking circuit 100 is applied to the CPLD, and the CPLD includes an FCT test circuit, which is used to perform an offline function test after unlocking. When the CPLD is in a normal working mode, the FCT test circuit is in a locked state to avoid the offline test function of the CPLD being mistakenly started and affecting its normal work.

[0027] The counting module 130 is connected to the enable port 110, the clock port 120 and the FCT test circuit. The counting module 130 is used to start counting after receiving an enable signal through the enable port 110 and a carrier signal of a preset frequency through the clock port 120, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value, so as to unlock the FCT test circuit.

[0028] It can be understood that the CPLD of the present application adds an FCT unlocking circuit 100, which includes an enable port 110, a clock port 120 and a counting module 130. The counting module 130 starts counting after receiving an enable signal through the enable port 110 and a carrier signal of a preset frequency through the clock port 120, and transmits an unlocking signal to the FCT test circuit after reaching a pre-designed value to unlock the FCT test circuit. This can avoid false startup of the FCT test circuit caused by interference, software misoperation, etc., thereby ensuring that the CPLD can operate stably.

[0029] In some embodiments, the counting module 130 is further configured to transmit a locking signal to the FCT test circuit when the enable signal stops being received, so as to lock the FCT test circuit.

[0030] In some embodiments, the counting module 130 is also used to start decrementing the count value at a preset time interval when receiving an enable signal but stopping receiving a carrier signal, and output a lock signal to the FCT test circuit when the count value is zero to lock the FCT test circuit.

[0031] In some embodiments, please refer to Figure 2 The counting module 130 includes an AND gate unit 131 and a counter 132. The first input end of the AND gate unit 131 is connected to the enable port 110, the second input end of the AND gate unit 131 is connected to the clock port 120, the output end of the AND gate unit 131 is connected to the counter 132, and the counter 132 is connected to the FCT test circuit.

[0032] The AND gate unit 131 is used to transmit a counting control signal to the counter 132 after receiving an enable signal through the enable port 110 and a carrier signal of a preset frequency through the clock port 120. The counter 132 is used to start counting when receiving the control signal, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value.

[0033] In some embodiments, the counter 132 is also used to start decrementing the count value at a preset time interval after the FCT test circuit is unlocked and stops receiving the control signal, and output a lock signal to the FCT test circuit when the count value is zero to lock the FCT test circuit.

[0034] Please refer to Figure 3 , Figure 3 A schematic block diagram of a CPLD provided in an embodiment of the present application, wherein the CPLD 30 includes a FCT test circuit 301 and a FCT unlock circuit 310 .

[0035] In the embodiment of the present application, the FCT test circuit 301 is used to perform offline functional test after unlocking. The FCT unlocking circuit 310 includes an enable port 311, a clock port 312 and a counting module 313, and the counting module 313 is connected to the enable port 311, the clock port 312 and the FCT test circuit 301.

[0036] Among them, the counting module 313 is used to start counting after receiving an enable signal through the enable port 311 and a carrier signal of a preset frequency through the clock port 312, and transmit an unlocking signal to the FCT test circuit 301 after reaching a pre-designed value to unlock the FCT test circuit 301.

[0037] In some embodiments, Figure 4 As shown, the CPLD 30 also includes a normal working circuit 302, and the normal working circuit 302 is connected to the counting module 313. The normal working circuit 302 is used to control the CPLD 30 to work normally after startup. The counting module 313 is also used to transmit a locking signal to the FCT test circuit 301 when the enable signal stops being received, so that the FCT test circuit 301 is locked, and transmit a start signal to the normal working circuit 302, so that the normal working circuit 302 is started.

[0038] In some embodiments, the counting module 313 is also used to start decrementing the count value at a preset time interval when the enable signal is received but the carrier signal is stopped being received, and when the count value is zero, output a lock signal to the FCT test circuit 301 to lock the FCT test circuit 301, and transmit a start signal to the normal working circuit 302 to start the normal working circuit 302.

[0039] It can be understood that the beneficial effects that can be achieved by the CPLD30 of the embodiment of the present application are consistent with the beneficial effects that can be achieved by the FCT unlocking circuit of any of the above embodiments, and will not be repeated here.

[0040] Please refer to Figure 5 , Figure 5 A schematic block diagram of a control board of a power conversion circuit provided in an embodiment of the present application, wherein the control board 500 includes a DSP chip 510 and a CPLD 520 of any of the above embodiments.

[0041] In the embodiment of the present application, the DSP chip 510 is used to transmit an enable signal and a carrier signal of a preset frequency to the CPLD 520 when receiving a test instruction, so that the CPLD 520 enables the offline test function of the control board.

[0042] It can be understood that the beneficial effects that can be achieved by the control board of the embodiment of the present application are consistent with the beneficial effects that can be achieved by the FCT unlocking circuit of any of the above-mentioned embodiments, and will not be repeated here.

[0043] The embodiments described above are merely preferred embodiments of the present application and are not intended to limit the scope of the present application. Without departing from the design spirit of the present application, various modifications and improvements made to the technical solutions of the present application by ordinary technicians in this field should fall within the protection scope determined by the claims of the present application.

Claims

1. A FCT unlocking circuit of a CPLD, characterized in that: The CPLD includes an FCT test circuit, and the FCT test circuit is used to perform an offline functional test after unlocking; The FCT unlocking circuit includes an enable port, a clock port and a counting module, and the counting module is connected to the enable port, the clock port and the FCT test circuit; The counting module is used to start counting after receiving an enable signal through the enable port and a carrier signal of a preset frequency through the clock port, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value to unlock the FCT test circuit.

2. The FCT unlocking circuit according to claim 1, characterized in that: The counting module is further configured to transmit a locking signal to the FCT test circuit when the enabling signal stops being received, so as to lock the FCT test circuit.

3. The FCT unlocking circuit according to claim 1, characterized in that: The counting module is also used to start decrementing the count value at a preset time interval when the enable signal is received but the carrier signal stops being received, and to output a lock signal to the FCT test circuit when the count value is zero, so as to lock the FCT test circuit.

4. The FCT unlocking circuit according to claim 1, characterized in that: The counting module comprises an AND gate unit and a counter, wherein the first input end of the AND gate unit is connected to the enable port, the second input end of the AND gate unit is connected to the clock port, the output end of the AND gate unit is connected to the counter, and the counter is connected to the FCT test circuit; The AND gate unit is used to transmit a counting control signal to the counter after receiving an enable signal through the enable port and receiving a carrier signal of a preset frequency through the clock port; The counter is used to start counting when receiving the control signal, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value.

5. The FCT unlocking circuit according to claim 4, characterized in that: The counter is also used to start decrementing the count value at a preset time interval after the FCT test circuit is unlocked and stops receiving the control signal, and output a locking signal to the FCT test circuit when the count value is zero to lock the FCT test circuit.

6. A CPLD, characterized in that: It includes an FCT test circuit and an FCT unlocking circuit, wherein the FCT test circuit is used to perform an offline functional test after unlocking; The FCT unlocking circuit includes an enable port, a clock port and a counting module, and the counting module is connected to the enable port, the clock port and the FCT test circuit; The counting module is used to start counting after receiving an enable signal through the enable port and a carrier signal of a preset frequency through the clock port, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value to unlock the FCT test circuit.

7. The CPLD according to claim 6, wherein: It also includes a normal working circuit, which is connected to the counting module; The normal working circuit is used to control the CPLD to work normally after startup; The counting module is also used to transmit a locking signal to the FCT test circuit to lock the FCT test circuit when the enable signal stops being received, and transmit a start signal to the normal working circuit to start the normal working circuit.

8. The CPLD according to claim 7, wherein: The counting module is also used to start decrementing the count value at a preset time interval when the enable signal is received but the carrier signal is stopped being received, and when the count value is zero, output a lock signal to the FCT test circuit to lock the FCT test circuit, and transmit a start signal to the normal working circuit to start the normal working circuit.

9. The CPLD according to claim 6, wherein: The counting module comprises an AND gate unit and a counter, wherein the first input end of the AND gate unit is connected to the enable port, the second input end of the AND gate unit is connected to the clock port, the output end of the AND gate unit is connected to the counter, and the counter is connected to the FCT test circuit; The AND gate unit is used to transmit a counting control signal to the counter after receiving an enable signal through the enable port and receiving a carrier signal of a preset frequency through the clock port; The counter is used to start counting when receiving the control signal, and transmit an unlocking signal to the FCT test circuit after reaching a pre-designed value.

10. A control board of a power conversion circuit, characterized in that: It comprises a DSP chip and a CPLD as claimed in any one of claims 6 to 9, wherein the DSP chip is used for transmitting an enable signal and a carrier signal of a preset frequency to the CPLD upon receiving a test instruction.

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