SIP circuit based on DSP and FPGA

Abstract

The utility model relates to the technical field of chip integration, and particularly discloses an SIP (Session Initiation Protocol) circuit based on a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array), which comprises a base, an FPGA chip and a DSP chip are integrated on the base, and the DSP chip is in communication connection with the FPGA chip through a first EMIF (External Memory Interface) bus and a second EMIF bus; the temperature sensor is integrated on the base and is connected with the FPGA chip; the DSP chip configuration module is integrated on the base and is connected with the DSP chip; and the semiconductor memory is integrated on the base and is connected with the first EMIF bus and the second EMIF bus. The temperature sensor is integrated on the SIP circuit base integrated with the DSP chip and the FPGA chip, so that the SIP circuit supports on-line temperature monitoring, the working temperature of the SIP circuit can be controlled within a certain range, and the service life of the SIP circuit is prolonged.

Description

Technical Field

[0001] The utility model relates to the field of chip integration, in particular to a SIP circuit based on DSP and FPGA. Background Art

[0002] The high-performance general-purpose image digital signal processing SIP circuit based on FPGA and DSP is a combined signal processing system that integrates computing and storage devices. This system solves many challenges in the field of signal processing by combining different computing devices, such as signal processors, unit controllers, and high-speed data transmission devices. The combined signal processing system has the advantages of high performance, high reliability, and high integration, and is an important trend in the development of networked systems.

[0003] Currently, when SIP circuits are applied to signal processors, unit controllers, and high-speed data transmission equipment, the operating temperature of the SIP circuits is not monitored in real time. If the operating temperature of the SIP circuits is too high, the circuits may fail, thereby shortening the service life of the SIP circuits. Utility Model Content

[0004] In order to overcome the above-mentioned technical problems existing in the prior art, an embodiment of the utility model provides a SIP circuit based on DSP and FPGA. By integrating a temperature sensor on a SIP circuit base integrated with a DSP chip and an FPGA chip, the SIP circuit supports online temperature monitoring, thereby controlling the operating temperature of the SIP circuit within a certain range, thereby extending the service life of the SIP circuit.

[0005] In order to achieve the above-mentioned purpose, an embodiment of the utility model provides a SIP circuit based on DSP and FPGA, including: a base, on which an FPGA chip and a DSP chip are integrated, and the DSP chip and the FPGA chip are communicatively connected via a first EMIF bus and a second EMIF bus; a temperature sensor, which is integrated on the base and connected to the FPGA chip; a DSP chip configuration module, which is integrated on the base and connected to the DSP chip; and a semiconductor memory, which is integrated on the base and connected to the first EMIF bus and the second EMIF bus.

[0006] Preferably, the DSP chip configuration module includes an EEPROM memory and a Nor Flash memory; the NorFlash memory is connected to the DSP chip via an SPI bus; and the EEPROM memory is connected to the DSP chip via a multi-channel buffered serial port.

[0007] Preferably, the DSP chip further includes a XINTF interface, and the DSP chip is connected to the first EMIF bus and the second EMIF bus through the XINTF interface.

[0008] Preferably, the DSP and FPGA-based SIP circuit further comprises: an FPGA storage module integrated on the base, and the FPGA storage module is connected to the FPGA chip.

[0009] Preferably, the FPGA storage module includes an LDO linear regulator and a PROM memory; the LDO linear regulator is connected to the PROM memory, and the PROM memory is connected to the FPGA chip.

[0010] Preferably, the semiconductor memory is an SRAM memory, and the model of the SRAM memory is M64LV25616.

[0011] Preferably, the model of the FPGA chip is JXCLX25, the model of the DSP chip is LS-Z35PQGS, and the model of the temperature sensor is JST18B20.

[0012] Preferably, the model of the EEPROM memory is W25Q128, and the model of the Nor Flash memory is GD25Q128EGXG.

[0013] Preferably, the model of the LDO linear regulator is AMS1117-ADJ, and the model of the PROM memory is JXCF32P.

[0014] Through the technical solution provided by the utility model, the utility model has at least the following technical effects:

[0015] By integrating a temperature sensor on a SIP circuit base integrated with a DSP chip and an FPGA chip, and connecting the temperature sensor to the FPGA chip, the SIP circuit supports online temperature monitoring and can control the operating temperature of the SIP circuit within a certain range, thereby extending the service life of the SIP circuit.

[0016] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the embodiments of the present utility model and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present utility model, but do not constitute a limitation on the embodiments of the present utility model. In the accompanying drawings:

[0018] Figure 1It is a structural schematic diagram of a SIP circuit based on DSP and FPGA provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0019] The specific implementation of the embodiment of the utility model is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the utility model, and is not used to limit the embodiment of the utility model.

[0020] The terms "system" and "network" in the embodiments of the present invention can be used interchangeably. "Multiple" refers to two or more than two. In view of this, in the embodiments of the present invention, "multiple" can also be understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the previous and subsequent associated objects are in an "or" relationship. In addition, it should be understood that in the description of the embodiments of the present invention, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0021] See also Figure 1 The utility model provides a SIP circuit of DSP and FPGA, including: a base, on which an FPGA chip and a DSP chip are integrated, and the DSP chip and the FPGA chip are communicatively connected via a first EMIF bus and a second EMIF bus; a temperature sensor, which is integrated on the base and connected to the FPGA chip; a DSP chip configuration module, which is integrated on the base and connected to the DSP chip; and a semiconductor memory, which is integrated on the base and connected to the first EMIF bus and the second EMIF bus.

[0022] In an embodiment of the utility model, the base of the SIP circuit based on DSP and FPGA is preferably a ceramic substrate, all chips in the SIP circuit are domestic chips, and an FPGA chip and a DSP chip are integrated on the base. The model of the FPGA chip is selected as the JXCLX25 chip produced by China Electronics Technology Group, and the model of the DSP chip is selected as the LS-Z35PQGS chip produced by Hubliang Microelectronics Co., Ltd., and the main frequency of the DSP chip is 150MHz. A communication connection is established between the DSP chip and the FPGA chip through the first EMIF bus and the second EMIF bus, so that efficient data exchange can be performed between the DSP chip and the FPGA chip through the EMIF bus; a semiconductor memory is integrated on the base, and the semiconductor memory is respectively connected to the first EMIF bus and the second EMIF bus to realize high-speed and high-reliability data storage and access of the SIP circuit, and the semiconductor memory is preferably an SRAM memory, and the model of the SRAM memory is M64LV25616.

[0023] Specifically, a temperature sensor is also integrated on the base. The model of the temperature sensor can be selected as the JST18B20 chip produced by Beijing Qixin Zhongchuang Technology Co., Ltd., and the temperature sensor and the FPGA chip are connected to communicate with each other. The temperature sensor is used to monitor the operating temperature of the FPGA chip online and ensure that the operating temperature of the FPGA chip is within the safe temperature range of -55°C ~ 125°C, so that when the operating temperature of the FPGA chip exceeds the safe temperature range, an alarm can be triggered or the operating frequency of the system can be automatically reduced, thereby preventing overheating and damaging the entire SIP circuit.

[0024] Furthermore, a DSP chip configuration module is integrated on the base and connected to the DSP chip. This DSP chip configuration module can ensure that the DSP chip can be flexibly configured according to specific application requirements, while also managing the resources inside the DSP chip and setting the communication interface between the DSP chip and other system components.

[0025] In one embodiment, the DSP chip configuration module includes an EEPROM memory and a Nor Flash memory, wherein the memory capacity of the EEPROM memory is 128Mbit, and the model of the EEPROM memory is W25Q128, the capacity and data width of the Nor Flash memory are internally expanded to 256K*16bit, and the model of the Nor Flash memory is GD25Q128EGXG; the DSP chip is also configured with an SPI interface, and the Nor Flash memory is connected to the SPI interface of the DSP chip via an SPI bus; the EEPROM memory is connected to the DSP chip via a multichannel buffered serial port (Multichannel Buffered Serial Port, McBSP).

[0026] In an embodiment of the utility model, the DSP chip also includes a XINTF interface, and the DSP chip is connected to the first EMIF bus and the second EMIF bus through the XINTF interface. The XINTF interface provides a flexible interface for the DSP chip to connect and configure various external memories and I / O devices to meet the needs of different applications.

[0027] In an embodiment of the utility model, an FPGA storage module is further integrated on the base, and the FPGA storage module is connected to the FPGA chip. The FPGA storage module can provide an efficient, flexible and reliable storage solution for the FPGA chip, and also help the FPGA chip to realize various complex digital logic and data processing tasks.

[0028] In one embodiment, the FPGA storage module includes an LDO linear regulator and a PROM memory, wherein the LDO linear regulator is connected to the PROM memory so that the LDO linear regulator provides power to the PROM memory, and the PROM memory is connected to the FPGA chip so as to provide flexibility and scalability to the FPGA chip, while also ensuring the security and stability of key data in the FPGA chip; the model of the LDO linear regulator is AMS1117-ADJ, and the model of the PROM memory is JXCF32P.

[0029] In the embodiment of the utility model, the packaging form of the SIP circuit based on DSP and FPGA provided in this embodiment is PBGA676, the packaging size of the SIP circuit is 27mm*27mm*2.45mm, the power consumption of the SIP circuit is less than or equal to 3.5W, and the weight is 5g.

[0030] Through the DSP and FPGA-based SIP circuit provided in this embodiment, an FPGA chip and a DSP chip are integrated on the base of the circuit. The FPGA chip and the DSP chip are connected to each other through an EMIF bus communication. A temperature sensor is also integrated on the base. The temperature sensor is connected to the FPGA chip and can monitor the operating temperature of the FPGA chip in real time to ensure that the FPGA chip operates within a safe temperature range, thereby preventing the entire SIP circuit from being damaged due to overheating of the FPGA chip. An efficient way can be provided to ensure the reliability and performance of the SIP circuit, while also improving the energy efficiency of the SIP circuit and extending the service life of the SIP circuit.

[0031] The optional implementation modes of the embodiments of the utility model are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the utility model are not limited to the specific details in the above implementation modes. Within the technical concept of the embodiments of the utility model, the technical scheme of the embodiments of the utility model can be subjected to various simple modifications, and these simple modifications all belong to the protection scope of the embodiments of the utility model.

[0032] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the utility model will not further describe various possible combinations.

[0033] In addition, various implementations of the embodiments of the present utility model can also be arbitrarily combined, as long as they do not violate the concept of the embodiments of the present utility model, they should also be regarded as the contents disclosed in the embodiments of the present utility model.

Claims

1. A SIP circuit based on DSP and FPGA, characterized in that: include: A base, on which an FPGA chip and a DSP chip are integrated, wherein the DSP chip and the FPGA chip are communicatively connected via a first EMIF bus and a second EMIF bus; A temperature sensor, integrated on the base and connected to the FPGA chip; A DSP chip configuration module, integrated on the base and connected to the DSP chip; A semiconductor memory is integrated on the base and connected to the first EMIF bus and the second EMIF bus.

2. The SIP circuit based on DSP and FPGA according to claim 1, characterized in that: The DSP chip configuration module includes an EEPROM memory and a Nor Flash memory; The Nor Flash memory is connected to the DSP chip via an SPI bus; The EEPROM memory is connected to the DSP chip via a multi-channel buffered serial port.

3. The SIP circuit based on DSP and FPGA according to claim 1, characterized in that: The DSP chip further includes a XINTF interface, and the DSP chip is connected to the first EMIF bus and the second EMIF bus through the XINTF interface.

4. The SIP circuit based on DSP and FPGA according to claim 1, characterized in that: The SIP circuit based on DSP and FPGA also includes: An FPGA storage module is integrated on the base, and the FPGA storage module is connected to the FPGA chip.

5. The SIP circuit based on DSP and FPGA according to claim 4, characterized in that: The FPGA storage module includes an LDO linear regulator and a PROM memory; The LDO linear regulator is connected to the PROM memory, and the PROM memory is connected to the FPGA chip.

6. The SIP circuit based on DSP and FPGA according to claim 1, characterized in that: The semiconductor memory is an SRAM memory, and the model of the SRAM memory is M64LV25616.

7. The SIP circuit based on DSP and FPGA according to claim 1, characterized in that: The model of the FPGA chip is JXCLX25, the model of the DSP chip is LS-Z35PQGS, and the model of the temperature sensor is JST18B20.

8. The SIP circuit based on DSP and FPGA according to claim 2, characterized in that: The model of the EEPROM memory is W25Q128, and the model of the Nor Flash memory is GD25Q128EGXG.

9. The SIP circuit based on DSP and FPGA according to claim 5, characterized in that: The model of the LDO linear regulator is AMS1117-ADJ, and the model of the PROM memory is JXCF32P.

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