GaN HEMT chip

Abstract

The utility model discloses a GaN HEMT chip comprising an epitaxial layer and an isolation layer arranged on the epitaxial layer, and the isolation layer is internally provided with a plurality of grid electrode extension parts, a plurality of drain electrode extension parts and a plurality of source electrode extension parts which are arranged at intervals. The upper surface of the grid electrode extension part, the upper surface of the drain electrode extension part and the upper surface of the source electrode extension part are exposed from the upper surface of the isolation layer; the drain electrode extension part is provided with at least one insulation protruding part extending upwards, each drain electrode extension part and the at least one insulation protruding part are covered with drain electrode wire parts to form a plurality of drain electrode wire parts, and each source electrode extension part is covered with source electrode wire parts to form a plurality of source electrode wire parts. And each gate extension part is covered with a gate wire part to form a plurality of gate wire parts. According to the GaN HEMT chip provided by the utility model, the at least one insulating lug boss extending upwards is arranged on the drain electrode extension part, and the drain electrode wire part is covered on the drain electrode extension part and the insulating lug boss, so that the length of the drain electrode wire part is increased, and the GaN HEMT chip can bear larger current.

Description

Technical Field

[0001] The utility model relates to the field of HEMT chips, in particular to a GaN HEMT chip. Background Art

[0002] At present, GaN HEMT chips have been gradually applied to consumer electronic power supplies, electric vehicles, high-speed rail, power stations, aerospace and other application fields. GaN HEMT is a high electron mobility transistor device that relies on the inherent characteristics of GaN materials to form a strong two-dimensional electron gas layer at the heterojunction. It has high power density and high frequency characteristics, and has the advantages of fast startup, long life, high efficiency, energy saving and environmental protection. The existing GaN HEMT high electron mobility transistors generally meet the demand for large current through large area or small line width design, but this will make the unit price too high or require expensive exposure process machines. Summary of the invention

[0003] The purpose of the present invention is to provide a GaN HEMT chip that can withstand large currents without increasing the chip area or reducing the chip line width, so as to solve the problem that the demand for large currents in existing GaN HEMT chips is generally achieved through large area or small line width designs, resulting in excessively high unit prices or requiring expensive exposure process machines.

[0004] In order to achieve the above-mentioned object, the utility model provides a GaN HEMT chip, comprising an epitaxial layer and an insulating layer arranged on the epitaxial layer, wherein a plurality of gate extensions, a plurality of drain extensions and a plurality of source extensions are arranged at intervals in the insulating layer, and the upper surfaces of the gate extensions, the upper surfaces of the drain extensions and the upper surfaces of the source extensions are exposed from the upper surface of the insulating layer; at least one insulating protrusion extending upward is provided on the drain extension, each of the drain extensions and the at least one insulating protrusion is covered with a drain wire portion, each of the source extensions is covered with a source wire portion, each of the gate extensions is covered with a gate wire portion, and a protective layer is provided on the insulating layer, and the protective layer covers the drain wire portion, the source wire portion and the gate wire portion.

[0005] Preferably, the epitaxial layer includes a gallium nitride layer, an aluminum gallium nitride layer and a two-dimensional electron gas layer formed between the gallium nitride layer and the aluminum gallium nitride layer, the isolation layer is provided on the aluminum gallium nitride layer, and at least one first recessed hole is also opened on the drain extension portion, the first recessed hole extends downward to the gallium nitride layer, and the drain wire portion covers the drain extension portion, the insulating protrusion and the first recessed hole.

[0006] Preferably, there are multiple insulating protrusions on each drain extension portion, and there are multiple first recessed holes on each drain extension portion, and the multiple insulating protrusions and the multiple first recessed holes are alternately arranged in the extension direction of the corresponding drain extension portion.

[0007] Preferably, the epitaxial layer includes a gallium nitride layer, an aluminum gallium nitride layer and a two-dimensional electron gas layer formed between the gallium nitride layer and the aluminum gallium nitride layer, the isolation layer is provided on the aluminum gallium nitride layer, at least one second recessed hole is opened on the drain extension portion, the second recessed hole extends downward to the gallium nitride layer, the second recessed hole is filled with an insulating portion, the upper surface of the insulating portion is flush with the upper surface of the drain extension portion, and the drain wire portion covers the drain extension portion, the insulating protrusion portion and the insulating portion.

[0008] Preferably, there are multiple insulating protrusions on each drain extension portion, and multiple second recessed holes on each drain extension portion, and the multiple insulating protrusions and the multiple second recessed holes are alternately arranged in the extension direction of the corresponding drain extension portion.

[0009] Preferably, a drain pad, a source pad and a gate pad which are spaced apart from each other are provided on the upper surface of the protective layer, the drain pad is connected to all the drain wire portions via a plurality of drain conductive columns passing through the protective layer, the source pad is connected to all the source wire portions via a plurality of source conductive columns passing through the protective layer, and the gate pad is connected to all the gate wire portions via a gate connection line.

[0010] Preferably, a plurality of the drain wire portions, a plurality of the source wire portions and a plurality of the gate wire portions are arranged at intervals along a first direction, and a plurality of the drain wire portions, a plurality of the source wire portions and a plurality of the gate wire portions extend along a second direction perpendicular to the first direction, one end of the drain wire portion in the second direction is connected to the drain conductive column, one end of the source wire portion away from the drain conductive column is connected to the source conductive column, the gate connection circuit includes a gate connection line and a gate conductive column, the gate connection line is arranged in the protective layer and connects one end of all the gate wire portions close to the drain conductive column, the gate conductive column is penetrated in the protective layer and connected to the gate pad.

[0011] Preferably, a first insulating widening portion is provided at the connection position between the drain extension portion and the drain conductive column, the size of the first insulating widening portion in the first direction is larger than the size of the drain extension portion in the first direction, and the first insulating widening portion is covered with a first conductive portion to be electrically connected to the drain extension portion and the drain conductive column; and / or, a second insulating widening portion is provided at the connection position between the source wire portion and the source conductive column, the size of the second insulating widening portion in the first direction is larger than the size of the source wire portion in the first direction, and the second insulating widening portion is covered with a second conductive portion to be electrically connected to the source wire portion and the source conductive column; and / or, a third insulating widening portion is provided at the connection position between the gate wire portion and the gate connection line, the size of the third insulating widening portion in the first direction is larger than the size of the gate wire portion in the first direction, and the third insulating widening portion is covered with a third conductive portion to be electrically connected to the gate wire portion and the gate connection line.

[0012] Preferably, the drain pad is in the shape of an elongated strip and corresponds to a plurality of drain conductive columns arranged on a first side of the protective layer, the source pad is in the shape of an elongated strip and corresponds to a plurality of source conductive columns arranged on a second side of the protective layer opposite to the first side, and there are two drain pads and they are respectively arranged on both sides of the length direction of the drain pad.

[0013] Preferably, the material of the insulating protrusion is one of silicon dioxide, aluminum oxide, and silicon nitride. The insulating protrusion is in the shape of a truncated cone that is small on the top and large on the bottom. The diameter of the upper base of the insulating protrusion is greater than or equal to 10 nanometers and less than or equal to 50 nanometers, the diameter of the lower base of the insulating protrusion is greater than or equal to 30 nanometers and less than or equal to 100 nanometers, and the height of the insulating protrusion is greater than or equal to 10 nanometers and less than or equal to 100 nanometers.

[0014] Compared with the prior art, the utility model provides at least one insulating protrusion extending upward on the drain extension portion and covers the drain wire portion on the drain extension portion and the insulating protrusion portion, thereby lengthening the drain wire portion, so that the GaN HEMT chip can withstand a larger current and meet the market demand for a large-current HEMT chip, thereby eliminating the need to increase the chip area or reduce the chip line width. The GaN HEMT chip of the utility model embodiment has a low cost and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The figure is a three-dimensional schematic diagram of a specific embodiment of the GaN HEMT chip of the utility model from one angle.

[0016] Figure 2 It is a three-dimensional schematic diagram from another angle of a specific embodiment of the GaN HEMT chip of the utility model.

[0017] Figure 3 for Figure 2 Cross-section along line AA.

[0018] Figure 4 for Figure 2 Cross-section along line BB.

[0019] Figure 5 for Figure 2 Sectional view along the CC line.

[0020] Figure 6 for Figure 2 Sectional view along line DD.

[0021] Figure 7 for Figure 2 Cross-sectional view along line EE.

[0022] Figure 8 for Figure 7 Enlarged view of point F in the middle.

[0023] Fig. 9 It is a structural schematic diagram of another specific embodiment of the GaN HEMT chip of the utility model.

[0024] Fig.10 It is a structural schematic diagram of another specific embodiment of the GaN HEMT chip of the utility model. DETAILED DESCRIPTION

[0025] In order to explain the technical content, structural features and effects achieved by the present invention in detail, the following is a detailed description in conjunction with the implementation modes and the accompanying drawings.

[0026] like Figures 1 to 8As shown, an embodiment of the utility model provides a GaN HEMT chip, including an epitaxial layer 200 and an insulating layer 300 arranged on the epitaxial layer 200, wherein a plurality of gate extensions 30, a plurality of drain extensions 10 and a plurality of source extensions 20 are arranged at intervals in the insulating layer 300, and the upper surfaces of the gate extensions 30, the upper surfaces of the drain extensions 10 and the upper surfaces of the source extensions 20 are exposed from the upper surface of the insulating layer 300; at least one insulating protrusion 11 extending upward is arranged on the drain extension 10, each drain extension 10 and at least one insulating protrusion 11 are covered with a drain wire portion 1 to form a plurality of drain wire portions 1, each source extension 20 is covered with a source wire portion 2 to form a plurality of source wire portions 2, each gate extension 30 is covered with a gate wire portion 3 to form a plurality of gate wire portions 3, and a protective layer 400 is arranged on the insulating layer 300, and the protective layer 400 covers the drain wire portion 1, the source wire portion 2 and the gate wire portion 3. Specifically, the epitaxial layer 200 is disposed on the substrate 100, and the substrate 100 may be a sapphire substrate or the like. The epitaxial layer 200 includes a gallium nitride layer 2001, an aluminum gallium nitride (ALGaN) layer, and a two-dimensional electron gas layer 2002 formed between the gallium nitride layer 2001 and the aluminum gallium nitride layer 2003. An isolation layer 300 is disposed on the aluminum gallium nitride layer 2003. A drain contact 40, a source contact 50, and a gate contact 60 are also disposed on the aluminum gallium nitride layer 2003. The lower portion of the drain extension portion 10 is connected to the drain contact 40 to achieve electrical connection, the lower portion of the source extension portion 20 is connected to the source contact 50 to achieve electrical connection, and the lower portion of the gate extension portion 30 is connected to the gate contact 60 to achieve electrical connection. The drain extension portion 10 may be formed by stacking a plurality of sub-drain extension portions, for example, the drain extension portion 10 may be formed by stacking a plurality of sub-drain extension portions. The portion 10 can be formed by stacking a first drain sub-extension portion 101 and a second drain sub-extension portion 102, the source extension portion 20 can be formed by stacking a first source sub-extension portion 201 and a second source sub-extension portion 202, the gate extension portion 30 can be formed by stacking a first gate sub-extension portion 301 and a second gate sub-extension portion 302 and a third gate sub-extension portion 303 stacked on the first gate sub-extension portion 301, and the upper surface of the second drain sub-extension portion 102, the upper surface of the second source sub-extension portion 202, the upper surface of the second gate sub-extension portion 302 and the upper surface of the third gate sub-extension portion 303 are flush with the upper surface of the isolation layer 300 to expose the upper surface of the gate extension portion 30, the upper surface of the drain extension portion 10 and the upper surface of the source extension portion 20. At least one insulating protrusion 11 is disposed on the upper surface of each drain extension portion 10 . Preferably, a plurality of insulating protrusions 11 are disposed at intervals on the upper surface of each drain extension portion 10 . The protective layer 400 may be a transparent protective layer.

[0027] In the embodiment of the utility model, at least one insulating protrusion 11 extending upward is provided on the drain extension portion 10 and the drain wire portion 1 is covered on the drain extension portion 10 and the insulating protrusion 11, thereby lengthening the drain wire portion 1, so that the GaN HEMT chip can withstand a larger current and meet the market demand for a large-current HEMT chip, thereby eliminating the need to increase the chip area or reduce the chip line width. The GaN HEMT chip in the embodiment of the utility model has a low cost, is easy to implement, and has good current spreading.

[0028] In an embodiment of the utility model, a drain pad 4, a source pad 5 and a gate pad 6 which are spaced apart from each other are provided on the upper surface of the protective layer 400. The drain pad 4 is connected to all drain wire portions 1 through a number of drain conductive columns 41 passing through the protective layer 400. The source pad 5 is connected to all source wire portions 2 through a number of source conductive columns 51 passing through the protective layer 400. The gate pad 6 is connected to all gate wire portions 3 through a gate connection line.

[0029] Specifically, Figures 1 to 7 As shown, the substrate 100, the epitaxial layer 200, the isolation layer 300 and the protective layer 400 are arranged in sequence along the thickness direction Z, a plurality of drain wire portions 1, a plurality of source wire portions 2 and a plurality of gate wire portions 3 are arranged at intervals along the first direction X, and the plurality of drain wire portions 1, the plurality of source wire portions 2 and the plurality of gate wire portions 3 extend along a second direction Y perpendicular to the first direction X, one end of the drain wire portion 1 in the second direction Y is connected to the drain conductive column 41, one end of the source wire portion 2 away from the drain conductive column 41 is connected to the source conductive column 51, the gate connection circuit includes a gate connection line 61 and a gate conductive column 62, the gate connection line 61 is arranged in the protective layer 400 and connects one end of all gate wire portions 3 close to the drain conductive column 41, and the gate conductive column 62 is penetrated in the protective layer 400 and connected to the gate pad 6. Specifically, each drain wire portion 1, each source wire portion 2 and each gate wire portion 3 are in the shape of an elongated strip, and the first drain sub-extension portion 101, the second drain sub-extension portion 102, the first source sub-extension portion 201, the second source sub-extension portion 202, the first gate sub-extension portion 301, the second gate sub-extension portion 302 and the third gate sub-extension portion 303 can be in the shape of an elongated strip extending along the second direction Y, or can be in the shape of a dot array arranged at intervals along the second direction Y.

[0030] In the embodiment of the utility model, a first insulating widened portion 7 is provided at the connection position between the drain wire portion 1 and the drain conductive column 41, and the size of the first insulating widened portion 7 in the first direction X is larger than the size of the drain wire portion 1 in the first direction X, and the first insulating widened portion 7 is covered with a first conductive portion 71 to be electrically connected to the drain wire portion 1 and the drain conductive column 41; a second insulating widened portion 8 is provided at the connection position between the source wire portion 2 and the source conductive column 51, and the size of the second insulating widened portion 8 in the first direction X is larger than the size of the source wire portion 2 in the first direction X, and the second insulating widened portion 8 is covered with a second conductive portion 81 to be electrically connected to the source wire portion 2 and the source conductive column 51; a third insulating widened portion 9 is provided at the connection position between the gate wire portion 3 and the gate connecting line 61, and the size of the third insulating widened portion 9 in the first direction X is larger than the size of the gate wire portion 3 in the first direction X, and the third insulating widened portion 9 is covered with a third conductive portion 63 to be electrically connected to the gate wire portion 3 and the gate connecting line 61. Specifically, the material of the first insulating widening portion 7, the second insulating widening portion 8 and the third insulating widening portion 9 is aluminum oxide, nickel oxide or zirconium oxide. It should be noted that the first insulating widening portion 7 and the second insulating widening portion 8 are circular, and the diameters of the first insulating widening portion 7 and the second insulating widening portion 8 are greater than or equal to 3 mm and less than or equal to 5 mm. The third insulating widening portion 9 can be square, and the side length of the third insulating widening portion 9 is greater than or equal to 3 mm and less than or equal to 5 mm. The setting of the first insulating widening portion 7 can increase the connection area between the drain wire portion 1 and the drain conductive column 41, thereby avoiding the risk of disconnection at the inflection point where the drain wire portion 1 and the drain conductive column 41 are connected. Similarly, the setting of the second insulating widening portion 8 can The connection area between the source wire portion 2 and the source conductive column 51 is increased to avoid the risk of disconnection at the inflection point where the source wire portion 2 and the source conductive column 51 are connected. The third insulating widening portion 9 can increase the connection area between the gate wire portion 3 and the gate connecting line 61 to avoid the risk of disconnection at the inflection point where the gate wire portion 3 and the gate connecting line 61 are connected. It should be noted that the specific shapes of the first insulating widening portion 7, the second insulating widening portion 8 and the third insulating widening portion 9 are not limited and can be selected according to actual needs. Only one of the first insulating widening portion 7, the second insulating widening portion 8 and the third insulating widening portion 9 can be selected. Of course, when the first insulating widening portion 7, the second insulating widening portion 8 and the third insulating widening portion 9 are all set, the risk of disconnection at the inflection point of the GaN HEMT chip is the lowest and the performance is the best.

[0031] In the embodiment of the utility model, the drain pad 4 is in the shape of a long strip and corresponds to a plurality of drain conductive pillars 41 disposed on a first side of the protective layer 400, the source pad 5 is in the shape of a long strip and corresponds to a plurality of source conductive pillars 51 disposed on a second side of the protective layer 400 opposite to the first side, and there are two gate pads 6 disposed on both sides of the drain pad 4 in the length direction. Figure 1 to Figure 2As shown, a plurality of drain conductive pillars 41 are connected through a long strip-shaped drain pad 4 to realize the parallel connection of a plurality of drain wire portions 1, a plurality of source conductive pillars 51 are connected through a long strip-shaped source pad 5 to realize the parallel connection of a plurality of source wire portions 2, and a plurality of gate wire portions 3 are realized in parallel through two gate pads 6, two gate conductive pillars 62 and a gate connecting line 61, and the structural layout is reasonable and compact.

[0032] In the embodiment of the utility model, the material of the insulating protrusion 11 is one of silicon dioxide, aluminum oxide, and silicon nitride. The insulating protrusion 11 is in the shape of a truncated cone with a small top and a large bottom. The diameter of the upper bottom of the insulating protrusion 11 is greater than or equal to 10 nanometers and less than or equal to 50 nanometers, the diameter of the lower bottom of the insulating protrusion 11 is greater than or equal to 30 nanometers and less than or equal to 100 nanometers, and the height of the insulating protrusion 11 is greater than or equal to 10 nanometers and less than or equal to 100 nanometers. Specifically, the insulating protrusion 11 can be deposited by a PECVD process and etched by a yellow light process. By setting the insulating protrusion 11 to be in the shape of a truncated cone with a small top and a large bottom, it is convenient to arrange the drain extension portion 10 on the insulating protrusion 11 by electroplating and other processes, which is a clever design.

[0033] Embodiment 2

[0034] The difference between this embodiment and the first embodiment is that: Fig. 9 And refer to Figures 1 to 8 As shown, in this embodiment, the epitaxial layer 200 includes a gallium nitride layer 2001, an aluminum gallium nitride layer 2003, and a two-dimensional electron gas layer 2002 formed between the gallium nitride layer 2001 and the aluminum gallium nitride layer 2003, an isolation layer 300 is provided on the aluminum gallium nitride layer 2003, at least one first recessed hole 12 is also provided on the drain extension portion 10, and the first recessed hole 12 extends downward to the gallium nitride layer 2001, and the drain wire portion 1 covers the drain extension portion 10, the insulating protrusion 11 and the first recessed hole 12. Specifically, there are multiple insulating protrusions 11 on each drain extension portion 10, and there are multiple first recessed holes 12 on each drain extension portion 10, and the multiple insulating protrusions 11 and the multiple first recessed holes 12 are alternately arranged in the extension direction of the corresponding drain extension portion 10. The first recessed hole 12 is a truncated cone-shaped opening that is larger at the top and smaller at the bottom. The diameter of the upper opening of the first recessed hole 12 is greater than or equal to 30 nanometers and less than or equal to 100 nanometers, the diameter of the bottom of the first recessed hole 12 is greater than or equal to 10 nanometers and less than or equal to 50 nanometers, and the depth of the first recessed hole 12 is greater than or equal to 10 nanometers and less than or equal to 100 nanometers. The interval between two adjacent first recessed holes 12 is greater than or equal to 1 micrometer and less than or equal to 3 micrometers. An insulating protrusion 11 is provided between two adjacent first recessed holes 12, and the first recessed hole 12 can be formed by an ICP etching process or a RIE etching process.

[0035] In this embodiment, the drain extension portion 10 is provided with an insulating protrusion 11 extending upward and a first recessed hole 12 recessed downward to increase the length of the drain wire portion 1, so that the GaN HEMT chip can withstand a large current and meet the market demand for a large current HEMT chip. In addition, since the drain wire portion 1 contacts more of the epitaxial layer 200, the ohmic contact is better.

[0036] Embodiment 3

[0037] The difference between this embodiment and the first embodiment is that: Fig.10 And refer to Figures 1 to 8 As shown, in this embodiment, the epitaxial layer 200 includes a gallium nitride layer 2001, an aluminum gallium nitride layer 2003, and a two-dimensional electron gas layer 2002 formed between the gallium nitride layer 2001 and the aluminum gallium nitride layer 2003, an isolation layer 300 is provided on the aluminum gallium nitride layer 2003, at least one second recessed hole 13 is opened on the drain extension portion 10, the second recessed hole 13 extends downward to the gallium nitride layer 2001, the second recessed hole 13 is filled with an insulating portion 14, the upper surface of the insulating portion 14 is flush with the upper surface of the drain extension portion 10, and the drain wire portion 1 covers the drain extension portion 10, the insulating protrusion 11 and the insulating portion 14. Specifically, there are multiple insulating protrusions 11 on each drain extension portion 10, and there are multiple second recessed holes 13 on each drain extension portion 10, and the multiple insulating protrusions 11 and the multiple second recessed holes 13 are alternately arranged in the extension direction of the corresponding drain extension portion 10. The second recessed hole 13 is a truncated cone-shaped opening that is larger at the top and smaller at the bottom. The diameter of the upper opening of the second recessed hole 13 is greater than or equal to 30 nanometers and less than or equal to 100 nanometers, the diameter of the lower bottom of the second recessed hole 13 is greater than or equal to 10 nanometers and less than or equal to 50 nanometers, and the depth of the second recessed hole 13 is greater than or equal to 10 nanometers and less than or equal to 100 nanometers. The interval between two adjacent second recessed holes 13 is greater than or equal to 1 micrometer and less than or equal to 3 micrometers. An insulating protrusion 11 is provided between two adjacent second recessed holes 13. The first recessed hole 12 can be formed by an ICP etching process or a RIE etching process. The material of the insulating part 14 is one of silicon dioxide, aluminum oxide, and silicon nitride.

[0038] In this embodiment, the drain extension portion 10 is provided with an insulating protrusion 11 extending upward and a second recessed hole 13 recessed downward, and an insulating portion 14 is filled in the recessed hole to increase the length of the drain wire layer, so that the GaN HEMT chip can withstand a large current and meet the market demand for a large current HEMT chip.

[0039] The above disclosure is only a preferred example of the present invention, and certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention still fall within the scope covered by the present invention.

Claims

1. GaN HEMT chip, characterized in that: The device comprises an epitaxial layer and an insulating layer disposed on the epitaxial layer, wherein a plurality of gate extensions, a plurality of drain extensions and a plurality of source extensions are disposed in the insulating layer at intervals, and the upper surfaces of the gate extensions, the upper surfaces of the drain extensions and the upper surfaces of the source extensions are exposed from the upper surface of the insulating layer; The drain extension portion is provided with at least one insulating protrusion extending upward, each of the drain extension portions and at least one insulating protrusion portion is covered with a drain wire portion, each of the source extension portion is covered with a source wire portion, and each of the gate extension portions is covered with a gate wire portion. A protective layer is provided on the insulating layer and the protective layer covers the drain wire portion, the source wire portion and the gate wire portion.

2. The GaN HEMT chip according to claim 1, characterized in that: The epitaxial layer includes a gallium nitride layer, an aluminum gallium nitride layer and a two-dimensional electron gas layer formed between the gallium nitride layer and the aluminum gallium nitride layer. The isolation layer is provided on the aluminum gallium nitride layer. The drain extension portion is also provided with at least one first recessed hole, which extends downward to the gallium nitride layer. The drain wire portion covers the drain extension portion, the insulating protrusion and the first recessed hole.

3. The GaN HEMT chip according to claim 2, characterized in that: There are multiple insulating protrusions on each drain extension portion, and there are multiple first recessed holes on each drain extension portion. The multiple insulating protrusions and the multiple first recessed holes are alternately arranged in the extension direction of the corresponding drain extension portion.

4. The GaN HEMT chip according to claim 1, characterized in that: The epitaxial layer includes a gallium nitride layer, an aluminum gallium nitride layer and a two-dimensional electron gas layer formed between the gallium nitride layer and the aluminum gallium nitride layer, the isolation layer is provided on the aluminum gallium nitride layer, at least one second recessed hole is opened on the drain extension portion, the second recessed hole extends downward to the gallium nitride layer, the second recessed hole is filled with an insulating portion, the upper surface of the insulating portion is flush with the upper surface of the drain extension portion, and the drain wire portion covers the drain extension portion, the insulating protrusion portion and the insulating portion.

5. The GaN HEMT chip according to claim 4, characterized in that: There are multiple insulating protrusions on each drain extension portion, and there are multiple second recessed holes on each drain extension portion. The multiple insulating protrusions and the multiple second recessed holes are alternately arranged in the extension direction of the corresponding drain extension portion.

6. The GaN HEMT chip according to claim 1, characterized in that: A drain pad, a source pad and a gate pad are provided on the upper surface of the protective layer, which are spaced apart from each other. The drain pad is connected to all the drain wire parts through a plurality of drain conductive columns passing through the protective layer, the source pad is connected to all the source wire parts through a plurality of source conductive columns passing through the protective layer, and the gate pad is connected to all the gate wire parts through a gate connecting line.

7. The GaN HEMT chip according to claim 6, characterized in that: A plurality of drain wire portions, a plurality of source wire portions and a plurality of gate wire portions are arranged at intervals along a first direction, and a plurality of drain wire portions, a plurality of source wire portions and a plurality of gate wire portions extend along a second direction perpendicular to the first direction, one end of the drain wire portion in the second direction is connected to the drain conductive column, one end of the source wire portion away from the drain conductive column is connected to the source conductive column, the gate connection circuit includes a gate connection line and a gate conductive column, the gate connection line is arranged in the protective layer and connects one end of all the gate wire portions close to the drain conductive column, the gate conductive column is penetrated in the protective layer and connected to the gate pad.

8. The GaN HEMT chip according to claim 7, characterized in that: A first insulating widening portion is provided at the connection position between the drain extension portion and the drain conductive column, and the size of the first insulating widening portion in the first direction is larger than the size of the drain extension portion in the first direction, and the first insulating widening portion is covered with a first conductive portion to be electrically connected to the drain extension portion and the drain conductive column; and / or, a second insulating widening portion is provided at the connection position between the source wire portion and the source conductive column, and the size of the second insulating widening portion in the first direction is larger than the size of the source wire portion in the first direction, and the second insulating widening portion is covered with a second conductive portion to be electrically connected to the source wire portion and the source conductive column; and / or, a third insulating widening portion is provided at the connection position between the gate wire portion and the gate connection line, and the size of the third insulating widening portion in the first direction is larger than the size of the gate wire portion in the first direction, and the third insulating widening portion is covered with a third conductive portion to be electrically connected to the gate wire portion and the gate connection line.

9. The GaN HEMT chip according to claim 6, characterized in that: The drain pad is in the shape of an elongated strip and corresponds to a plurality of drain conductive columns disposed on a first side of the protective layer. The source pad is in the shape of an elongated strip and corresponds to a plurality of source conductive columns disposed on a second side of the protective layer opposite to the first side. There are two gate pads and they are respectively disposed on both sides of the drain pad in the length direction.

10. The GaN HEMT chip according to claim 1, characterized in that: The material of the insulating protrusion is one of silicon dioxide, aluminum oxide, and silicon nitride. The insulating protrusion is in the shape of a truncated cone with a small top and a large bottom. The diameter of the upper bottom of the insulating protrusion is greater than or equal to 10 nanometers and less than or equal to 50 nanometers, the diameter of the lower bottom of the insulating protrusion is greater than or equal to 30 nanometers and less than or equal to 100 nanometers, and the height of the insulating protrusion is greater than or equal to 10 nanometers and less than or equal to 100 nanometers.

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