Isolation communication circuit for on-site definition of GPIO (General Purpose Input / Output) pin type of singlechip
By designing an isolated communication circuit that defines the GPIO pin type on-site in the microcontroller, and using the optocoupling isolation circuit to achieve flexible adjustment of the GPIO pin type, the problem of insufficient pins of the microcontroller in multiple input or multiple output scenarios is solved, and efficient utilization of the equipment and environmental adaptability are achieved.
Patent Information
- Application Number
- CN202422024374.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-08-20
AI Technical Summary
In actual use, due to the fixed GPIO pin type, in the case of multiple input or multiple output external sensors, the pins of the microcontroller are insufficient, and multiple microcontrollers are needed to use multiple microcontrollers to cause equipment redundancy.
By designing an isolated communication circuit that defines the GPIO pin type on-site, the optocoupling isolation circuit is used to realize the field definition of the GPIO pin type, allowing flexible adjustment of input or output types.
The field definition of input and output types of microcontroller GPIO ports is realized, which avoids device redundancy, rationally utilizes GPIO port resources, and improves the equipment's environmental adaptability.
Smart Images
Figure CN222914074U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of electronic circuits, and particularly relates to an isolated communication circuit for on-site defining the GPIO pin type of a single-chip microcomputer. Background Technique
[0002] The statements in this part only provide background technical information related to the present disclosure, and do not necessarily constitute prior art.
[0003] In the actual use scenarios of single-chip microcomputer related applications, there are many input or output external sensors that need to communicate with the GPIO pins of the single-chip microcomputer. The traditional method is to fixedly set the GPIO pins of the single-chip microcomputer as input pins or output pins. Since the peripheral isolation circuits of input pins and output pins are different, only corresponding type functions can be realized after the pin type is fixedly set. In actual use, if the number of input or output external sensors is more than the number of pins of the corresponding type set by the single-chip microcomputer, it will lead to insufficient pins of the corresponding type of the single-chip microcomputer, and using multiple single-chip microcomputers for matching will also cause redundancy of equipment.
[0004] For example, there is a single-chip microcomputer with 8 GPIO pins. At the beginning of the hardware device design, 4 pins are fixedly set as input pins and 4 pins are fixedly set as output pins. Because the pin types are fixed at the beginning of the product design, the peripheral isolation circuits are also fixed. However, in the actual use scenario, if there are 8 external sensors, among which 5 are input external sensors and 3 are output external sensors. If this hardware device is used to connect these 8 external sensors, 2 devices are required to complete.
[0005] Because there are 5 input external sensors, but the isolated input pins of a single device are only 4. So 2 devices are required to completely connect 5 input sensors. This not only causes redundancy of equipment, but also the second device wastes 3 isolated input pins and 4 isolated output pins in vain. Summary of the Utility Model
[0006] In order to solve the technical problems existing in the prior art, the utility model provides an isolated communication circuit for on-site defining the GPIO pin type of a single-chip microcomputer, and realizes on-site definition of the GPIO pin type by adjusting the peripheral isolation circuit of the GPIO pin.
[0007] To achieve the above object, the utility model is realized by the following technical solutions:
[0008] An isolation communication circuit for on-site defining the GPIO pin type of a single-chip microcomputer, comprising an input / output terminal IO, a peripheral output terminal, a peripheral input terminal, a first opto-isolation circuit and a second opto-isolation circuit. The input / output terminal IO is respectively connected to one ends of the first opto-isolation circuit and the second opto-isolation circuit. The other end of the first opto-isolation circuit is connected to the peripheral output terminal, and the other end of the second opto-isolation circuit is connected to the peripheral input terminal.
[0009] Further, the first opto-isolation circuit comprises a connected first opto-isolation and a first triode.
[0010] Further, the third terminal of the first opto-isolation is connected to the collector of the first triode.
[0011] Further, the first terminal of the first opto-isolation is connected to the first power output terminal, the sixth terminal is connected to the peripheral output terminal, and the fourth terminal is connected to the third peripheral interface terminal.
[0012] Further, the base of the first triode is connected to the input / output terminal IO, and the emitter is grounded.
[0013] Further, the second opto-isolation circuit comprises a connected second opto-isolation and a second triode.
[0014] Further, the fourth terminal of the second opto-isolation is connected to the base of the second triode.
[0015] Further, the first terminal of the second opto-isolation is connected to the peripheral input terminal, the third terminal is connected to the third peripheral interface terminal, and the sixth terminal is connected to the second power output terminal.
[0016] Further, the emitter of the second triode is grounded, and the collector is respectively connected to the third power output terminal and the input / output terminal IO.
[0017] Further, a third resistor is connected in series between the third power output terminal and the input / output terminal IO.
[0018] The beneficial effects of the present utility model:
[0019] The present utility model improves at the basic circuit level to solve the technical problems existing in the prior art. By integrating the peripheral isolation input or output type circuits of the GPIO pins, the on-site definition of the input or output type of the GPIO pins is realized.
[0020] The present utility model can realize the on-site definition of the input and output of the single-chip microcomputer GPIO port, without fixedly setting some GPIO ports as input or output, solving the problem of fixed setting of GPIO. It improves the environmental adaptability of the device, effectively reduces the usage quantity of the product, and rationally utilizes the GPIO port resources. Brief Description of the Drawings
[0021] The drawings are used to provide a further understanding of the present utility model, and constitute a part of the specification. Together with the embodiments of the present utility model, they are used to explain the present utility model, and do not constitute a limitation to the present utility model.
[0022] Figure 1 It is a circuit diagram of the isolation communication circuit of the present utility model. Detailed Embodiments
[0023] The following further describes the present utility model in conjunction with the drawings and specific embodiments.
[0024] Term Explanation:
[0025] Single-chip microcomputer: It is an integrated circuit chip. It uses very large scale integrated circuit technology to integrate a central processing unit CPU with data processing capabilities, a random access memory RAM, a read-only memory ROM, multiple I / O ports, an interrupt system, a timer / counter, etc. (possibly also including a display driver circuit, a pulse width modulation circuit, an analog multiplexer, an A / D converter, etc.) into a small and complete microcomputer system on a silicon chip.
[0026] GPIO pin: The abbreviation of General-Purpose Input / Output. Through this type of pin, the single-chip microcomputer can obtain the input high and low level signals or output high and low level signals externally.
[0027] The peripheral isolation circuit of the single-chip microcomputer GPIO pin is used to protect the single-chip microcomputer from damage caused by excessive voltage or current.
[0028] As Figure 1 shown, the embodiment of the present utility model provides an isolation communication circuit for defining the GPIO pin type on-site of a single-chip microcomputer, including an input / output terminal IO, a peripheral output terminal, a peripheral input terminal, a first optocoupler isolation circuit, and a second optocoupler isolation circuit. One end of the input / output terminal IO is respectively connected to the first optocoupler isolation circuit and the second optocoupler isolation circuit. The other end of the first optocoupler isolation circuit is connected to the peripheral output terminal, and the other end of the second optocoupler isolation circuit is connected to the peripheral input terminal.
[0029] In this embodiment, the input / output terminal IO is the GPIO pin of the single-chip microcomputer. Through this type of pin, the single-chip microcomputer can obtain the input high and low level signals or output high and low level signals externally.
[0030] In this embodiment, the first opto-isolation circuit includes a connected first opto-isolator U1 and a first triode Q1. Specifically, the first end of the first opto-isolator U1 is connected to the first power output terminal OUT1, the third end of the first opto-isolator U1 is connected to the collector of the first triode Q1, the base of the first triode Q1 is connected to the input / output terminal IO, the emitter of the first triode Q1 is grounded to GND, the sixth end of the first opto-isolator U1 is connected to the peripheral output terminal 0J2, and the fourth end of the first opto-isolator U1 is connected to the third peripheral interface terminal J3.
[0031] A first resistor R1 is connected in series between the first opto-isolator U1 and the peripheral output terminal 0J2 to limit the magnitude of the current and prevent the circuit from being burned out due to excessive current. Specifically, the sixth end of the first opto-isolator U1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the peripheral output terminal 0J2.
[0032] A first capacitor C1 is connected in parallel with the first triode Q1 to prevent abnormal peripheral current caused by unstable voltage. Specifically, the base of the first triode Q1 is connected to the first end of the first capacitor C1, and the emitter of the first triode Q1 is connected to the second end of the first capacitor C1.
[0033] In this embodiment, the second opto-isolation circuit includes a connected second opto-isolator U2 and a second triode Q2. Specifically, the first end of the second opto-isolator U2 is connected to the peripheral input terminal 1J2, the third end of the second opto-isolator U2 is connected to the third peripheral interface terminal J3, the sixth end of the second opto-isolator U2 is connected to the second power output terminal OUT2, the fourth end of the second opto-isolator U2 is connected to the base of the second triode Q2, the emitter of the second triode Q2 is grounded to GND, and the collector of the second triode Q2 is connected to the third power output terminal OUT3 and the input / output terminal IO respectively.
[0034] A second resistor R2 is connected in series between the second opto-isolator U2 and the peripheral input terminal 1J2 to limit the magnitude of the current of the external device and prevent the circuit from being burned out due to excessive current. Specifically, the first end of the second opto-isolator U2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the peripheral input terminal 1J2.
[0035] A second capacitor C2 is connected in parallel with the second triode Q2 to prevent abnormal peripheral isolation circuit caused by unstable voltage. Specifically, the base of the second triode Q2 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the emitter of the first triode Q1.
[0036] A third resistor R3 is connected in series between the third power output terminal OUT3 and the input / output terminal IO to limit the current input to the pin of the microcontroller chip, i.e., the input / output terminal IO, and prevent the chip and the circuit from being damaged due to excessive current. Specifically, the third power output terminal OUT3 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the input / output terminal IO.
[0037] The above-mentioned first power output terminal OUT1, second power output terminal OUT2, and third power output terminal OUT3 are all outputs of the DC power supply for the microcontroller chip; GND is the ground of the DC power supply for the microcontroller chip.
[0038] For the external devices of the microcontroller, a simple schematic is shown on the right side of the circuit diagram. The VCC of the external device's DC power supply is connected to the first external device interface terminal J1, and the third external device interface terminal J3 is connected to the ground VGND of the external DC power supply.
[0039] In some embodiments, the first opto-isolator U1 and the second opto-isolator U2 use opto-coupler devices of the TLP185 model, and the first transistor Q1 and the second transistor Q2 use the S8050 model. The selection of the above models is only an example, and components of mainstream models can be used, and can be flexibly selected according to actual situations.
[0040] Based on the above circuit, the working principle of the present invention is described in detail as follows:
[0041] As Figure 1 shown, when the GPIO pin is defined as an input pin on-site, if a high / low level input device is connected at this time, the VCC lead of the device is connected to J1, the signal lead is connected to 1J2, and the GND lead is connected to J3. When the signal lead of the input device is at a high level, the first end 1 to the third end 3 of the second opto-isolator U2 conducts, and the sixth end 6 to the fourth end 4 conducts. At this time, the second transistor Q2 conducts, and the voltage collected by the input / output terminal IO pin is about 0V, which is a low level. The microcontroller recognizes it as 0, and at the same time, the first transistor Q1 does not conduct. The first end 1 to the third end 3 of the first opto-isolator U1 does not conduct, so the sixth end 6 to the fourth end 4 of the first opto-isolator U1 does not conduct. When the signal line of the input device is at a low level, the first end 1 to the third end 3 of the second opto-isolator U2 does not conduct, so the sixth end 6 to the fourth end 4 does not conduct. At this time, the second transistor Q2 does not conduct, and the voltage collected by the input / output terminal IO pin is about 3.3V, which is a high level. The microcontroller recognizes it as 1, and at the same time, the first transistor Q1 conducts, and the first end 1 to the third end 3 of the first opto-isolator U1 conducts, and the sixth end 6 to the fourth end 4 conducts. Since the external device output terminal 0J2 is floating, there is no current passing through from the sixth end 6 to the fourth end 4.
[0042] If a switch-type input device is connected at this time, the VCC lead of the device is connected to J1, and the GND lead is connected to 1J2. When the switch-type input device is closed, the first end 1 to the third end 3 of the second opto-isolator U2 are conducted, and the sixth end 6 to the fourth end 4 are conducted. At this time, the second triode Q2 is conducted, and the voltage collected by the input / output terminal IO pin is about 0V, which is a low level. The single-chip microcomputer recognizes it as 0, and at the same time, the first triode Q1 is not conducted. The first end 1 to the third end 3 of the first opto-isolator U1 are not conducted, so the sixth end 6 to the fourth end 4 of the first opto-isolator U1 are not conducted. When the switch input device is disconnected, the first end 1 to the third 3 of the second opto-isolator U2 are not conducted, so the sixth end 6 to the fourth end 4 are not conducted. At this time, the second triode Q2 is not conducted, and the voltage collected by the input / output terminal IO pin is about 3.3V, which is a high level. The single-chip microcomputer recognizes it as 1, and at the same time, the first triode Q1 is conducted, and the first end 1 to the third end 3 of the first opto-isolator U1 are conducted, and the sixth end 6 to the fourth end 4 are conducted. Because 0J2 is floating, there is no current passing through the sixth end 6 to the fourth end 4 of the first opto-isolator U1.
[0043] When the GPIO pin is defined as an output pin on-site, if a high / low level output device is connected at this time, the VCC lead of the device is connected to J1, the signal lead is connected to 0J2, and the GND lead is connected to J3. When the IO lead is at a high level, the first triode Q1 is conducted, and the first end 1 to the third end 3 of the first opto-isolator U1 are conducted, so the sixth end 6 to the fourth end 4 are conducted, and the voltage collected at the 0J2 end is about 0V. Because 1J2 is floating, the second triode Q2 is not conducted. When the IO lead is at a low level, the first triode Q1 is not conducted, and the first end 1 to the third end 3 of the first opto-isolator U1 are not conducted, so the sixth end 6 to the fourth end 4 are not conducted. Therefore, the voltage collected at the 0J2 connection end is about the VCC voltage. Because 1J2 is floating, the second triode Q2 is not conducted.
[0044] If a switch output device is connected for testing, the VCC of the device is connected to J1, and the GND is connected to 0J2. When the IO lead is at a high level, the first triode Q1 is conducted, and the first end 1 to the third end 3 of the first opto-isolator U1 are conducted, so the sixth end 6 to the fourth end 4 are conducted, and the switch device is conducted. Because 1J2 is floating, the second triode Q2 is not conducted. When the IO lead is at a low level, the first triode Q1 is not conducted, and the first end 1 to the third end 3 of the first opto-isolator U1 are not conducted, so the sixth end 6 to the fourth end 4 are not conducted. Therefore, the switch device is not conducted. Because 1J2 is floating, the second triode Q2 is not conducted.
[0045] For the above principle, in the example given in the background art, 8 pins are set as field-definable isolation pins at the initial design of the hardware product. Similarly, when connecting 8 external sensors, 5 of them are input external sensors and 3 are output external sensors. Then, only by setting 5 pins as input pins and 3 pins as output pins on-site, these 8 external sensors can be directly connected.
[0046] Although the specific implementation manners of the present invention have been described in conjunction with the accompanying drawings above, they do not limit the protection scope of the present invention. Those skilled in the art should understand that, based on the technical solution of the present invention, various modifications or deformations that can be made by those skilled in the art without creative efforts still fall within the protection scope of the present invention.
Claims
1. An isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer, characterized in that: The device comprises an input / output terminal IO, an external device output terminal, an external device input terminal, a first optocoupler isolation circuit and a second optocoupler isolation circuit. The input / output terminal IO is respectively connected to one end of the first optocoupler isolation circuit and the second optocoupler isolation circuit, the other end of the first optocoupler isolation circuit is connected to the external device output terminal, and the other end of the second optocoupler isolation circuit is connected to the external device input terminal.
2. The isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer as claimed in claim 1, characterized in that: The first optocoupler isolation circuit includes a first optocoupler isolation and a first transistor connected.
3. The isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer as claimed in claim 2, characterized in that: The third end of the first optical coupler is connected to the collector of the first transistor.
4. The isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer as claimed in claim 3, characterized in that: The first end of the first optical coupler is connected to the first power supply output end, the sixth end is connected to the peripheral output end, and the fourth end is connected to the third peripheral interface end.
5. The isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer as claimed in claim 3, characterized in that: The base of the first transistor is connected to the input / output terminal IO, and the emitter is grounded.
6. The isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer as claimed in claim 1, characterized in that: The second optocoupler isolation circuit includes a second optocoupler isolation and a second transistor connected.
7. The isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer as claimed in claim 6, characterized in that: The fourth end of the second optical coupler is connected to the base of the second transistor.
8. The isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer as claimed in claim 7, characterized in that: The first end of the second optical coupler is connected to the peripheral input end, the third end is connected to the third peripheral interface end, and the sixth end is connected to the second power supply output end.
9. The isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer as claimed in claim 7, characterized in that: The emitter of the second transistor is grounded, and the collector is connected to the third power supply output terminal and the input / output terminal IO respectively.
10. The isolated communication circuit for defining GPIO pin types on-site in a single-chip microcomputer as claimed in claim 9, characterized in that: A third resistor is connected in series between the third power supply output terminal and the input / output terminal IO.