Test system applied to storage and calculation integrated chip

Abstract

The utility model provides a test system applied to a storage and calculation integrated chip. The test system comprises a test carrier plate; the test carrier plate is provided with a chip test seat; a plurality of SATA interfaces, wherein the SATA interfaces are electrically connected to the chip test seat; the JTAG interface is electrically connected to the chip testing seat; at least two LAN interfaces, wherein the LAN interfaces are electrically connected to the chip test seat; a plurality of PCIE interfaces, wherein the PCIE interfaces are electrically connected to the chip test seat; the at least two optical fiber interfaces are electrically connected to the chip testing seat; and the power interface is electrically connected to the chip testing seat. According to the utility model, the problem of low performance test efficiency of a high-integration-level storage and calculation integrated chip in the prior art can be solved.

Description

Technical Field

[0001] The utility model belongs to the field of chip testing, and more specifically, relates to a testing system applied to a memory - in - computing chip. Background Art

[0002] A memory - in - computing chip refers to a single chip that can implement functions such as data acquisition, hardware encryption and decryption, data calculation, data processing, and data storage. In actual use, the memory - in - computing chip can be field - programmed according to the specific needs of users. In related technologies, memory - in - computing chips can be divided into two types: low - integration - degree and high - integration - degree. A low - integration - degree memory - in - computing chip means that only a main control chip and an FPGA chip are integrated in the package, while other chips required for the operation of the memory - in - computing chip, such as FLASH chips, DDR chips, and crystal oscillator chips, are arranged on the peripheral circuit board of the package. A high - integration - degree memory - in - computing chip means that its involved sub - chips, including FLASH chips, FPGA chips, SATA selectors, DDR chips, main control chips, crystal oscillator chips, and hundreds of passive devices, are all integrated within the package. In recent years, high - integration - degree memory - in - computing chips have shown a trend of gradually replacing low - integration - degree memory - in - computing chips.

[0003] Currently, during the research and development stage of memory - in - computing chips, it is often necessary to test the performance of memory - in - computing chips. For high - integration - degree memory - in - computing chips, the test board used includes a test carrier board and a chip test socket, a power interface, and a communication interface of a predetermined type arranged on the test carrier board. Therefore, in order to test the performance of the memory - in - computing chip under different communication interfaces, a set of test boards needs to be configured, with each test board configured with a corresponding communication interface. When testing the performance of the memory - in - computing chip under a predetermined communication interface, the corresponding test board is used for testing. However, when implementing the performance test of the memory - in - computing chip based on such test boards, it is time - consuming and laborious, and the test efficiency is low. Summary of the Utility Model

[0004] The purpose of the utility model is to solve the problem of low test efficiency for the performance of high - integration - degree memory - in - computing chips in related technologies.

[0005] To achieve the above - mentioned purpose, the utility model provides a testing system applied to a memory - in - computing chip, and the testing system includes a test carrier board;

[0006] Arranged on the test carrier board are:

[0007] A chip test socket;

[0008] Multiple SATA interfaces, and the SATA interfaces are electrically connected to the chip test socket;

[0009] A JTAG interface, and the JTAG interface is electrically connected to the chip test socket;

[0010] At least two LAN interfaces, and the LAN interfaces are electrically connected to the chip test socket;

[0011] Multiple PCIE interfaces, and the PCIE interfaces are electrically connected to the chip test socket;

[0012] At least two optical fiber interfaces, and the optical fiber interfaces are electrically connected to the chip test socket;

[0013] A power supply interface, and the power supply interface is electrically connected to the chip test socket.

[0014] Optionally, the SATA interface is a SATA3.0 interface for connecting to a test server through a SATA3.0 transmission line.

[0015] Optionally, the JTAG interface is used to connect to a test server through a USB to JTAG high-speed emulator.

[0016] Optionally, the LAN interface is used to connect to a test server through a gigabit network cable.

[0017] Optionally, the PCIE interface is used to connect to a test server through a PCIE extension cable.

[0018] Optionally, the optical fiber interface is used to connect to a test server through an optical fiber.

[0019] Optionally, the power supply interface is used to connect to a test power supply, and the power supply interface is compatible with digital power and ATX power.

[0020] The beneficial effects of the present utility model are as follows:

[0021] The test system of the present utility model is applied to a memory and computing integrated chip. A chip test socket and a variety of interfaces electrically connected to the chip test socket are provided on the test carrier board, including a SATA interface, a JTAG interface, a LAN interface, a PCIE interface, an optical fiber interface, and a power supply interface. The test system of the present utility model applied to a memory and computing integrated chip realizes the compatibility of multiple communication interfaces on a single test board. By using this test system, the performance test of the memory and computing integrated chip under different communication interfaces can be conveniently and quickly realized, and thus the problem of low performance test efficiency of high-integration memory and computing integrated chips in the related technology is effectively solved.

[0022] Other features and advantages of the present utility model will be described in detail in the subsequent specific implementation part. Description of the Drawings

[0023] The present utility model can be better understood by referring to the descriptions made in conjunction with the accompanying drawings below, where the same or similar reference numerals are used throughout all the drawings to denote the same or similar components.

[0024] Figure 1 FIG. 4 shows a schematic structural diagram of a test system applied to a memory - in - computing chip according to an embodiment of the present utility model;

[0025] Figure 2 FIG. 5 shows a schematic block diagram of a test system applied to a memory - in - computing chip according to an embodiment of the present utility model. Detailed Embodiments

[0026] In order to enable those skilled in the art to more fully understand the technical solutions of the present utility model, the exemplary embodiments of the present utility model will be described more comprehensively and in detail below in conjunction with the accompanying drawings. Obviously, one or more of the embodiments of the present utility model described below are merely one or more of the specific ways to implement the technical solutions of the present utility model, and are not exhaustive. It should be understood that other ways belonging to a general inventive concept of the present utility model can be used to implement the technical solutions of the present utility model, and should not be limited by the exemplary embodiments described. Based on one or more embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0027] Embodiment: Figure 1 FIG. 6 shows a schematic structural diagram of a test system applied to a memory - in - computing chip according to an embodiment of the present utility model, Figure 2 FIG. 7 shows a schematic block diagram of a test system applied to a memory - in - computing chip according to an embodiment of the present utility model.

[0028] Referring to Figure 1 and Figure 2 , the test system applied to a memory - in - computing chip according to an embodiment of the present utility model includes a test carrier board;

[0029] Disposed on the test carrier board are:

[0030] A chip test socket;

[0031] A plurality of SATA interfaces, and the SATA interfaces are electrically connected to the chip test socket;

[0032] A JTAG interface, and the JTAG interface is electrically connected to the chip test socket;

[0033] At least two LAN interfaces, and the LAN interfaces are electrically connected to the chip test socket;

[0034] Multiple PCIE interfaces, and the PCIE interfaces are electrically connected to the chip test socket;

[0035] At least two optical fiber interfaces, and the optical fiber interfaces are electrically connected to the chip test socket;

[0036] A power supply interface, and the power supply interface is electrically connected to the chip test socket.

[0037] Specifically, in the embodiment of the present invention, the memory-computation integrated chip to be tested is arranged on the chip test socket. The memory-computation integrated chip integrates 7 chips and hundreds of passive devices within an effective area of 45mm * 45mm. Among them, the 7 chips include 2 FLASH chips, 1 FPGA chip, 1 SATA selector, 1 DDR chip, 1 main control chip, and 1 crystal oscillator.

[0038] Further, in the embodiment of the present invention, the SATA interface is a SATA3.0 interface, which is used to be connected to the test server through a SATA3.0 transmission line.

[0039] Still further, in the embodiment of the present invention, the JTAG interface is used to be connected to the test server through a USB to JTAG high-speed emulator.

[0040] Still further, in the embodiment of the present invention, the LAN interface is used to be connected to the test server through a gigabit network cable.

[0041] Still further, in the embodiment of the present invention, the PCIE interface is used to be connected to the test server through a PCIE extension cable.

[0042] Still further, in the embodiment of the present invention, the optical fiber interface is used to be connected to the test server through an optical fiber.

[0043] Still further, in the embodiment of the present invention, the power supply interface is used to be connected to the test power supply, and the power supply interface is compatible with digital power and ATX power.

[0044] Specifically, the test system of the embodiment of the present invention applied to the memory-computation integrated chip is configured with:

[0045] Two LAN interfaces. Based on the LAN interfaces, the connection between the memory-computation integrated chip and the test server can be realized, and then the computing power of the memory-computation integrated chip can be tested;

[0046] One JTAG interface. Based on the JTAG interface, the connection between the memory-computation integrated chip and the test server can be realized, and then the computing power of the memory-computation integrated chip can be tested;

[0047] One power supply interface, which is used to connect to the test power supply;

[0048] Seven SATA interfaces. Based on the SATA interfaces, the connection between the memory - computing integrated chip and the test server can be realized, and then the computing power of the memory - computing integrated chip can be tested;

[0049] Three PCIE interfaces. Based on the PCIE interfaces, the connection between the memory - computing integrated chip and the test server can be realized, and then the computing power of the memory - computing integrated chip can be tested;

[0050] Two fiber - optic interfaces. Based on the fiber - optic interfaces, the connection between the memory - computing integrated chip and the test server can be realized, and then the computing power of the memory - computing integrated chip can be tested.

[0051] The test method realized by the test system for the memory - computing integrated chip according to the embodiment of the present utility model includes:

[0052] Step1: Place the memory - computing integrated chip to be tested in the chip test socket;

[0053] Step2: Connect the 12V digital power supply to the power interface to power on the memory - computing integrated chip;

[0054] Step3: Static power consumption test: Power on the PC motherboard and turn on the computer. When the memory - computing integrated chip only maintains the power - on state, use the digital power supply to test the chip current, and the digital power supply directly displays the current and power consumption of the test chip in the static state;

[0055] Step4: Dynamic power consumption test: On the test server, use the Atto disk software to test the chip read - write speed, and the power supply directly displays the current and power consumption of the test chip in the dynamic (read - write state);

[0056] Step5: Use the JTAG interface to test the chip computing power: Connect the memory - computing integrated chip to be tested to the USB - to - JTAG high - speed emulator through the emulator connection line, and then connect it to the test server. Input the test cases to test the chip computing power;

[0057] Step6: Use the LAN interface to test the chip computing power: Connect the chip to the test server through the LAN interface using a gigabit network cable. Input the test cases to test the chip computing power;

[0058] Step7: Use the SATA interface to test the chip computing power: Connect the chip to the test server through the SATA3.0 interface using a SATA3.0 transmission line. Input the test cases to test the chip computing power;

[0059] Step8: Use the PCIE interface to test the chip computing power: Connect the chip to the test server through the PCIE interface using a PCIE extension cable. Input the test cases to test the chip computing power;

[0060] Step9: Use the optical fiber interface to test the computing power of the chip: Connect the chip to the test server through the optical fiber interface and the optical fiber, input test cases, and test the computing power of the chip.

[0061] The test system for the memory - in - computing chip according to the embodiment of the present utility model realizes the compatibility of multiple communication interfaces such as SATA3.0 interface, JTAG interface, LAN interface, power interface, PCIE interface, optical port, etc. on a single test board to test the computing power of the chip under different interfaces, without the need to develop additional carrier boards for single - interface testing, saving test costs and improving test efficiency.

[0062] Although the above describes one or more embodiments of the present utility model, those of ordinary skill in the art should understand that the present utility model can be implemented in any other form without departing from its gist and scope. Therefore, the above - described embodiments are illustrative rather than restrictive, and many modifications and substitutions are obvious to those of ordinary skill in the art in the technical field without departing from the spirit and scope of the present utility model as defined by the appended claims.

Claims

1. A test system for a storage-computing integrated chip, characterized in that: Including test carrier board; The test carrier is provided with: Chip test socket; A plurality of SATA interfaces, wherein the SATA interfaces are electrically connected to the chip test socket; A JTAG interface, the JTAG interface is electrically connected to the chip test socket; At least two LAN interfaces, the LAN interfaces being electrically connected to the chip test socket; A plurality of PCIE interfaces, wherein the PCIE interfaces are electrically connected to the chip test socket; At least two optical fiber interfaces, the optical fiber interfaces are electrically connected to the chip test seat; A power interface is electrically connected to the chip test socket.

2. The test system for a storage-computing integrated chip according to claim 1, characterized in that: The SATA interface is a SATA 3.0 interface, which is used to connect to the test server via a SATA 3.0 transmission line.

3. The test system for a storage-computing integrated chip according to claim 1, characterized in that: The JTAG interface is used to connect to the test server via a USB to JTAG high-speed emulator.

4. The test system for a storage-computing integrated chip according to claim 1, characterized in that: The LAN interface is used to connect to the test server via a Gigabit network cable.

5. The test system for storage-computing integrated chip according to claim 1, characterized in that: The PCIE interface is used to connect to the test server via a PCIE extension cable.

6. The test system for storage-computing integrated chip according to claim 1, characterized in that: The optical fiber interface is used to connect to the test server via optical fiber.

7. The test system for a storage-computing integrated chip according to claim 1, characterized in that: The power supply interface is used to connect to a test power supply, and the power supply interface is compatible with a digital power supply and an ATX power supply.

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