Gate lead-out piece and power semiconductor device with same

Abstract

The utility model provides a gate pole leading-out piece and a power semiconductor device with the same, and the gate pole leading-out piece comprises a bottom leading-out structure, the middle part of which is provided with an avoiding hole; and the spoke structure comprises a sleeve and a plurality of connecting plates arranged on the sleeve, the sleeve is arranged at the receding hole, and the plurality of connecting plates are connected with the gate pole of the chip. According to the technical scheme of the invention, the problem of large parasitic inductance of a device in the prior art is effectively solved.

Description

Technical Field

[0001] The utility model relates to the technical field of power semiconductor devices, and in particular, to a gate lead-out component and a power semiconductor device having the same. Background Art

[0002] Integrated gate-commutated thyristor (IGCT) is a high-performance power semiconductor device that combines thyristor and gate drive technologies and can achieve fast and reliable current turn-off without an external commutation circuit. IGCTs are mainly used in medium-voltage and high-current industrial applications such as motor drives, power transmission, and inverters in renewable energy systems.

[0003] In the prior art, the gate of the chip of the integrated gate-commutated thyristor is led out through a gate lead-out structure, and the gate lead-out structure includes a gate lead-out flange and gate spokes arranged on the gate lead-out flange. When the distance between the gate of the chip and the gate lead-out flange is large, in order to connect the gate lead-out flange to the gate of the chip, it is necessary to stretch the gate spokes towards the direction close to the gate of the chip. However, such a setting will increase the gate-cathode parasitic inductance and affect the turn-off ability of the device. Summary of the Utility Model

[0004] The main purpose of the present utility model is to provide a gate lead-out component and a power semiconductor device having the same, so as to solve the problem of large parasitic inductance of the device in the related art.

[0005] To achieve the above object, according to one aspect of the present utility model, a gate lead-out component is provided, including: a bottom lead-out structure, with an avoidance hole arranged in the middle of the bottom lead-out structure; a spoke structure, the spoke structure includes a sleeve and a plurality of connecting plates arranged on the sleeve, the sleeve is arranged at the avoidance hole, and the plurality of connecting plates are all connected to the gate of the chip.

[0006] Further, at least one notch is arranged on the sleeve, and the notch extends along the axial direction of the sleeve and penetrates through the sleeve.

[0007] Further, the plurality of connecting plates are arranged at one end of the sleeve far from the bottom lead-out structure, and each connecting plate extends towards the inside of the sleeve.

[0008] Further, the plurality of connecting plates are evenly arranged in the circumferential direction of the avoidance hole.

[0009] Further, the thickness of the bottom lead-out structure, the wall thickness of the sleeve, and the thickness of the connecting plate are the same.

[0010] Further, the wall thickness of the sleeve is between 0.3 mm and 1.5 mm.

[0011] Further, the distance between the two ends of the sleeve is between 3 mm and 25 mm.

[0012] Furthermore, the gate lead is an integrally formed structure.

[0013] According to another aspect of the present utility model, a power semiconductor device is provided, including: a first electrode and a second electrode; a chip disposed between the first electrode and the second electrode and electrically connected to both the first electrode and the second electrode; a gate lead, the gate lead being the above-mentioned gate lead, the spoke structure of the gate lead being electrically connected to the gate of the chip, and the gate lead being disposed around the outer periphery of the first electrode.

[0014] Furthermore, the power semiconductor device further includes a gate insulator disposed on the first electrode and between the first electrode and the gate lead.

[0015] Furthermore, the first electrode includes a support platform and a connection platform. The side portion of the connection platform is located in the vertical space where the side portion of the support platform is located. An accommodation portion is formed between the top of the support platform and the side portion of the connection platform. The gate insulator is disposed at the accommodation portion, and the gate lead is disposed around the outer periphery of the gate insulator.

[0016] Furthermore, the power semiconductor device further includes an elastic component disposed between the gate insulator and the spoke structure.

[0017] Furthermore, in the radial direction of the avoidance hole, the minimum distance L between the side of the spoke structure close to the support platform and the side portion of the support platform is between 0.5 mm and 6 mm.

[0018] Furthermore, the thickness of the first electrode is greater than the thickness of the second electrode.

[0019] Furthermore, the ratio of the thickness of the second electrode to the thickness of the first electrode is greater than 0 and less than or equal to 0.6.

[0020] Applying the technical solution of the present utility model, the gate lead includes a bottom lead structure and a spoke structure. An avoidance hole is provided in the middle of the bottom lead structure. The spoke structure includes a sleeve and a plurality of connecting plates. The sleeve is disposed at the avoidance hole, and the plurality of connecting plates are connected to the gate of the chip. Through the above settings, the gate of the chip can be led out through the plurality of connecting plates, the sleeve, and the bottom lead structure. With the setting of the sleeve structure, the current will be more evenly distributed throughout the structure of the sleeve, and the generated magnetic field will also be more uniform. Since the current direction inside the sleeve is opposite to the current direction outside, the internal and external magnetic fields will cancel each other out, thereby reducing the parasitic inductance of the device. Therefore, the technical solution of the present application effectively solves the problem of large parasitic inductance of the device in the related art. Description of the Drawings

[0021] The accompanying drawings of the specification, which form a part of this application, are used to provide a further understanding of the present utility model. The schematic embodiments of the present utility model and their descriptions are used to explain the present utility model and do not constitute an improper limitation of the present utility model. In the drawings:

[0022] Figure 1 Shows a three-dimensional structural schematic diagram of an embodiment of a gate lead of the present utility model;

[0023] Figure 2 Shows Figure 1 A cross-sectional schematic diagram of the gate lead of

[0024] Figure 3 Shows Figure 1 A top-view structural schematic diagram of the gate lead of

[0025] Figure 4 Shows Figure 1 A three-dimensional structural schematic diagram of another structure of the gate lead of

[0026] Figure 5 Shows Figure 1 A three-dimensional structural schematic diagram of another structure of the gate lead of

[0027] Figure 6 Shows Figure 1 A three-dimensional structural schematic diagram of another structure of the gate lead of

[0028] Figure 7 Shows Figure 1 A three-dimensional structural schematic diagram of another structure of the gate lead of

[0029] Figure 8 Shows a cross-sectional schematic diagram of the three-dimensional structure of an embodiment of a power semiconductor device according to the present utility model;

[0030] Figure 9 Shows Figure 8 A cross-sectional schematic diagram of an embodiment of the power semiconductor device of

[0031] Figure 10 Shows Figure 8 A schematic diagram of the commutation loop current path of the power semiconductor device of

[0032] Figure 11 Shows Figure 8 A broken-line graph of the parasitic inductance of the power semiconductor device of

[0033] Figure 12 Shows Figure 8 A schematic diagram of the correspondence relationship between the series-parallel ratio coefficient β and the x ratio of the power semiconductor device of ; where the x ratio is the ratio of the unilateral thermal resistance to the series thermal resistance.

[0034] Among them, the above-mentioned drawings include the following reference numerals:

[0035] 10. Bottom lead-out structure; 11. Avoidance hole; 20. Spoke structure; 21. Sleeve; 211. Notch; 22. Connecting plate; 100. First electrode; 101. Support platform; 102. Connecting platform; 110. Second electrode; 120. Chip; 130. Gate insulator; 140. Elastic component. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and in no way restrictive of the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0037] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0038] Unless otherwise specifically stated, the relative arrangements of the components and steps set forth in these embodiments, numerical expressions, and values do not limit the scope of the present invention. At the same time, it should be understood that, for the sake of convenience of description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationships. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and devices should be regarded as part of the specification. In all the examples shown and discussed herein, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that: similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0039] During the hard turn-off process of an IGCT (Integrated Gate Commutated Thyristor) device, it is necessary to quickly transfer the gate current and establish a stable blocking state. The magnitude of the package parasitic inductance directly affects the turn-off speed and reliability. A low-inductance package can reduce the voltage spike and current tail phenomenon during turn-off, thereby improving the turn-off performance of the device. To achieve fast turn-off, the package parasitic inductance of the IGCT device needs to be controlled at an extremely low level. To reduce the parasitic inductance, the IGCT device usually adopts an integrated gate drive structure, and reduces the parasitic inductance by optimizing the PCB layout and wiring method. In addition, the magnitude of the package parasitic inductance also directly affects the turn-off characteristics of the IGCT device. A lower parasitic inductance can reduce the overvoltage and current tail during turn-off, thereby reducing the turn-off loss and dynamic avalanche effect of the device. At the same time, a low-inductance package helps to achieve a stable transition of the IGCT device from the thyristor mode to the transistor mode. Therefore, the hard turn-off of the IGCT device requires a low-inductance package to ensure fast and reliable turn-off ability, and the optimization of the package design is the key to achieving this goal.

[0040] In the traditional packaging structure of an IGCT device, the gate of the GCT (Gate Commutated Thyristor) chip is generally led out by a spoke-shaped gate lead flange. The structure of this lead flange is to lead out multiple independent spokes from the inside of a circular flange. The spokes are evenly distributed, have the same length, and are in the same plane as the outer ring. The ends of the spokes are connected to the gate of the GCT chip through a gate molybdenum ring to realize the connection of the control loop. To avoid short-circuiting of the gate spokes with the cathode on the lower side, an insulating sleeve needs to be put on each spoke.

[0041] Based on the traditional packaging structure of an IGCT device, in order to further reduce the package junction-to-case thermal resistance, a packaging scheme of anode thinning and cathode thickening is proposed. As the thickness of the cathode electrode increases significantly, it is necessary to match and set the gate lead-out structure. According to the existing design idea, it is necessary to bend the gate spokes upward (i.e., in the direction close to the anode) to adapt to the thicker cathode electrode, but such a setting will result in a large parasitic inductance of the device, seriously restricting the improvement of the device turn-off ability.

[0042] Through parasitic parameter simulation analysis, it can be known that changing the number of spokes affects the package parasitic inductance. As the number of spokes increases, the package parasitic inductance decreases monotonically. Therefore, in order to achieve the purpose of reducing the parasitic inductance, the number of spokes can be increased. However, increasing the number of spokes will bring greater assembly difficulty. Based on the above general rule, in order to minimize the parasitic inductance, part of the structure of the gate lead-out part in this embodiment is interconnected to finally form a sleeve. Through simulation verification, the sleeve-shaped gate lead-out structure significantly reduces the gate-cathode parasitic inductance and significantly improves the device turn-off ability.

[0043] The gate lead component of this embodiment mainly solves the problem of low-inductance packaging of press-fit devices, and proposes a gate lead component and a power semiconductor device having the same, which can reduce the parasitic inductance of the device control loop and improve the turn-off ability of the device.

[0044] As Figures 1 to 3 shown, the gate lead component of this embodiment includes: a bottom lead structure 10 and a spoke structure 20. An avoidance hole 11 is provided in the middle of the bottom lead structure 10. The spoke structure 20 includes a sleeve 21 and a plurality of connecting plates 22 provided on the sleeve 21. The sleeve 21 is provided at the avoidance hole 11, and the plurality of connecting plates 22 are all connected to the gate of the chip 120.

[0045] Applying the technical solution of this embodiment, the gate lead component includes a bottom lead structure 10 and a spoke structure 20. An avoidance hole 11 is provided in the middle of the bottom lead structure 10. The spoke structure 20 includes a sleeve 21 and a plurality of connecting plates 22. The sleeve 21 is provided at the avoidance hole 11, and the plurality of connecting plates 22 are connected to the gate of the chip 120. Through the above settings, the gate of the chip 120 can be led out through the plurality of connecting plates 22, the sleeve 21, and the bottom lead structure 10. With the setting of the sleeve 21, the current will be more evenly distributed in the entire structure of the sleeve 21, and the generated magnetic field will also be more uniform. Since the current direction inside the sleeve 21 is opposite to the current direction outside, the internal and external magnetic fields will cancel each other out, thereby reducing the parasitic inductance of the device. Therefore, the technical solution of this embodiment effectively solves the problem of large parasitic inductance of the device in the related art.

[0046] The avoidance hole 11 is provided in the middle of the bottom lead structure 10, which means that the axis of the avoidance hole 11 and the axis of the bottom lead structure 10 can be coincidentally arranged or not.

[0047] The bottom lead structure 10 is a bottom lead flange.

[0048] In this embodiment, the sleeve 21 is an integral structure, and no notch 211 is provided on the sleeve 21.

[0049] As Figures 4 to 7 shown, in other embodiments, at least one notch 211 is provided on the sleeve 21, and the notch 211 extends along the axis direction of the sleeve 21 and penetrates the sleeve 21. By providing the notch 211, the mechanical flexibility of the sleeve 21 can be improved, and the structural deformation of the sleeve 21 caused by thermal stress can be reduced.

[0050] As Figure 4As shown, the sleeve 21 has a notch. In the circumferential direction of the sleeve 21, for the two connection plates closest to the notch, one is the first connection plate and the other is the second connection plate. The side wall of the first connection plate facing the second connection plate is flush with the side wall of the notch, and the side wall of the second connection plate facing the first connection plate is flush with the side wall of the notch, that is, the distance between the side walls of the notch is equal to the distance between the side walls of the two adjacent connection plates.

[0051] As Figure 5 shown, the sleeve 21 has two notches. In the circumferential direction of the sleeve 21, the distance between the side walls of the notches is less than the distance between the side walls of the two connection plates closest to the notches. A connection plate is provided between the two notches.

[0052] As Figure 6 shown, the sleeve 21 has two notches. In the circumferential direction of the sleeve 21, the distance between the side walls of the notches is less than the distance between the side walls of the two connection plates closest to the notches. At least two connection plates are provided between the two notches.

[0053] As Figure 7 shown, the sleeve has three notches. In the circumferential direction of the sleeve, the distance between the side walls of the notches is equal to the distance between the side walls of the two adjacent connection plates.

[0054] Of course, in an embodiment not shown in the figure, other numbers of notches can also be provided, and the distance between the side walls of the notches can be less than or equal to the distance between the side walls of the two connection plates closest to the notches.

[0055] As Figure 1 shown, in this embodiment, a plurality of connection plates 22 are provided at one end of the sleeve 21 far from the bottom lead-out structure 10, and each connection plate 22 extends towards the inside of the sleeve 21. Such a setting facilitates the connection of the plurality of connection plates 22 to the device, and further facilitates the connection of the gate lead-out member to the device. Each connection plate 22 extends along the radial direction of the sleeve 21.

[0056] As Figure 3 shown, in this embodiment, a plurality of connection plates 22 are evenly arranged in the circumferential direction of the avoidance hole 11. This facilitates the processing of the connection plates 22. It can also balance the distribution of the gate lead-out current, reduce local overheating caused by current hitting, and make the reliability of the gate lead-out member better.

[0057] The number of the connection plates 22 is between 8 and 22. Such a setting can reduce the parasitic inductance of the gate lead-out member, and further reduce the parasitic inductance of the device.

[0058] The number of the connection plates 22 between 8 and 22 can be 8, 10, 15, 18, 20 or 22.

[0059] As Figures 1 to 3 shown, in this embodiment, the thickness of the bottom lead-out structure 10, the wall thickness of the sleeve 21, and the thickness of the connecting plate 22 are the same. This can improve the overall thermal stability of the packaging structure, reduce the thermal stress and mechanical stress caused by the different thicknesses of the bottom lead-out structure 10, the wall thickness of the sleeve 21, and the thickness of the connecting plate 22, and can improve the reliability and service life of the gate lead-out component.

[0060] The bottom lead-out structure 10 and the sleeve 21 are coaxially arranged.

[0061] The concentricity of the sleeve 21 is between 0 and 0.15 mm. This facilitates the installation of the sleeve 21. Specifically, it can be 0.05 mm, 0.08 mm, 0.1 mm, or 0.15 mm.

[0062] Preferably, the concentricity of the sleeve 21 is between 0 and 0.1 mm.

[0063] As Figures 1 to 3 shown, in this embodiment, the wall thickness of the sleeve 21 is between 0.3 mm and 1.5 mm. By limiting the wall thickness of the sleeve 21, the mechanical strength of the sleeve 21 can be effectively guaranteed, and thus the service life of the gate lead-out component can be guaranteed.

[0064] The wall thickness of the sleeve 21 can be 0.3 mm, 0.5 mm, 0.6 mm, 0.8 mm, 1 mm, 1.2 mm, or 1.5 mm.

[0065] As Figures 1 to 3 shown, in this embodiment, the distance between the two ends of the sleeve 21 is between 3 mm and 25 mm. By setting the distance between the two ends of the sleeve 21, the path length of the gate lead-out of the chip 120 can be optimized, and thus the parasitic inductance of the device can be optimized, and the turn-off speed and reliability of the device can be improved.

[0066] The distance between the two ends of the sleeve 21, that is, the distance between the end where the sleeve is connected to the plurality of connecting plates and the end where the sleeve is connected to the bottom lead-out structure, can be 3 mm, 5 mm, 8 mm, 10 mm, 15 mm, 20 mm, or 25 mm.

[0067] Preferably, the distance between the two ends of the sleeve 21 is between 5 mm and 20 mm.

[0068] As Figure 1 shown, in this embodiment, the gate lead-out component is an integrally formed structure. Through the above settings, the connection points between the various structures of the gate lead-out component can be reduced, which is convenient for the processing and manufacturing of the gate lead-out component, can reduce the complexity and production cost of the packaging structure, improve the mechanical strength and thermal stability of the packaging structure, and reduce the parasitic inductance and thermal resistance of the packaging structure.

[0069] It should be noted that the gate lead is processed by stamping process.

[0070] In other embodiments, the gate lead can be processed by processes such as milling and turning. It is also possible to first process the bottom lead structure 10, then process the sleeve 21, and then process a plurality of connecting plates 22, and finally weld the bottom lead structure 10, the sleeve 21, and the plurality of connecting plates 22 to obtain the gate lead. It is also possible to obtain an integral bottom lead structure 10 and sleeve 21 by milling or turning, then process a plurality of connecting plates 22, and weld the plurality of connecting plates 22 to the sleeve 21 to obtain the gate lead. It is also possible to obtain the spoke structure 20 by milling and turning processes, then process the bottom lead structure 10, and weld the sleeve 21 to the bottom lead structure 10 to obtain the gate lead.

[0071] As Figure 8 shown, the power semiconductor device of this embodiment includes: a first electrode 100, a second electrode 110, a chip 120, and a gate lead. The chip 120 is disposed between the first electrode 100 and the second electrode 110 and is electrically connected to both the first electrode 100 and the second electrode 110. The gate lead is the above-mentioned gate lead. The spoke structure 20 of the gate lead is electrically connected to the gate of the chip 120, and the gate lead is disposed around the outer periphery of the first electrode 100. Current can flow between the first electrode 100, the chip 120, and the second electrode 110, ensuring the conduction of the chip 120. The spoke structure 20 can be connected to the gate of the chip 120, so that the gate of the chip 120 can be led out. The sleeve 21 of the gate lead can not only lead out the gate of the chip 120, but also reduce the parasitic inductance of the device, thereby improving the turn-off speed and reliability of the device. The power semiconductor device with a gate lead also has the above-mentioned advantages.

[0072] The first electrode 100 is the cathode, and the second electrode 110 is the anode.

[0073] The power semiconductor device of this embodiment is an integrated gate-commutated thyristor.

[0074] As Figures 1 to 3 shown, in this embodiment, the power semiconductor device further includes a gate insulator 130. The gate insulator 130 is disposed on the first electrode 100, and the gate insulator 130 is disposed between the first electrode 100 and the gate lead. By providing the gate insulator 130, the gate lead can be separated from the first electrode 100, ensuring electrical isolation between the gate lead and the first electrode 100, avoiding short circuits and arc discharges, ensuring insulation between the gate lead and the first electrode 100, reducing the risk of short circuits and arc discharges, and improving the operating stability of the device.

[0075] As Figure 8As shown, in this embodiment, the first electrode 100 includes a support platform 101 and a connection platform 102. The side portion of the connection platform 102 is located in the vertical space where the side portion of the support platform 101 is located. An accommodation portion is formed between the top of the support platform 101 and the side portion of the connection platform 102. The gate insulator 130 is disposed at the accommodation portion, and the gate lead-out member is disposed on the outer periphery of the gate insulator 130. The support platform 101 can support the connection platform 102. The support platform 101 can also support the gate insulator 130, and the side portion of the connection platform 102 can limit the position of the gate insulator 130 to ensure that the gate insulator 130 is stably placed on the first electrode 100.

[0076] As Figures 8 to 10 shown, in this embodiment, the power semiconductor device further includes an elastic component 140, and the elastic component 140 is disposed between the gate insulator 130 and the spoke structure 20. When the power semiconductor device is in the press-fitting state, the first electrode 100, the chip 120, and the second electrode 110 will be pressed, and then the pressure will be transmitted to the elastic component 140, making the contact between the spoke structure 20 and the gate insulator 130 softer. Disposing the elastic component 140 between the gate insulator 130 and the spoke structure 20 can reduce the current path, and thus can reduce the gate-cathode parasitic inductance of the device.

[0077] The gate insulator 130 includes a first insulating structure and a second insulating structure connected to the first insulating structure. The first insulating structure extends along the direction from the first electrode 100 to the second electrode 110, and the second insulating structure extends radially outward from the first insulating structure. The elastic component is disposed between the second insulating structure and the plurality of connection plates 22.

[0078] The first insulating structure is in contact with the side portion of the connection platform 102, and the second insulating structure is disposed at one end of the support platform 101 close to the connection platform.

[0079] As Figure 8 and Figure 9 shown, in this embodiment, in the radial direction of the avoidance hole 11, the minimum distance L between the side of the spoke structure 20 close to the support platform 101 and the side portion of the support platform 101 is between 0.5 mm and 6 mm. By adjusting the distance between the spoke structure 20 and the support platform 101, the path length of the gate lead-out can be optimized, and thus the gate-cathode parasitic inductance of the device can be reduced. It can also ensure sufficient electrical clearance, avoid short circuits and arc discharges, and improve the electrical safety and reliability of the device.

[0080] The minimum distance L between the side of the spoke structure 20 close to the support platform 101 and the side portion of the support platform 101 is between 0.5 mm and 6 mm, which means the distance between the inner wall of the sleeve 21 and the side portion of the support platform 101 is L, and the value of L is between 0.5 and 6 mm. Specifically, it can be 0.5 mm, 1 mm, 1.5 mm, 3 mm, 4 mm or 5 mm.

[0081] The gate lead component with a sleeve-shaped gate lead flange structure, after being connected to the chip 120, the commutation loop current path of the power semiconductor device is as Figure 10 shown. The gap between the gate lead component and the cathode copper electrode is the core design parameter of the parasitic inductance. The smaller this distance, the smaller the parasitic inductance. However, to avoid short circuit between the gate and the cathode and the limitation of the installation space of the elastic component, this distance should not be too small, that is, the minimum distance between the side of the spoke structure 20 close to the support platform 101 and the side portion of the support platform 101 should not be too small. Preferably, the value of the minimum distance L between the side of the spoke structure 20 close to the support platform 101 and the side portion of the support platform 101 is between 1 mm and 5 mm.

[0082] As Figure 8 shown, in this embodiment, the thickness of the first electrode 100 is greater than the thickness of the second electrode 110. Such a setting can reduce the thermal resistance of the power semiconductor device.

[0083] As Figure 8 shown, in this embodiment, the ratio of the thickness of the second electrode 110 to the thickness of the first electrode 100 is greater than 0 and less than or equal to 0.6. By limiting the ratio of the thickness of the second electrode 110 to the thickness of the first electrode 100, the reduction of the thermal resistance of the power semiconductor device can be ensured.

[0084] In the prior art, the press-pack type power semiconductor device is usually designed as a symmetric structure, that is: the chip is arranged at the center of the device, and the cathode electrode and the anode electrode are arranged approximately symmetrically on both sides of the chip. In this way, after the chip generates heat, the heat can be dissipated along the two paths above and below the chip to ensure the heat dissipation requirement of the power semiconductor device. However, it is difficult to further reduce the device thermal resistance and improve the device current-carrying capacity by adopting the above symmetric structure for the power semiconductor device.

[0085] The power semiconductor device provided in this embodiment can improve the heat transfer efficiency of the device electrode, reduce the device junction-case thermal resistance, and make the chip junction temperature lower during the operation of the device, so as to improve the rated current-carrying capacity of the device, thereby meeting the further heat dissipation requirements of the press-pack type power semiconductor device.

[0086] This embodiment provides a low-inductance packaging structure for a power semiconductor device. The power semiconductor device includes a chip 120, an anode molybdenum sheet, a cathode molybdenum sheet, an upper cover of the anode tube shell, and a base of the cathode tube shell.

[0087] The chip 120 is an integrated chip GCT silicon-based chip, and its size can be 2 inches, 3 inches, 4 inches, 6 inches, 8 inches, etc., and the thickness is between 0.2 mm and 2 mm. It is divided into an active area in the central region and a terminal area in the edge region. The active area is the current-carrying area and the heat-generating area, and the terminal area is the insulating area.

[0088] The anode molybdenum sheet and the cathode molybdenum sheet are made of pure molybdenum, and the thickness is between 0.5 mm and 5 mm. They have a high flatness, and the flatness is less than 5 microns, ensuring that the pressure acting on the chip is very uniform when under pressure. Molybdenum metal has the closest coefficient of thermal expansion to that of the silicon chip among all conductive materials. Therefore, it can buffer the thermal stress between the copper electrode and the silicon chip during temperature cycling and improve the reliability of the chip.

[0089] The upper cover of the anode tube shell is made of oxygen-free copper and includes a second electrode 110 in the central region and a copper flange in the edge part, and the two are interconnected by high-temperature welding.

[0090] The base of the cathode tube shell is made of oxygen-free copper and alumina ceramic, and specifically includes a first electrode 100, a lower flange, a bottom lead-out structure 10, an elastic component 140, a ceramic porcelain ring, and an upper flange. The above components are interconnected by high-temperature welding. The lower flange, the bottom lead-out structure 10, the elastic component 140, the ceramic porcelain ring, and the upper flange are arranged in sequence in the direction from the first electrode 100 to the second electrode 110. The ceramic porcelain ring mainly plays a role in high-voltage insulation, and the creepage distance and electrical clearance meet the high-voltage requirements of 8.5 kV and above. The first electrode 100 has the functions of conducting current and dissipating heat. The lower flange and the upper flange mainly play the roles of interconnection and sealing. The elastic component 140 is stacked by disc springs and gaskets and has a certain elasticity, and will produce a certain displacement under pressure.

[0091] The upper cover of the anode tube shell and the base of the cathode tube shell are interconnected through a cold pressure welding process to achieve the sealing of the device tube shell, providing a sealed protection space for the chip 120. After evacuating the inside and filling it with nitrogen, it isolates the influence of the external environment on the chip 120. Specifically, during cold pressure welding, the copper flange and the upper flange at the edge part of the upper cover of the anode tube shell undergo plastic deformation under pressure, enabling the two flanges to be interconnected at the metal atomic level and completing the cold pressure welding process. This step is carried out in a vacuum mold.

[0092] The gate lead component of this embodiment is a sleeve-shaped gate lead flange structure. It is integrally stamped from oxygen-free copper sheet, and the thickness of the oxygen-free copper sheet is between 0.5 mm and 1.0 mm. Since the height of the sleeve 21 is relatively large, to avoid the copper sheet from breaking during stamping, the stamping process should be carried out in multiple times, and the stamping depth each time should not be too large until the total elongation reaches the designed height. Finally, bendable connecting plates 22 are stamped out at the edge of the sleeve 21, and the connecting plates 22 are evenly distributed. After the gate lead component is stamped, it is integrally welded with the other components of the ceramic package to form a complete cathode package base. The welding process parameters are: the solder is Ag72Cu28 eutectic alloy, the welding temperature is 840 °C, the heating time is 1 h, the holding time is 10 min, the cooling time is 1.5 h, the welding equipment is a brazing furnace, and the protective atmosphere is hydrogen. After welding, a helium mass spectrometer leak detector is used to detect the weld to ensure good welding.

[0093] As Figure 11 shown, the parasitic inductance of the device is reduced from 0.68 nH of the discrete spoke structure to 0.54 nH of the sleeve-shaped spoke structure (i.e., the gate lead component of this embodiment), with a reduction of 20.6%.

[0094] When the first electrode 100 is in direct contact with the chip 120 and the second electrode 110 is in direct contact with the chip 120, the first electrode 100 is located on the first side of the chip 120. The second electrode 110 is located on the second side of the chip 120. The first side and the second side of the chip 120 are oppositely arranged. The thermal resistance of the first side of the chip 120 is the first thermal resistance R th-A , and the thermal resistance of the second side of the chip 120 is the second thermal resistance R th-K ; the series thermal resistance of the first thermal resistance R th-A and the second thermal resistance R th-K and the parallel thermal resistance of the first thermal resistance R th-A and the second thermal resistance R th-K have a ratio greater than or equal to 4.3.

[0095] The first electrode 100 is used to rigidly press the first side surface of the chip 120, including the direct press when the first electrode 100 is adjacent to the chip 120, and also including the indirect press when there are other structures between the first electrode 100 and the chip 120. The second electrode 110 is used to rigidly press the second side surface of the chip 120, including the direct press when the second electrode 110 is adjacent to the chip 120, and also including the indirect press when there are other structural components between the second electrode 110 and the chip 120.

[0096] The power semiconductor device of this embodiment has a press-pack structure, specifically: each press-pack component in the power semiconductor device is independently arranged, and can maintain a good contact state and generate good electrical and thermal conductivity through pressure. However, after removing the pressure, the contact interfaces between each press-pack component or some sub-components in the press-pack component can maintain the contact state or the separated state (that is, there can be a gap between adjacent components or adjacent sub-components). In addition, when the power semiconductor device is actually applied, pressure needs to be applied to achieve the rigid press-pack (including indirect press-pack) between the first electrode 100 and / or the second electrode 110 and the chip 120. The power semiconductor device has the advantages of strong current-carrying capacity, easy series connection, and being in a short-circuit state after failure.

[0097] The rigid press-pack mentioned in the embodiments of the present disclosure is relative to the elastic press-pack. Among them, the rigid press-pack means that the compressive deformation of the press-pack component or the press-pack sub-component is mainly achieved by the elastic deformation of its own material; the elastic press-pack means that the compressive deformation of the press-pack component or the press-pack sub-component is mainly achieved by the structural deformation of a spring or a disc spring, etc. Further, the essential difference between the rigid press-pack and the elastic press-pack is also reflected in: there is an order-of-magnitude difference in the deformation amount under the same pressure. For example, the compressive deformation amount during the rigid press-pack is usually in the micron level, and the compressive deformation amount during the elastic press-pack is usually in the millimeter level.

[0098] It should be noted that defining the first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series of the two and the parallel thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-paral The ratio is the series-parallel coefficient β, then the calculation formula of the series-parallel coefficient β can be deduced as follows:

[0099] The first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series Satisfies the formula: .

[0100] The first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-paral Satisfies the formula: .

[0101] The series-parallel coefficient β satisfies: , where x is the ratio of the unilateral thermal resistance of the chip (for example, the first thermal resistance R th-A or the second thermal resistance R th-K ) to the series thermal resistance R th-series .

[0102] Such asFigure 12 As shown, when the power semiconductor device adopts a symmetric or approximately symmetric packaging structure, its upper and lower thermal resistances are, for example, the same. The value of x is approximately 0.5, and the series-parallel ratio coefficient β is 4.0. If the series-parallel ratio coefficient β is increased, then according to the relationship between the series-parallel ratio coefficient β and the first thermal resistance R th-A and the second thermal resistance R th-K , an asymmetric packaging structure (which can also be called an offset packaging structure) can be designed for the power semiconductor device. For example, in a power semiconductor device with a certain total height, it can be designed that the chip 120 deviates by a preset size to any one side of the first electrode 100 or the second electrode 110. In this way, when the total height of the power semiconductor device remains constant, the series thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-series can remain unchanged. However, as the series-parallel ratio coefficient β increases, the parallel thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-paral will decrease accordingly. And, according to the changing trend of the curve shown in Figure 12 , it can be known that during the process of the power semiconductor device changing from a symmetric or approximately symmetric packaging structure to an asymmetric packaging structure, the series-parallel ratio coefficient β gradually changes from a slow increase to a rapid increase. Based on this, it can be known that the influence of the offset degree of the power semiconductor device on its parallel thermal resistance is non-linear, that is, at the beginning, the influence is very small and can almost be ignored. However, as the offset degree increases, the parallel thermal resistance will decrease rapidly, making the technical advantages of the offset packaging structure can be significantly manifested. Therefore, in this embodiment, by setting the value range of the series-parallel ratio coefficient β between 4.3 and 20, an offset packaging structure of the power semiconductor device can be effectively designed to achieve a significant reduction in the junction-case thermal resistance of the power semiconductor device and the power device.

[0103] The value of the series-parallel ratio coefficient β can be 4.3, 4.43, 5, 5.77, 6, 7.88, 8, 10, 15, or 20.

[0104] Matching the change of the series-parallel ratio coefficient β, for the junction-case thermal resistance R thThe corresponding relationship with the series - parallel ratio coefficient β was simulated and calculated, and it was obtained that: Among them, when the power semiconductor device adopts a symmetric packaging structure, the series - parallel ratio coefficient β is 4.0, and the junction - to - case thermal resistance of the power semiconductor device at this time is 3.04 K / kW; when the series - parallel ratio coefficient β of the power semiconductor device is adjusted, when the series - parallel ratio coefficient β increases to 4.43, the junction - to - case thermal resistance of the power semiconductor device will drop to 2.33 K / kW, and the reduction rate reaches 23%. When the series - parallel ratio coefficient β increases to 5.77, the junction - to - case thermal resistance of the power semiconductor device will drop to 1.78 K / kW, and the reduction rate reaches 41%. When the series - parallel ratio coefficient β further increases to 7.88, the junction - to - case thermal resistance of the power semiconductor device will drop to 1.56 K / kW, and the reduction rate reaches 49%.

[0105] In this embodiment, the thermal resistance on the first side of the chip 120 is the first thermal resistance R th-A , and the thermal resistance on the second side of the chip 120 is the second thermal resistance R th-K , and by setting the ratio of the series thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-series to its parallel thermal resistance R th-paral to be greater than or equal to 4.3, the offset packaging of the chip 120 can be controlled, so that the parallel thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-paral when the chip 120 dissipates heat from both sides will be less than the thermal resistance of either side. Based on this technical principle, the thermal resistance of either the first side or the second side of the chip 120 can be minimized as much as possible, so as to significantly reduce the parallel thermal resistance R th-paral of the power semiconductor device, effectively reduce the junction - to - case thermal resistance of the power semiconductor device, and further effectively improve the heat dissipation efficiency and current - carrying capacity of the power semiconductor device.

[0106] In this embodiment, the ratio of the series thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-series to its parallel thermal resistance R th-paral ranges from 4.3 to 20, and can be 4.3, 4.43, 5, 5.77, 6, 7.88, 8, 10, 15 or 20.

[0107] Preferably, the ratio of the series thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-series to its parallel thermal resistance R th-paral ranges from 4.3 to 8.

[0108] In this embodiment, the thicknesses of the first electrode 100 and the second electrode 110 are different. The adjustment of the series-parallel ratio coefficient β can be achieved by adjusting the thicknesses of the first electrode 100 and the second electrode 110. Specifically, the thickness of one of the first electrode 100 and the second electrode 110 can be thinned while the thickness of the other is increased. In addition, the power semiconductor device of this embodiment can also adjust the thicknesses of the first electrode 100 and the second electrode 110 while ensuring that the total height of the power semiconductor device remains unchanged, so as to ensure the compatibility of the power semiconductor device.

[0109] A plurality of first sub-components can be provided between the first electrode 100 and the chip 120. The plurality of first sub-components are sequentially stacked in the direction from the second electrode 110 to the first electrode 100. The first sub-component can be an interlayer structure, such as a transition layer.

[0110] The first thermal resistance R th-A is the sum of the bulk thermal resistance of each first sub-component, the bulk thermal resistance of the first electrode 100, the contact thermal resistance between adjacent first sub-components, the contact thermal resistance between the first sub-component closest to the first electrode 100 and the first electrode, and the contact thermal resistance between the first sub-component closest to the chip 120 and the chip 120.

[0111] A plurality of second sub-components can be provided between the second electrode 110 and the chip 120. The plurality of second sub-components are sequentially stacked in the direction from the first electrode 100 to the second electrode 110. The second sub-component can be an interlayer structure, such as a transition layer.

[0112] The second thermal resistance R th-K is the sum of the bulk thermal resistance of each second sub-component, the bulk thermal resistance of the second electrode 110, the contact thermal resistance between adjacent second sub-components, the contact thermal resistance between the second sub-component closest to the second electrode 110 and the second electrode 110, and the contact thermal resistance between the second sub-component closest to the chip 120 and the chip 120.

[0113] Thus, the series thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-series is: the sum of the first thermal resistance R th-A and the second thermal resistance R th-K , that is, R th-series =(R th-A +R th-K ). The parallel thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-paral is: the product of the first thermal resistance R th-A and the second thermal resistance R th-K divided by the sum of the first thermal resistance R th-A and the second thermal resistance R th-KThe sum, i.e., R th-paral =(R th-A ×R th-K ) / (R th-A +R th-K )。

[0114] In other embodiments, the first crimping component has only one first sub-component, and this first sub-component is the first electrode 100. The second crimping component has only one second sub-component, and this second crimping component is the second electrode 110. Both the first electrode 100 and the second electrode 110 are directly connected to the chip 120.

[0115] Correspondingly, the first thermal resistance R th-A is: the sum of the bulk thermal resistance of the first electrode 100 and the first contact thermal resistance between the first electrode 100 and the chip 120.

[0116] The second thermal resistance R th-K is: the sum of the bulk thermal resistance of the second electrode 110 and the second contact thermal resistance between the second electrode 110 and the chip 120.

[0117] It should be noted that both the first electrode 100 and the second electrode 110 are thermally and electrically conductive composite metal materials. However, it is not limited to this. In this embodiment, both of the first electrode 100 and the second electrode 110 use metal electrodes, or one of the first electrode 100 and the second electrode 110 uses a thermally and electrically conductive composite metal material, and the other uses a metal electrode, such as a copper electrode.

[0118] It should be noted that the series thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-series and the parallel thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-para has a ratio value ranging from 7 to 20, and can be 7, 7.88, 8, 9, 10, 15, or 20.

[0119] Preferably, the ratio of the series thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-series to the parallel thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-para is 7.88.

[0120] It should be noted that the total thickness of the power semiconductor device is, for example, 35 mm. Correspondingly, the thickness of the second electrode 110 is between 0 and 5 mm, but does not include 0, and can be 3 mm, 3.5 mm, 4 mm, 4.5 mm or 5 mm. Optionally, the sum of the thicknesses of the second electrode 110 and the first electrode 100 is a target value. After thinning the thickness of the second electrode 110, the thickness of the first electrode 100 can be correspondingly increased. Correspondingly, the gate lead component interconnected with the first electrode 100 can be adjusted towards the side of the second electrode 110. For example, the spokes of the gate lead ring can be bent upwards to match and adapt to the first electrode 100 with an increased thickness. Through verification by the finite element simulation model, when the thickness of the second electrode 110 is thinned to 3 mm to 5 mm, the junction-to-case thermal resistance of this power semiconductor device will drop from 3.0 K / kW to 1.5 K / kW, and the reduction rate can reach 50%. This embodiment can greatly improve the device heat dissipation efficiency and device current-carrying capacity of the power semiconductor device.

[0121] The thickness of the first electrode 100 is less than the thickness of the second electrode 110. The thickness of the first electrode 100 is between 0 and 5 mm, but does not include 0, and can be, for example, 1 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm or 5 mm.

[0122] In other embodiments, the power semiconductor device further includes a transition layer. Among them, one of the first electrode 100 and the second electrode 110 is directly connected to the chip 120, and the other is connected to the chip 120 through the transition layer.

[0123] Matching the setting position of the transition layer, the transition layer can be used as the first sub-component or the second sub-component.

[0124] A transition layer is provided between the chip 120 and the first electrode 100. At this time, the first thermal resistance R th-A is: the sum of the bulk thermal resistance of the transition layer, the third contact thermal resistance between the transition layer and the chip 120, the bulk thermal resistance of the first electrode 100, and the fourth contact thermal resistance between the first electrode 100 and the transition layer. No transition layer is provided between the second electrode and the chip. At this time, the second thermal resistance R th-K is: the sum of the bulk thermal resistance of the second electrode 110 and the second contact thermal resistance between the second electrode 110 and the chip 120.

[0125] No transition layer is provided between the first electrode 100 and the chip 120. At this time, the first thermal resistance R th-A is: the sum of the bulk thermal resistance of the first electrode 100 and the first contact thermal resistance between the first electrode 100 and the chip 120. A transition layer is provided between the chip 120 and the second electrode 110. At this time, the second thermal resistance R th-K is: the sum of the bulk thermal resistance of the transition layer, the fifth contact thermal resistance between the transition layer and the chip 120, the bulk thermal resistance of the second electrode 110, and the sixth contact thermal resistance between the second electrode 110 and the transition layer.

[0126] Moreover, the transition layer can be used to match the thermal expansion coefficients of the chip 120 and the corresponding electrode (such as the first electrode 100 or the second electrode 110), serving as the thermal expansion coefficient transition layer between the chip 120 and the corresponding electrode (such as the first electrode 100 or the second electrode 110) to transition and balance the difference in thermal expansion coefficients between the chip 120 and the corresponding electrode (such as the first electrode 100 or the second electrode 110). The transition layer can also be a stress transition layer or a transition layer with other functions.

[0127] The transition layer includes but is not limited to a molybdenum sheet and can also be a thermally and electrically conductive composite metal sheet.

[0128] In other embodiments, the transition layer can be formed of a thermally and electrically conductive composite metal material such as aluminum diamond or copper diamond, so as to have a relatively high thermal conductivity, a relatively high electrical conductivity, and a relatively low expansion coefficient, thereby further reducing the overall thermal resistance of the power semiconductor device.

[0129] The electrode in the first electrode 100 and the second electrode 110 that is directly connected to the chip 120 is the aforementioned thermally and electrically conductive composite metal material. The first electrode 100 and the second electrode 110 can be copper electrodes, or both can adopt the aforementioned thermally and electrically conductive composite metal material, or the electrode directly connected to the chip 120 is a metal electrode while the electrode connected to the chip 120 through the transition layer adopts the aforementioned thermally and electrically conductive composite metal material.

[0130] The first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series of the first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-para The ratio of is between 5 and 20 and can be 5, 5.77, 6, 8, 10, 15, or 20.

[0131] The first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series of the first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-para The ratio of can be 5.77.

[0132] The total thickness of the power semiconductor device is, for example, 35 mm. The thickness of the second electrode 110 is between 0 and 5 mm, but does not include 0, and can be 1 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, or 5 mm. Optionally, the sum of the thicknesses of the second electrode 110 and the first electrode 100 is a target value. After thinning the thickness of the second electrode 110, the thickness of the first electrode 100 can be correspondingly increased. Accordingly, the gate assembly interconnected with the first electrode 100 can be adjusted toward the second electrode 110 side. For example, the spokes of the gate lead ring can be bent upward to match and adapt to the first electrode 100 with an increased thickness. In the embodiments of the present disclosure, through verification by a finite element simulation model, when the thickness of the second electrode 110 is thinned to 3 mm to 5 mm, the junction-to-case thermal resistance of the power semiconductor device will drop from 3.0 K / kW to 1.7 K / kW, and the reduction rate can reach 43%. The embodiments of the present disclosure can take into account the production cost of the power semiconductor device, its device heat dissipation efficiency, and its device current-carrying capacity.

[0133] In other embodiments, the thickness of the first electrode 100 is less than the thickness of the second electrode 110. The thickness of the first electrode 100 is between 0 and 5 mm, but does not include 0, and can be 1 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, or 5 mm.

[0134] In this embodiment, a first transition layer is provided between the first electrode 100 and the chip 120, and the first transition layer is electrically connected to both the first electrode 100 and the chip 120. A second transition layer is provided between the second electrode 110 and the chip 120, and the second transition layer is electrically connected to both the second electrode 110 and the chip 120.

[0135] Accordingly, the first thermal resistance R th-A is: the sum of the bulk thermal resistance of the first transition layer, the seventh contact thermal resistance between the first transition layer and the chip 120, the bulk thermal resistance of the first electrode 100, and the eighth contact thermal resistance between the first electrode 100 and the first transition layer. The second thermal resistance R th-K is: the sum of the bulk thermal resistance of the second transition layer, the ninth contact thermal resistance between the second transition layer and the chip 120, the bulk thermal resistance of the second electrode 110, and the tenth contact thermal resistance between the second electrode 110 and the second transition layer.

[0136] Both the first electrode 100 and the second electrode 110 are metal electrodes. For example, they can be copper electrodes. However, it is not limited thereto. In this embodiment, it is also allowed that the first electrode 100 and the second electrode 110 adopt the aforementioned thermally conductive and electrically conductive composite metal material.

[0137] It should be noted that the series thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-series is the same as the first thermal resistance R th-A and the second thermal resistance Rth-K The parallel thermal resistance R th-para has a ratio greater than or equal to 4.4.

[0138] In some examples, the series thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-series and the parallel thermal resistance R th-A of the first thermal resistance R th-K and the second thermal resistance R th-para has a ratio of 4.43.

[0139] The total thickness of the power semiconductor device is, for example, 35 mm. Correspondingly, the thickness of the second electrode 110 is less than that of the first electrode 100, and the thickness of the second electrode 110 is between 0 and 2.5 mm, excluding 0, and can be, for example, 1 mm, 1.5 mm, 2 mm, or 2.5 mm. Optionally, the sum of the thicknesses of the second electrode 110 and the first electrode 100 is a target value. After thinning the thickness of the second electrode 110, the thickness of the first electrode 100 can be correspondingly increased. Correspondingly, the gate assembly interconnected with the first electrode 100 can be adjusted toward the side of the second electrode 110. For example, the spokes of the gate lead ring can be bent upward to match and adapt to the first electrode 100 with an increased thickness. In the embodiments of the present disclosure, through verification by a finite element simulation model, when the thickness of the second electrode 110 is thinned to 1 mm to 2.5 mm, the junction-to-case thermal resistance of the power semiconductor device will drop from 3.0 K / kW to 2.7 K / kW, and the reduction rate can reach 20%. The embodiments of the present disclosure can effectively improve the device heat dissipation efficiency and the device current-carrying capacity based on the offset structure design of the power semiconductor device while ensuring a low production cost of the power semiconductor device.

[0140] In other embodiments, the thickness of the first electrode 100 is less than that of the second electrode 110, and the thickness of the first electrode 100 is between 0 and 2.5 mm, excluding 0, and can be, for example, 1 mm, 1.5 mm, 2 mm, or 2.5 mm.

[0141] The power semiconductor device of this embodiment has the following advantages:

[0142] (1) The parasitic inductance of the device package is significantly reduced. After changing the structure of the gate lead, the magnetic fields in the gate-cathode loop cancel each other out, significantly reducing the stray inductance and remarkably improving the device turn-off ability.

[0143] (2) By using the gate lead of this embodiment, the anode electrode can be thinned and the cathode electrode can be thickened. Such a setting can significantly reduce the junction-to-case thermal resistance of the device and improve the device current-carrying capacity.

[0144] (3) High compatibility. The device package structure can be well compatible with the existing valve string press-fitting structure without changing the existing shell sealing welding process.

[0145] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by orientation terms such as "front, rear, upper, lower, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom", etc. is usually based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description. Without contrary description, these orientation terms do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the protection scope of the present utility model; the orientation terms "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0146] For the convenience of description, spatial relative terms such as "above...", "over...", "on the upper surface of...", "upper...", etc. can be used here to describe the spatial positional relationship between a device or feature shown in the drawings and other devices or features. It should be understood that the spatial relative terms are intended to include different orientations in use or operation in addition to the orientation described in the drawings for the device. For example, if the device in the drawing is inverted, the device described as "above other devices or structures" or "over other devices or structures" will then be positioned as "below other devices or structures" or "under other devices or structures". Thus, the exemplary term "above..." can include both the orientations of "above..." and "below...". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding interpretations should be made for the spatial relative descriptions used here.

[0147] In addition, it should be noted that the use of words such as "first", "second", etc. to limit components is only for the convenience of distinguishing the corresponding components. Without otherwise stated, the above words have no special meaning. Therefore, it should not be construed as a limitation on the protection scope of the present utility model.

[0148] The above are only the preferred embodiments of the present utility model and are not used to limit the present utility model. For those skilled in the art, the present utility model can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

[0149] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by orientation words such as "front, rear, upper, lower, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom", etc. is usually based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description. Without contrary description, these orientation words do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the protection scope of the present utility model; the orientation words "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0150] For the convenience of description, spatial relative terms such as "above...", "over...", "on the upper surface of...", "upper...", etc. can be used here to describe the spatial positional relationship between a device or feature shown in the drawings and other devices or features. It should be understood that the spatial relative terms are intended to include different orientations in use or operation other than the orientation described in the drawings for the device. For example, if the device in the drawing is inverted, the device described as "above other devices or structures" or "over other devices or structures" will then be positioned as "below other devices or structures" or "under other devices or structures". Thus, the exemplary term "above..." can include both the orientations of "above..." and "below...". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the corresponding explanations for the spatial relative descriptions used here should be made.

[0151] In addition, it should be noted that the use of words such as "first", "second", etc. to limit components is only for the convenience of distinguishing the corresponding components. Without otherwise stated, the above words have no special meaning. Therefore, it should not be construed as a limitation on the protection scope of the present utility model.

[0152] The above are only the preferred embodiments of the present utility model and are not used to limit the present utility model. For those skilled in the art, the present utility model can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A gate lead-out component, characterized in that: include: A bottom lead-out structure (10), wherein a middle portion of the bottom lead-out structure (10) is provided with an avoidance hole (11); A spoke structure (20), the spoke structure (20) comprising a sleeve (21) and a plurality of connecting plates (22) arranged on the sleeve (21), the sleeve (21) being arranged at the avoidance hole (11), and the plurality of connecting plates (22) being connected to the gate of the chip (120).

2. The gate lead-out member according to claim 1, characterized in that: At least one notch (211) is provided on the sleeve (21), and the notch (211) extends along the axial direction of the sleeve (21) and penetrates the sleeve (21).

3. The gate lead-out member according to claim 1, characterized in that: A plurality of connecting plates (22) are arranged at one end of the sleeve (21) away from the bottom lead-out structure (10), and each connecting plate (22) extends toward the interior of the sleeve (21).

4. The gate lead-out member according to claim 1, characterized in that: The plurality of connecting plates (22) are evenly arranged in the circumferential direction of the avoidance hole (11).

5. The gate lead-out member according to claim 1, characterized in that: The thickness of the bottom lead-out structure (10), the wall thickness of the sleeve (21), and the thickness of the connecting plate (22) are the same.

6. The gate lead-out member according to claim 1, characterized in that: The wall thickness of the sleeve (21) is between 0.3 mm and 1.5 mm.

7. The gate lead-out member according to claim 1, characterized in that: The distance between the two ends of the sleeve (21) is between 3 mm and 25 mm.

8. The gate lead-out member according to any one of claims 1 to 7, characterized in that: The gate lead-out member is an integrally formed structure.

9. A power semiconductor device, characterized in that: include: A first electrode (100) and a second electrode (110); a chip (120), arranged between the first electrode (100) and the second electrode (110), and electrically connected to both the first electrode (100) and the second electrode (110); A gate lead-out member, wherein the gate lead-out member is the gate lead-out member according to any one of claims 1 to 8, wherein the spoke structure (20) of the gate lead-out member is electrically connected to the gate of the chip (120), and the gate lead-out member is arranged around the periphery of the first electrode (100).

10. The power semiconductor device according to claim 9, characterized in that: The power semiconductor device further comprises a gate insulating member (130), wherein the gate insulating member (130) is arranged on the first electrode (100), and the gate insulating member (130) is arranged between the first electrode (100) and the gate lead-out member.

11. The power semiconductor device according to claim 10, characterized in that: The first electrode (100) comprises a support platform (101) and a connection platform (102); the side of the connection platform (102) is located in the vertical space where the side of the support platform (101) is located; an accommodation portion is formed between the top of the support platform (101) and the side of the connection platform (102); the gate insulating member (130) is arranged at the accommodation portion; and the gate lead-out member is arranged at the periphery of the gate insulating member (130).

12. The power semiconductor device according to claim 10, characterized in that: The power semiconductor device further comprises an elastic component (140), wherein the elastic component (140) is arranged between the gate insulating component (130) and the spoke structure (20).

13. The power semiconductor device according to claim 11, characterized in that: In the radial direction of the avoidance hole (11), the value of the minimum distance (L) between a side of the spoke structure (20) close to the support platform (101) and a side portion of the support platform (101) is between 0.5 mm and 6 mm.

14. The power semiconductor device according to any one of claims 10 to 13, characterized in that: The thickness of the first electrode (100) is greater than the thickness of the second electrode (110).

15. The power semiconductor device according to claim 14, characterized in that: The ratio of the thickness of the second electrode (110) to the thickness of the first electrode (100) is greater than 0 and less than or equal to 0.6.

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