Integrated longitudinal high-voltage device
By using longitudinal high-voltage devices with deep groove gate structure and P-type deep well zone preparation in high-voltage integrated circuits, the problem of increasing area under high voltage is solved, the device withstand voltage value and integration is improved, and the development of high-voltage BCD process is promoted.
Patent Information
- Application Number
- CN202421905887.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-07
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-08-07
AI Technical Summary
The area of traditional LDMOS devices increases under high voltage, resulting in a decrease in cost-effectiveness and limiting the development of high-voltage BCD processes.
A longitudinal high-voltage device with a deep groove gate structure and a P-type deep well region is set in the N-type epitaxial layer to prepare CMOS devices, thereby realizing the integration of the power output tube and CMOS devices.
The withstand voltage value of high-voltage devices is improved, the integration of large-area power output tubes and CMOS devices is achieved, and the development of high-voltage BCD processes is promoted.
Smart Images
Figure CN222916506U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present utility model relate to the technical field of integrated circuit manufacturing, and particularly to an integrable vertical high-voltage device. Background Art
[0002] In the field of high-voltage integrated circuits, it is often necessary to integrate a large-area power output transistor and ordinary complementary metal oxide semiconductor (CMOS) devices. In the traditional BCD (Bipolar-CMOS-DMOS) process, the large-area power transistor is completed by using a planar laterally diffused metal oxide semiconductor (LDMOS) device. However, for the LDMOS device, especially as the voltage increases, the area of this device will increase sharply, resulting in a sharp decline in the cost performance of the device under high voltage. At the same time, the poor reliability of the high-voltage LDMOS has also been restricting the continuous development of the high-voltage BCD process. Summary of the Utility Model
[0003] The present utility model provides an integrable vertical high-voltage device to improve the reliability of high-voltage LDMOS and realize the integration of a large-area power output transistor and CMOS devices.
[0004] The embodiments of the present utility model provide an integrable vertical high-voltage device, including:
[0005] A drain metal layer;
[0006] An N-type buried layer, located above the drain metal layer;
[0007] An N-type epitaxial layer, located above the N-type buried layer;
[0008] A deep trench gate high-voltage device and a CMOS device, located above the N-type epitaxial layer and arranged horizontally; the N-type epitaxial layer includes a P-type deep well region, and the CMOS device is located above the P-type deep well region.
[0009] Optionally, the CMOS device includes a grounding region, an NMOS region, a PMOS region, and a power supply region. The grounding region, the NMOS region, the PMOS region, and the power supply region are arranged in sequence horizontally and away from the deep trench high-voltage device. First shallow trench isolation regions are provided between the grounding region, the NMOS region, the PMOS region, and the power supply region in pairs.
[0010] Optionally, the grounding region includes a P-type heavily doped region, and the P-type heavily doped region is grounded through a contact hole;
[0011] The power supply region includes an N-type heavily doped region, and the N-type heavily doped region is connected to the power supply through a contact hole;
[0012] The NMOS region includes a P-well and two N-type heavily doped regions located in the P-well, and there is a gap between the two N-type heavily doped regions; a first gate oxide layer and a first polysilicon gate are sequentially arranged above the gap between the two N-type heavily doped regions; the two N-type heavily doped regions are respectively connected to the source metal layer and the drain metal layer through contact holes; the first polysilicon gate is connected to the gate metal layer through a contact hole;
[0013] The PMOS region includes an N-well and two P-type heavily doped regions located in the N-well, and there is a gap between the two P-type heavily doped regions; a second gate oxide layer and a second polysilicon gate are sequentially arranged above the gap between the two P-type heavily doped regions; the two P-type heavily doped regions are respectively connected to the source metal layer and the drain metal layer through contact holes; the second polysilicon gate is connected to the gate metal layer through a contact hole;
[0014] The depths of the P-well and the N-well are both less than the depth of the P-type deep well region, the depth of the first shallow trench isolation region is less than the depths of the P-well and the N-well, and the depths of the P-type heavily doped region and the N-type heavily doped region are less than the depth of the first shallow trench isolation region.
[0015] Optionally, a second shallow trench isolation region is provided between the deep trench gate high-voltage device and the CMOS device.
[0016] Optionally, the deep trench gate high-voltage device includes a gate region, a source region, and a body region; the body region and the gate region are arranged horizontally, and the source region is located above the body region and adjacent to the gate region;
[0017] The gate region includes a gate deep trench and a third gate oxide layer and a third polysilicon gate located in the gate deep trench, and the third gate oxide layer wraps the third polysilicon gate; the depth of the gate deep trench is greater than the depth of the body region.
[0018] Optionally, the source region includes an N-type heavily doped region, and the N-type heavily doped region in the source region is connected to the source metal layer through a contact hole.
[0019] Optionally, the body region includes a body pole deep trench and a P-type heavily doped region located in the body pole deep trench, and the P-type heavily doped region in the body pole deep trench is connected to the body pole metal layer through a contact hole; the depth of the body pole deep trench is less than the depth of the body region.
[0020] Optionally, the upper surface of the P-type heavily doped region in the body region is lower than the upper surface of the N-type heavily doped region in the source region.
[0021] Optionally, the depth range of the body region is 0.3 - 3 um, and / or, the depth difference between the upper surface of the P-type heavily doped region in the body region and the upper surface of the N-type heavily doped region in the source region ranges from 0.3 - 3 um.
[0022] Optionally, the depth range of the deep trench of the gate is 0.3 - 3 um, and / or, the thickness range of the third gate oxide layer is 5 nm - 100 nm.
[0023] The technical solution of the embodiment of the present invention includes, in an integrable vertical high-voltage device: a drain metal layer; an N-type buried layer located above the drain metal layer; an N-type epitaxial layer located above the N-type buried layer; a deep trench gate high-voltage device and a CMOS device located above the N-type epitaxial layer and arranged horizontally; the N-type epitaxial layer includes a P-type deep well region, and the CMOS device is located above the P-type deep well region. The embodiment of the present invention solves the problem that it is impossible to balance both area and breakdown voltage when integrating a power output transistor and a common CMOS device. By setting the power output transistor as a vertical high-voltage device with a deep trench gate structure and using a P-type deep well to fabricate the CMOS device, the power output transistor and the CMOS device are integrated. When integrating the vertical high-voltage device and the CMOS device, the breakdown voltage of the high-voltage device in the integrated device is increased, which contributes to the development of the high-voltage BCD process. Description of the Drawings
[0024] Figure 1 is a schematic structural diagram of an integrable vertical high-voltage device provided by an embodiment of the present invention;
[0025] In the figure:
[0026] 10 - Contact hole, 100 - Drain metal layer, 200 - N-type buried layer, 300 - N-type epitaxial layer, 400 - Deep trench gate high-voltage device, 410 - Gate region, 411 - Deep trench of the gate, 412 - Third gate oxide layer, 413 - Third polysilicon gate, 420 - Source region, 430 - Body region, 431 - Deep trench of the body electrode, 500 - CMOS device, 510 - Ground region, 520 - NMOS region, 521 - First polysilicon gate, 530 - PMOS region, 531 - Second polysilicon gate, 540 - Power supply region, 551 - First shallow trench isolation region, 552 - Second shallow trench isolation region. Detailed Embodiments
[0027] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that, for the sake of description, only parts related to the present invention are shown in the drawings, rather than all the structures.
[0028] The terms used in the embodiments of the present utility model are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. It should be noted that the orientation terms such as "upper", "lower", "left", and "right" described in the embodiments of the present utility model are described from the angles shown in the drawings and should not be construed as limiting the embodiments of the present utility model. In addition, in the context, it should also be understood that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also be indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only used for descriptive purposes and do not indicate any order, quantity, or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0029] The term "comprising" and its variations used in the present utility model are open-ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment".
[0030] It should be noted that the concepts such as "first" and "second" mentioned in the present utility model are only used to distinguish the corresponding contents and are not used to limit the order or the interdependent relationship.
[0031] It should be noted that the modifications of "one" and "multiple" mentioned in the present utility model are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly specified in the context, it should be understood as "one or more".
[0032] Figure 1 is a schematic structural diagram of an integrable vertical high-voltage device provided by an embodiment of the present utility model. Refer to Figure 1 , the integrable vertical high-voltage device includes: a drain metal layer 100; an N-type buried layer 200, located above the drain metal layer 100; an N-type epitaxial layer 300, located above the N-type buried layer 200; a deep trench gate high-voltage device 400 and a complementary metal oxide semiconductor (CMOS) device 500, located above the N-type epitaxial layer 300 and arranged in the horizontal direction; the N-type epitaxial layer 300 includes a P-type deep well region DPW, and the CMOS device 500 is located above the P-type deep well region DPW.
[0033] First, the integrable vertical high-voltage device represents the integration of the deep trench gate high-voltage device 400 and the CMOS device 500. Here, the horizontal direction refers to the direction parallel to the surface of the semiconductor substrate 100. The deep trench gate high-voltage device 400 and the CMOS device 500 are horizontally arranged above the N-type epitaxial layer 300, indicating that the two devices are integrated in a planar manner. Among them, the vertical high-voltage device more refers to the deep trench gate high-voltage device 400 being a vertical device, which is longitudinally located on both sides of the N-type buried layer 200 and the N-type epitaxial layer 300 with respect to the drain metal layer 100, thus forming a longitudinal conductive channel. The CMOS device 500 is a planar device structure. In this embodiment, to integrate the CMOS device 500 with the longitudinal deep trench gate high-voltage device 400, a P-type deep well region DPW is set in the N-type epitaxial layer 300, and then the planar CMOS device 500 is fabricated on the P-type deep well region DPW.
[0034] In the above technical solution, the integrable vertical high-voltage device includes: a drain metal layer; an N-type buried layer located above the drain metal layer; an N-type epitaxial layer located above the N-type buried layer; a deep trench gate high-voltage device and a CMOS device located above the N-type epitaxial layer and arranged in the horizontal direction; the N-type epitaxial layer includes a P-type deep well region, and the CMOS device is located above the P-type deep well region. The embodiment of the present invention solves the problem that it is impossible to balance both area and breakdown voltage when integrating a power output transistor and a common CMOS device. By setting the power output transistor as a vertical high-voltage device with a deep trench gate structure and using a P-type deep well to fabricate the CMOS device, the power output transistor and the CMOS device are integrated. When integrating the vertical high-voltage device and the CMOS device, the breakdown voltage of the high-voltage device in the integrated device is increased, which contributes to the development of the high-voltage BCD process.
[0035] In a specific embodiment, continue to refer to Figure 1 , in this vertical high-voltage device, the CMOS device 500 includes a grounding region 510, an NMOS region 520, a PMOS region 530, and a power supply region 540. The grounding region 510, the NMOS region 520, the PMOS region 530, and the power supply region 540 are arranged in sequence along the horizontal direction and away from the deep trench high-voltage device 400. First shallow trench isolation regions 551 are provided between the grounding region 510, the NMOS region 520, the PMOS region 530, and the power supply region 540 in pairs.
[0036] Among them, first shallow trench isolation regions 551 are provided between the grounding region 510, the NMOS region 520, the PMOS region 530, and the power supply region 540 in pairs, which can effectively isolate the electrical connection between the gate and the source or the drain using shallow trenches, achieve electrical insulation, and avoid short-circuit and leakage problems.
[0037] In a specific embodiment, continue to refer to Figure 1, the grounding region 510 includes a heavily doped P-type region P+, and the heavily doped P-type region P+ is grounded through a contact hole 10 (not shown in the figure); the power supply region 540 includes a heavily doped N-type region N+, and the heavily doped N-type region N+ is connected to a power supply through a contact hole 10 (not shown in the figure).
[0038] The NMOS region 520 includes a P-well PW and two heavily doped N-type regions N+ located in the P-well PW, with a gap between the two heavily doped N-type regions N+; a first gate oxide layer (not shown in the figure) and a first polysilicon gate 521 are sequentially disposed above the gap between the two heavily doped N-type regions N+; the two heavily doped N-type regions N+ are respectively connected to a source metal layer (not shown in the figure) and a drain metal layer (not shown in the figure) through contact holes 10; the first polysilicon gate 521 is connected to a gate metal layer (not shown in the figure) through a contact hole.
[0039] The PMOS region includes an N-well NW and two heavily doped P-type regions P+ located in the N-well NW, with a gap between the two heavily doped P-type regions P+; a second gate oxide layer (not shown in the figure) and a second polysilicon gate 531 are sequentially disposed above the gap between the two heavily doped P-type regions; the two heavily doped P-type regions P+ are respectively connected to a source metal layer (not shown in the figure) and a drain metal layer (not shown in the figure) through contact holes 10; the second polysilicon gate 531 is connected to a gate metal layer (not shown in the figure) through a contact hole.
[0040] The depths D1 of the P-well PW and the N-well NW are both less than the depth D2 of the P-type deep well region DPW, the depth D3 of the first shallow trench isolation region 551 is less than the depths D1 of the P-well PW and the N-well NW, and the depths D4 of the heavily doped P-type region P+ and the heavily doped N-type region N+ are less than the depth D3 of the first shallow trench isolation region 551.
[0041] Among them, the depths D1 of the P-well PW and the N-well NW are both less than the depth D2 of the P-type deep well region DPW. Essentially, after the P-type deep well region DPW is formed by implantation in the N-type epitaxial layer 300, the NMOS transistor and the PMOS transistor are then fabricated in the P-type deep well region DPW. It can be seen that the well region depths in the NMOS transistor and the PMOS transistor are necessarily less than the depth of the P-type deep well DPW.
[0042] In a specific embodiment, continue to refer to Figure 1 , a second shallow trench isolation region 552 is provided between the deep trench gate high-voltage device 400 and the CMOS device 500.
[0043] As mentioned above, providing the second shallow trench isolation region 552 between the deep trench gate high-voltage device 400 and the CMOS device 500 can effectively isolate the electrical connection between the high-voltage device and the CMOS device by using the shallow trench, achieve electrical insulation, and avoid short-circuit and leakage problems.
[0044] In a specific embodiment, continue to refer toFigure 1 The deep trench gate high voltage device 400 includes a gate region 410, a source region 420 and a body region 430; the body region 430 and the gate region 410 are arranged in a horizontal direction, the source region 420 is located above the body region 430 and is adjacent to the gate region 410; the gate region 410 includes a gate deep trench 411 and a third gate oxide layer 412 and a third polysilicon gate 413 located in the gate deep trench 411, and the third gate oxide layer 412 wraps the third polysilicon gate 413; the depth D5 of the gate deep trench 411 is greater than the depth D6 of the body region 430.
[0045] Among them, the gate region 410 includes a gate deep groove 411 and a third gate oxide layer 412 and a third polysilicon gate 413 located in the gate deep groove 411, which constitute a deep groove gate structure. By utilizing the deep groove gate structure, the on-resistance of the high-voltage DMOS device can be significantly reduced, while significantly increasing the withstand voltage of the device.
[0046] In a specific embodiment, continue to refer to Figure 1 The source region 420 includes an N-type heavily doped region N+, and the N-type heavily doped region N+ in the source region 420 is connected to a source metal layer (not shown) through a contact hole 10 .
[0047] In a specific embodiment, continue to refer to Figure 1 The body region 430 includes a body deep trench 431 and a P-type heavily doped region P+ located in the body deep trench 431. The P-type heavily doped region P+ in the body deep trench 431 is connected to the body metal layer (not shown in the figure) through a contact hole 10. The depth D7 of the body deep trench 431 is less than the depth D6 of the body region 430.
[0048] In this embodiment, the depth D7 of the body deep trench 431 is less than the depth D6 of the body region 430. In essence, the P+ deep hole contact window is formed by using the P-type heavily doped region P+ to form a larger contact area with the body region 430. Therefore, when the high-voltage device is used in a space scene, the body region 430 absorbs a large number of holes generated by cosmic rays, and the holes can be guided out as soon as possible, thereby reducing the generation of large BJT currents and improving the life of the device. It should also be added that the bottom of the P+ deep hole contact window formed by the P-type heavily doped region P+ can form an ohmic contact by p+ injection or preparation of a silicide film layer to ensure good conductivity.
[0049] In a specific embodiment, continue to refer to Figure 1 , an upper surface of the P-type heavily doped region P+ in the body region 430 is lower than an upper surface of the N-type heavily doped region N+ in the source region 420 .
[0050] In this embodiment, the upper surface of the P-type heavily doped region P+ in the body region 430 is set lower than the upper surface of the N-type heavily doped region N+ in the source region 420, so that the longitudinal height of the P-type heavily doped region P+ in the body region 430 can be reduced, thereby enabling the extra-generated holes to be exported as soon as possible, which helps to reduce the large current of the BJT.
[0051] In a specific embodiment, with continued reference to Figure 1 , the depth D6 of the body region 430 ranges from 0.3 to 3 um, and / or, the depth difference ΔD between the upper surface of the P-type heavily doped region P+ in the body region 430 and the upper surface of the N-type heavily doped region N+ in the source region 420 ranges from 0.3 to 3 um.
[0052] In a specific embodiment, with continued reference to Figure 1 , the depth D5 of the gate deep trench 411 ranges from 0.3 to 3 um, and / or, the thickness D8 of the third gate oxide layer 412 ranges from 20 nm to 1000 nm.
[0053] Note that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, combinations with each other, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. An integrable vertical high voltage device, characterized in that: include: Drain metal layer; An N-type buried layer, located above the drain metal layer; An N-type epitaxial layer, located above the N-type buried layer; The deep trench gate high voltage device and the CMOS device are located above the N-type epitaxial layer and arranged in a horizontal direction; the N-type epitaxial layer includes a P-type deep well region, and the CMOS device is located above the P-type deep well region.
2. The vertical high voltage device according to claim 1, characterized in that: The CMOS device includes a grounding region, an NMOS region, a PMOS region and a power region, wherein the grounding region, the NMOS region, the PMOS region and the power region are arranged in sequence horizontally and away from the deep trench high-voltage device, and a first shallow trench isolation region is arranged between each of the grounding region, the NMOS region, the PMOS region and the power region.
3. The vertical high voltage device according to claim 2, characterized in that: The grounding region includes a P-type heavily doped region, and the P-type heavily doped region is grounded through a contact hole; The power supply area includes an N-type heavily doped area, and the N-type heavily doped area is connected to the power supply through a contact hole; The NMOS region includes a P well and two N-type heavily doped regions in the P well, wherein a gap exists between the two N-type heavily doped regions; a first gate oxide layer and a first polysilicon gate are sequentially arranged above the gap between the two N-type heavily doped regions; the two N-type heavily doped regions are respectively connected to a source metal layer and a drain metal layer through contact holes; and the first polysilicon gate is connected to a gate metal layer through a contact hole; The PMOS region includes an N-well and two P-type heavily doped regions located in the N-well, wherein a gap exists between the two P-type heavily doped regions; a second gate oxide layer and a second polysilicon gate are sequentially arranged above the gap between the two P-type heavily doped regions; the two P-type heavily doped regions are respectively connected to a source metal layer and a drain metal layer through contact holes; and the second polysilicon gate is connected to a gate metal layer through a contact hole; The depths of the P-well and the N-well are both smaller than the depth of the P-type deep well region, the depth of the first shallow trench isolation region is smaller than the depths of the P-well and the N-well, and the depths of the P-type heavily doped region and the N-type heavily doped region are smaller than the depth of the first shallow trench isolation region.
4. The vertical high voltage device according to claim 1, characterized in that: A second shallow trench isolation region is arranged between the deep trench gate high voltage device and the CMOS device.
5. The vertical high voltage device according to claim 4, characterized in that: The deep trench gate high voltage device comprises a gate region, a source region and a body region; the body region and the gate region are arranged in a horizontal direction, and the source region is located above the body region and adjacent to the gate region; The gate region includes a gate deep trench and a third gate oxide layer and a third polysilicon gate located in the gate deep trench, wherein the third gate oxide layer wraps the third polysilicon gate; the depth of the gate deep trench is greater than the depth of the body region.
6. The vertical high voltage device according to claim 5, characterized in that: The source region includes an N-type heavily doped region, and the N-type heavily doped region in the source region is connected to a source metal layer through a contact hole.
7. The vertical high voltage device according to claim 6, characterized in that: The body region includes a body deep trench and a P-type heavily doped region located in the body deep trench, wherein the P-type heavily doped region in the body deep trench is connected to a body metal layer via a contact hole; and the depth of the body deep trench is less than the depth of the body region.
8. The vertical high voltage device according to claim 7, characterized in that: An upper surface of the P-type heavily doped region in the body region is lower than an upper surface of the N-type heavily doped region in the source region.
9. The vertical high voltage device according to claim 8, characterized in that: The depth of the body region is in the range of 0.3 to 3 um, and / or the depth difference between the upper surface of the P-type heavily doped region in the body region and the upper surface of the N-type heavily doped region in the source region is in the range of 0.3 to 3 um.
10. The vertical high voltage device according to claim 5, characterized in that: The depth of the gate deep trench is in the range of 0.3 to 3 um, and / or the thickness of the third gate oxide layer is in the range of 5 nm to 100 nm.