Power semiconductor device

Abstract

The utility model provides a power semiconductor device which comprises a plurality of device units, and each device unit comprises a substrate with a first surface; the gate poles are located on the first surface at intervals; at least part of the cathode emitting electrode is located in the substrate; the cathode is located on the side, away from the substrate, of the cathode emitter, and the orthographic projection of the cathode on the first surface covers the orthographic projection of at least part of the gate on the first surface. The area of the cathode is expanded, so that the gate pole and the cathode are overlapped in orthographic projection in the longitudinal direction, and under the condition that the device bears the same current, the cathode with a larger area can disperse the current more, so that the current density of the cathode can be reduced, the capability of the device for bearing instant large current is improved, and the surge resistance of the device is further improved. And the current density is reduced, so that the distribution of the current in the cathode is more uniform and is not concentrated at one point, and the risk of local overheating of the cathode can be further reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power semiconductor device. Background Art

[0002] Integrated Gate-Commutated Thyristor (IGCT) has the characteristics of high blocking voltage, strong current capacity, and full control. It has broad application potential in the fields of converters, rectifiers, inverters, and current fast switching. Compared with thyristors (Silicon Controlled Rectifier, SCR), IGCT devices achieve fast turn-on and turn-off through small-sized, comb-shaped cathode islands and large-area gate designs. However, the small-sized, comb-shaped cathode emitter structure design reduces the area of ​​the cathode metal on the entire chip, resulting in a reduction in the heat dissipation area on the cathode side and an increase in thermal resistance, which affects the surge capability of the device. As the current density of the device continues to increase, this contradiction becomes more prominent. On the other hand, as the comb size continues to decrease, the difficulty of process implementation is also increasing. Utility Model Content

[0003] The main purpose of the present application is to provide a power semiconductor device to solve the problem of poor surge resistance of power semiconductor devices in the prior art.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a power semiconductor device is provided, comprising a plurality of device units, wherein the device units include: a substrate having a first surface; a plurality of gates spaced apart on the first surface; a cathode emitter, at least a portion of the cathode emitter being located in the substrate; a cathode being located on a side of the cathode emitter facing away from the substrate, the orthographic projection of the cathode on the first surface covering at least a portion of the orthographic projection of the gate on the first surface.

[0005] Optionally, the cathodes of any two of the device units are connected to each other.

[0006] Optionally, there is a gap between the cathodes of any two of the device units.

[0007] Optionally, the substrate includes: a first doped layer having a first doping type; a second doped layer located on one side of the first doped layer, the second doped layer having a second doping type different from the first doping type; a third doped layer located on the side of the second doped layer away from the first doped layer, the third doped layer having the first doping type; a fourth doped layer located on the side of the third doped layer away from the second doped layer, a surface of the fourth doped layer away from the first doped layer being the first surface, and the fourth doped layer having the first doping type.

[0008] Optionally, the device unit further includes an anode located on the side of the substrate away from the cathode.

[0009] Optionally, a part of the cathode emitter is located in the substrate, and another part of the cathode emitter protrudes from the first surface.

[0010] Optionally, a surface of the cathode emitter away from the substrate is located in the first surface.

[0011] Optionally, the device unit further includes: a first isolation layer, at least a part of the first isolation layer being located between the cathode and the gate, and the first isolation layer covering the first surface and a part of the cathode emitter.

[0012] Optionally, the device unit further includes: a plurality of second isolation layers located on the side of the first isolation layer close to the substrate, each second isolation layer being in contact with the cathode and the gate respectively, and covering the first surface and a part of the cathode emitter.

[0013] Optionally, the power semiconductor device further includes an alignment region and a gate lead-out portion. Among them, the device units are arranged around the alignment region with the alignment region as the center. Among the plurality of gates, there are a plurality of target gates. The distance between the gates other than the target gates and the alignment region is less than the distance between the target gates and the alignment region. The gate lead-out portion is located on the target gates and corresponds to the target gates one by one.

[0014] Applying the technical solution of the present application, the power semiconductor device proposed in the present application includes a plurality of device units. Each device unit includes a substrate, a gate, and a cathode. The substrate has a first surface, and a plurality of gates are spaced on the first surface. Part of the cathode is located on the side of the gate away from the substrate, and the positive projection of the cathode on the first surface covers at least part of the positive projection of the gate on the first surface. In the prior art, the cathode and the gate do not overlap in the longitudinal direction. In the present application, by expanding the area of the cathode, the gate and the cathode overlap in the longitudinal direction in terms of positive projection. When the device bears the same current, the cathode with a larger area can disperse the current more widely, thereby reducing the current density of the cathode, improving the ability of the device to withstand instantaneous large currents, and further enhancing the surge resistance of the device. The reduction in current density can also make the distribution of current in the cathode more uniform and not concentrated at a single point, thereby reducing the risk of local overheating of the cathode. The power semiconductor device of the present application solves the problem of poor surge resistance of power semiconductor devices in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings forming a part of this application are used to provide a further understanding of the present application. The schematic embodiments and descriptions thereof are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0016] Figure 1 FIG. 9 shows a top view structural schematic diagram of an embodiment of the first power semiconductor device proposed according to the present application;

[0017] Figure 2 FIG. 13 shows a cross-sectional structural schematic diagram of an embodiment of the first power semiconductor device proposed according to the present application;

[0018] Figure 3 FIG. 17 shows a cross-sectional structural schematic diagram of an embodiment of the second power semiconductor device proposed according to the present application;

[0019] Figure 4 FIG. 21 shows a cross-sectional structural schematic diagram of an embodiment of the third power semiconductor device proposed according to the present application;

[0020] Figure 5 FIG. 25 shows a top view structural schematic diagram of an embodiment of the second power semiconductor device proposed according to the present application;

[0021] Figure 6 FIG. 29 shows a cross-sectional structural schematic diagram of an embodiment of the fourth power semiconductor device proposed according to the present application;

[0022] Figure 7 FIG. 33 shows a cross-sectional structural schematic diagram of an embodiment of the fifth power semiconductor device proposed according to the present application.

[0023] Among them, the above-mentioned drawings include the following reference numerals:

[0024] 1. Alignment region; 20. Device unit; 30. Substrate; 31. First doped layer; 32. Second doped layer; 33. Third doped layer; 34. Fourth doped layer; 40. Gate; 41. Target gate; 50. Cathode emitter; 60. Cathode; 61. Large-sized cathode; 70. Anode; 80. First isolation layer; 90. Second isolation layer; 100. Gate lead-out part; 110. Terminal region. Detailed implementation manners

[0025] It should be noted that the following detailed description is exemplary and is intended to provide further illustration of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.

[0026] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0027] It should be noted that the terms "first", "second", etc. in the description and claims of the present utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present utility model described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or device units does not necessarily have to be limited to those steps or device units clearly listed, but may include other steps or device units not clearly listed or inherent to these processes, methods, products, or devices.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or there can also be an intermediate element. Moreover, in the description and claims of the specification, when an element is described as being "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0029] As introduced in the background technology, the integrated gate-commutated thyristor (IGCT) in the prior art has a small-sized, comb-shaped cathode emitter structural design, which reduces the area of ​​the cathode metal on the entire chip, resulting in a reduction in the heat dissipation area on the cathode side and an increase in thermal resistance, which affects the surge capability of the device. As the current density of the device continues to increase, this contradiction becomes more prominent. On the other hand, as the size of the comb continues to decrease, the difficulty of process implementation also increases. In order to solve the problem of poor surge resistance of power semiconductor devices, an embodiment of the present application provides a power semiconductor device.

[0030] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0031] According to one aspect of the present application, a power semiconductor device is provided, such as Figures 1 to 4 As shown, it includes a plurality of device units 20, and the device unit 20 includes: a substrate 30 having a first surface; a plurality of gates 40, which are spaced apart and located on the first surface; a cathode emitter 50, at least a portion of the cathode emitter 50 is located in the substrate 30; a cathode 60, which is located on the side of the cathode emitter 50 away from the substrate 30, and the orthographic projection of a portion of the cathode 60 on the first surface covers the orthographic projection of at least a portion of the gate 40 on the first surface.

[0032] Compared with the prior art in which the cathode and the gate do not overlap in the longitudinal direction, the present application increases the area of ​​the cathode by making the gate and the cathode overlap in the longitudinal direction, so that when the power semiconductor device is subjected to a large current, the current can be quickly dispersed, more current can be conducted, the current density can be reduced, the ability of the device to withstand instantaneous large currents can be improved, and the device's surge resistance can be further improved. Increasing the cathode area can also improve the cathode's heat dissipation capacity, and reducing the current density can make the current distribution in the cathode more uniform and not concentrated at one point, thereby reducing the thermal resistance of the power semiconductor device and the risk of local overheating of the cathode. Increasing the cathode area can also increase the window of the power semiconductor device manufacturing process and reduce the difficulty of manufacturing power semiconductor devices.

[0033] In some embodiments, Figure 1As shown, the power semiconductor device further includes an alignment region 1, and a plurality of rings formed by a plurality of interconnected device units 20 are formed around the alignment region 1. The alignment region 1 is used for alignment during the test of the power semiconductor device, improving the accuracy of the test of the power semiconductor device. The test is to detect whether there are damaged device units 20 in the prepared power semiconductor device, such as adhesion of the cathodes between adjacent device units 20. If there is a situation where the device unit 20 is damaged, the cathode of the damaged device unit 20 needs to be removed to ensure the normal use of other device units 20 and make the function of the power semiconductor device intact.

[0034] In some alternative embodiments, such as Figure 1 As shown, the cathodes between any two device units 20 are interconnected. The cathode of each device unit 20 is made to be the largest, so that all the cathodes in the power semiconductor device are connected together. A continuous large-sized cathode 61 is formed in the power semiconductor device, which can further increase the heat dissipation area of the cathode. When the power semiconductor device bears the same current, the current can be further quickly dispersed, conduct more current, reduce the current density, and improve the heat dissipation capacity and surge resistance of the device.

[0035] In some embodiments, the doping type of the cathode emitter is N-type, and different positions of the cathode emitter indicate different types of power semiconductor devices. Such as Figure 2 As shown, the surface of the side of the cathode emitter 50 facing away from the substrate 30 is located in the first surface, and this is a planar power semiconductor device. Such as Figure 3 As shown, a part of the cathode emitter 50 is located in the substrate 30, and another part of the cathode emitter 50 protrudes from the first surface to form a mesa-type power semiconductor device. The technical solutions in this application can be applied to planar and mesa-type power semiconductor devices, with a wide range of applications.

[0036] In some embodiments, the material of the above-mentioned substrate can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide, and aluminum gallium nitride. The material of the above-mentioned cathode can be any one of aluminum, copper, tungsten, and silver, or an alloy of the above-mentioned metals. The material of the above-mentioned gate can be any one of aluminum, titanium, tungsten, and silver, or an alloy of the above-mentioned metals.

[0037] In some alternative embodiments, such as Figures 2 to 4 As shown, the device unit further includes an anode 70, and the anode 70 is located on the side of the substrate 30 facing away from the cathode 60. The anode 70 is usually the main input or output terminal of the current. When the device is in the forward conduction state, the current mainly flows from the anode 70 to the cathode 60. The material of the anode 70 can be selected from any one or more of aluminum, copper, and silver, and can also be a multi-layer metal formed by multiple of titanium, aluminum, copper, nickel, and gold.

[0038] In some alternative embodiments, such as Figure 3 and Figure 4 shown, the substrate 30 includes: a first doped layer 31 having a first doping type; a second doped layer 32 located on one side of the first doped layer 31, the second doped layer 32 having a second doping type, the first doping type and the second doping type being different; a third doped layer 33 located on the side of the second doped layer 32 facing away from the first doped layer 31, the third doped layer 33 having the first doping type; a fourth doped layer 34 located on the side of the third doped layer 33 facing away from the second doped layer 32, the surface of the side of the fourth doped layer 34 facing away from the first doped layer 31 being a first surface, and the fourth doped layer 34 having the first doping type. A PNPN structure is formed between the first doped layer 31, the second doped layer 32, the third doped layer 33, the fourth doped layer 34 and the cathode emitter 50. The working principle of the power semiconductor device is as follows:

[0039] When a positive voltage is applied across the device, i.e., the anode is at a positive voltage relative to the cathode, the PN junction between the first doped layer and the second doped layer is forward-biased. This allows holes in the first doped layer to move towards the second doped layer. When a positive voltage is applied to the gate relative to the cathode, the PN junction between the fourth doped layer and the cathode emitter is also forward-biased. The application of the gate voltage causes electrons from the cathode emitter to be injected into the fourth doped layer and the third doped layer. Since electrons are minority carriers in P-type materials, their injection increases the conductivity. Therefore, the injected electrons reduce the effective resistance of the fourth doped layer and the third doped layer. Once the resistance in the fourth doped layer and the third doped layer is reduced to a certain extent, current can flow sequentially through the conductive channels of the anode, the first doped layer, the second doped layer, the third doped layer, the fourth doped layer and the cathode emitter, and finally reach the cathode to turn on the device.

[0040] When the voltage applied to the gate is removed or becomes negative, the device enters the off state. The specific process is as follows: The PN junction between the fourth doped layer and the cathode emitter returns to reverse bias, prohibiting the injection of electrons from the gate. Since there is no electron injection into the fourth doped layer and the third doped layer, their resistance returns to a higher value, preventing current from flowing in from the second doped layer. The entire PNPN structure blocks the current flow from the anode to the cathode, and the device enters the forward blocking or off state.

[0041] In the above alternative embodiments, the first doping type is P-type and the second doping type is N-type. The first doped layer (P-type) usually serves as part of the anode, and the second doped layer (N-type) serves as the base region of the device, with a relatively low doping concentration, used for transporting carriers and withstanding the blocking voltage. The third doped layer (P-type) and the fourth doped layer (P-type) are part of the gate region (the region where the gate is formed), and the fourth doped layer (P-type) is connected to the gate, used to control the switching state of the device.

[0042] In some embodiments, such as Figure 2 shown, the substrate 30 of the power semiconductor device in the present application may include a first doped layer 31, a second doped layer 32, and a third doped layer 33, and the third doped layer 33 is in contact with the gate 40. It may also be as Figure 3 and Figure 4 shown, the substrate 30 may include a first doped layer 31, a second doped layer 32, a third doped layer 33, and a fourth doped layer 34. The doping types of the third doped layer 33 and the fourth doped layer 34 are the same, and the doping concentration of the fourth doped layer 34 is higher than that of the third doped layer 33. The fourth doped layer 34 with a higher doping concentration can more easily form an ohmic contact with the gate 40, reducing the gate 40 contact resistance. When a positive voltage is applied to the gate 40, the PN junction formed by the fourth doped layer 34 and the cathode emitter 50 can be more easily opened, prompting electrons of the cathode emitter 50 to be injected into the fourth doped layer 34 and the third doped layer 33. The injection of electrons can significantly reduce the resistance of the third doped layer 33, thereby reducing the conduction voltage drop of the entire device and reducing the power loss in the conduction state.

[0043] In some alternative embodiments, such as Figure 4 shown, the device unit further includes: a plurality of second isolation layers 90. The second isolation layers 90 are located on the side of the first isolation layer 80 close to the substrate 30. Each second isolation layer 90 is in contact with the cathode 60 and the gate 40 respectively, and covers the first surface and a part of the cathode emitter 50. The thickness of the second isolation layer 90 is thinner, and the accuracy for etching to form the cathode 60 and the gate 40 is higher. Thus, after the gate 40 and the cathode 60 are formed, the distance deviation between the gate 40 and the cathode 60 can be smaller, improving the consistency of the characteristics of each device unit.

[0044] In the above alternative embodiments, the material of the second isolation layer may be an insulating material such as silicon dioxide. Such as Figure 4As shown, a second isolation layer 90 is formed before forming the gate 40. The second isolation layer 90 is etched to obtain the formation regions of the gate 40 and the cathode 60, and then the gate 40 and the cathode 60 are formed in the corresponding regions. The thickness of the second isolation layer 90 is thinner than the thickness of the electrode materials for forming the gate 40 and the cathode 60, and the etching accuracy is higher. In this way, after the gate 40 and the cathode 60 are formed, the distance deviation between the gate 40 and the cathode 60 can be smaller. If the electrode materials are directly formed and then etched to form the gate 40 and the cathode 60, since the thickness of the electrode materials is relatively thick, the etching deviation will be relatively large, and it is difficult to control the distance between the gate 40 and the cathode 60. Therefore, setting the second isolation layer 90 can improve the accuracy of the distance between the formed cathode 60 and the gate 40, and can better limit the distance between the gate 40 and the cathode 60 of each device unit to be basically the same, improving the consistency of the characteristics of each device unit.

[0045] In some alternative embodiments, there is a gap between the cathodes of any two device units. As Figure 5 and Figure 6 shown, by reducing the width of the cathode 60 of each device unit 20 on the basis of the power semiconductor device shown in Figures 2 to 4 , it can be ensured that the cathode 60 can cover part of the gate 40 in the vertical direction. When forming the layout of the power semiconductor device, the cathodes 60 between adjacent device units are separated, and it can be detected and identified which cathode 60 has problems, and the problematic cathode 60 can be removed, thereby improving the yield. Exemplarily, Figure 6 the cathode 60 in Figure 3 is about 200 μm wider than the cathode 60 in

[0046] Limiting it to 200 μm can not only make the device have good heat dissipation performance and surge resistance performance, but also improve the yield of the device.

[0047] In some alternative embodiments, as Figures 1 to 7 shown, the device unit further includes: a first isolation layer 80, at least part of the first isolation layer 80 is located between the cathode 60 and the gate 40, and the first isolation layer 80 covers the first surface and part of the cathode emitter 50. Figure 5The first isolation layer therein is the white area except for the cathode 60. The material of the first isolation layer 80 can be an insulating material such as silicon dioxide. In the embodiment of the present application, the first isolation layer 80 is used to achieve insulation in the longitudinal direction between the gate 40 and the cathode 60. When fabricating the device, by forming the cathode 60 after the first isolation layer 80 completely surrounds the gate 40, the limitation that the cathode 60 and the gate 40 cannot overlap in the transverse direction is broken through, thereby helping the device to better implement the large-area cathode 60 structure, reducing the contact thermal resistance of the device, and reducing the difficulty of the device fabrication process. Moreover, by using the first isolation layer 80, the gate 40 and the cathode 60 can be completely insulated, and the PI (Polyimide) passivation process for the gate 40 can be omitted, reducing the steps of coating and patterning polyimide on the gate 40 in the prior art, simplifying the process flow, and improving the flexibility of the device fabrication process. In addition, without the PI layer covering the gate 40, the heat dissipation capacity at the gate 40 is also improved, and the heat resistance characteristics of the device are enhanced.

[0048] In some alternative embodiments, such as Figure 1 、 Figure 5 and Figure 7 shown, the power semiconductor device further includes an alignment region 1, a gate lead-out portion 100, and a terminal region 110. Among them, as Figure 1 and Figure 5 shown, the device units 20 are arranged around the alignment region 1 with the alignment region 1 as the center. As Figure 7 shown, among the multiple gates 40, there are multiple target gates 41. The distance between the gates 40 other than the target gates 41 and the alignment region 1 is less than the distance between the target gates 41 and the alignment region 1, and the gate lead-out portion 100 is located on the target gates 41.

[0049] In the above alternative embodiments, Figure 7 only two target gates 41 of the device units 20 are shown. Figure 7 Among them, the left gate 40 is the gate 40 close to the alignment region, and the right target gate 41 is the gate close to the terminal region 110. The target gate 41 close to the terminal region 110 is set wider, and is used to set the gate lead-out portion 100 to lead out the gate 40 signal to the outside. Figure 4 The second isolation layer 90 in Figure 7 is the part of the first isolation layer 80 that is not covered by the cathode 60.

[0050] The fabrication method of the power semiconductor device of the present application includes the following steps:

[0051] Embodiment 1

[0052] The present embodiment provides a method for fabricating a device unit of a power semiconductor device, including the following steps:

[0053] Provide a substrate, which includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer. The second doped layer, the third doped layer, and the fourth doped layer are sequentially located on one surface of the first doped layer. The first doped layer is P-type doped, the second doped layer is N-type doped, the third doped layer is P-type doped, and the fourth doped layer is P-type doped. The doping concentration of the fourth doped layer is greater than that of the third doped layer. The fourth doped layer has a first surface on the side facing away from the first doped layer.

[0054] Form a second isolation layer on the first surface, and perform an etching process on the second isolation layer to form a gate region and a cathode region on the first surface. Since the thickness of the second isolation layer is relatively thin and the etching precision is high, the distance between the gate region and the cathode region formed by etching is easy to control. Among them, the distance between the gate region and the cathode region of each device unit in the power semiconductor device can be made basically the same, which is convenient for subsequent testing.

[0055] Form a gate in the gate region, deposit a first isolation layer on the gate, and perform an etching process on the first isolation layer to expose the cathode region.

[0056] Form a cathode in the cathode region. Part of the cathode covers the first isolation layer, and the projection of the cathode on the first surface covers the projection of the gate on the first surface.

[0057] Form an anode on the side of the first doped layer facing away from the second doped layer.

[0058] Embodiment 2

[0059] This embodiment provides a method for manufacturing a device unit of a power semiconductor device, including the following steps:

[0060] Provide a substrate, which includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer. The second doped layer, the third doped layer, and the fourth doped layer are sequentially located on one surface of the first doped layer. The first doped layer is P-type doped, the second doped layer is N-type doped, the third doped layer is P-type doped, and the fourth doped layer is P-type doped. The doping concentration of the fourth doped layer is greater than that of the third doped layer. The fourth doped layer has a first surface on the side facing away from the first doped layer.

[0061] Deposit gate metal on the first surface, and etch the gate metal to obtain a gate.

[0062] Deposit a first isolation layer on the gate. The first isolation layer covers the first surface and the gate, and perform an etching process on the first isolation layer to expose part of the first surface to form a cathode region.

[0063] Deposit cathode metal in the cathode region to form a cathode. Part of the cathode covers the first isolation layer, and the projection of the cathode on the first surface covers the projection of the gate on the first surface.

[0064] An anode is formed on the side of the first doping layer away from the second doping layer.

[0065] A terminal region is formed.

[0066] From the above description, it can be seen that the power semiconductor device provided by this application achieves the following technical effects:

[0067] 1) Increasing the cathode area can improve the heat dissipation capacity of the cathode, reduce the thermal resistance of the power semiconductor device, reduce the risk of local overheating of the cathode, and further improve the surge resistance of the device.

[0068] 2) By increasing the area of the cathode, when the power semiconductor device withstands a large current, the current can be conducted quickly, the current density is reduced, and the ability of the device to withstand an instantaneous large current is improved.

[0069] 3) After the cathode area is increased, the process window for manufacturing the power semiconductor device is enlarged, and the manufacturing difficulty of the power semiconductor device is reduced.

[0070] 4) The first isolation layer realizes the insulation between the gate and the cathode longitudinally. By forming the cathode after completely surrounding the gate with the first isolation layer, the limitation that the cathode and the gate cannot overlap laterally is broken through, thereby helping the device to better realize a large-area cathode structure, reducing the contact thermal resistance of the device, and reducing the manufacturing process difficulty of the device.

[0071] 5) Using the first isolation layer can completely insulate between the gate and the cathode, no longer perform the PI (Polyimide) passivation process on the gate, reduce the coating and patterning of polyimide, simplify the process flow, improve the flexibility of the device manufacturing process, and without the PI layer covering on the gate, the heat dissipation capacity at the gate is also improved, and the heat resistance characteristics of the device are improved.

[0072] The above are only the preferred embodiments of this application and are not used to limit this application. For those skilled in the art, this application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims

1. A power semiconductor device, characterized in that: The invention comprises a plurality of device units, wherein the device units include: a substrate having a first surface; A plurality of gate electrodes are spaced apart and located on the first surface; a cathode emitter, at least a portion of which is located in the substrate; A cathode is located at a side of the cathode emitter away from the substrate, and an orthographic projection of the cathode on the first surface covers at least a portion of an orthographic projection of the gate on the first surface.

2. The power semiconductor device according to claim 1, characterized in that: The cathodes of any two of the device units are connected to each other.

3. The power semiconductor device according to claim 1, characterized in that: There is a gap between the cathodes of any two of the device units.

4. The power semiconductor device according to claim 1, characterized in that: The substrate comprises: a first doped layer having a first doping type; A second doping layer, located on one side of the first doping layer, the second doping layer having a second doping type, the first doping type and the second doping type being different; a third doping layer, located on a side of the second doping layer away from the first doping layer, the third doping layer having the first doping type; The fourth doping layer is located on a side of the third doping layer away from the second doping layer, a surface of the fourth doping layer away from the first doping layer is the first surface, and the fourth doping layer has the first doping type.

5. The power semiconductor device according to claim 1, characterized in that: The device unit further includes an anode, which is located on a side of the substrate facing away from the cathode.

6. The power semiconductor device according to claim 1, characterized in that: A portion of the cathode emitter is located in the substrate, and another portion of the cathode emitter protrudes from the first surface.

7. The power semiconductor device according to claim 1, characterized in that: A surface of the cathode emitter facing away from the substrate is located in the first surface.

8. The power semiconductor device according to claim 1, characterized in that: The device unit further includes: a first isolation layer, at least a portion of the first isolation layer is located between the cathode and the gate, and the first isolation layer covers the first surface and a portion of the cathode emitter.

9. The power semiconductor device according to claim 8, characterized in that: The device unit further includes: a plurality of second isolation layers, the second isolation layers are located on a side of the first isolation layer close to the substrate, each of the second isolation layers is in contact with the cathode and the gate respectively, and covers the first surface and a portion of the cathode emitter.

10. The power semiconductor device according to claim 1, characterized in that: The power semiconductor device also includes an alignment area and a gate lead-out portion, wherein the device unit is arranged around the alignment area with the alignment area as the center, there are multiple target gates among the multiple gates, the distance between the gates other than the target gate and the alignment area is smaller than the distance between the target gate and the alignment area, and the gate lead-out portion is located on the target gate and corresponds one-to-one to the target gate.

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