Fan-out wafer level packaging unit
By designing a multi-layer conduction structure and welding pad electrical connection in a fanout wafer-level packaging unit, the problems of high manufacturing cost and unenvironmental protection of the conduction circuit are solved, and the integration of lightweight and short and efficient electrical connections are achieved.
Patent Information
- Application Number
- CN202421482765.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-26
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-06-26
AI Technical Summary
The existing fan-out packaging technology has high manufacturing costs and is not conducive to environmental protection when making guide lines. In multi-chip fan-out wafer-level packaging units, the design space demand for guide lines has increased, making it difficult for the technology to maintain the integrated effect of lightness, thinness and shortness.
A fan-out wafer-level packaging unit design is adopted to form a multi-layer conduction structure through the combination of carrier plate, dielectric layer and conduction circuit, and conduction circuit is formed by metal paste filling and grinding technology, and a solder pad is formed through the opening of the outer cover layer to achieve electrical connection.
It effectively reduces the manufacturing cost of the conductor circuit, improves environmental protection performance, and maintains or achieves a certain degree of lightweight, short and integrated effect in multi-chip models, improving the market competitiveness of the product.
Smart Images
Figure CN222927492U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a packaging unit, in particular to a fan-out wafer-level packaging unit. Background Art
[0002] The development trend of the semiconductor industry is towards thin, light, short, and small packaging technologies with high efficiency and high reliability. Among them, fan-out wafer-level packaging (FOWLP) is an existing packaging technology.
[0003] In advanced packaging FOWLP, the redistribution layer (RDL) is the most critical. Because the conductive lines in the RDL can cause the XY-plane electrical extension and interconnection of multiple pads on the die, so that a plurality of pads can be formed more dispersedly around each die, thereby effectively improving the design space and reliability of each conductive line. However, how to make each conductive line in the RDL maintain or achieve a certain degree of thin, light, short, and small effect while generating the XY-plane electrical extension and interconnection effect is the most critical for the production of each conductive line in the RDL. However, the forming method of each conductive line in the RDL technology applied in the existing FOWLP packaging technology is to use electroless plating forming technology or electroplating forming technology to manufacture. In this way, in addition to the relatively high material cost and manufacturing cost, the existing manufacturing process also does not meet or is not conducive to environmental protection requirements.
[0004] In addition, when the FOWLP is used to provide products with higher performance or more functions, generally, at least two or more dies are stacked in the FOWLP and integrated through the RDL to form a multi-chip type fan-out wafer-level packaging unit. At this time, the demand for the design space of each conductive line in the RDL of the FOWLP will increase relatively, and the manufacturing technology of each conductive line in the RDL is also relatively more critical. Summary of the Utility Model
[0005] The main object of the present utility model is to provide a fan-out wafer-level packaging unit, comprising a carrier plate, at least one lower die, a first dielectric layer, at least one first connection line, a second dielectric layer, at least one second connection line, at least one upper die, a third dielectric layer, at least one third connection line, a fourth dielectric layer, at least one fourth connection line and an outer protective layer; wherein the at least one lower die and the at least one upper die form a corresponding relationship of being stacked at intervals one above the other; wherein each of the fourth connection lines forms a solder pad within each opening of the outer protective layer; and wherein the at least one lower die and the at least one upper die can be electrically connected externally through the solder pads around the chip regions on the second surfaces of the respective upper dies, effectively solving the problems that the existing fan-out packaging technology is prone to high manufacturing costs and is not environmentally friendly when manufacturing the respective connection lines.
[0006] To achieve the above object, the present utility model provides a fan-out wafer-level packaging unit, which includes a carrier plate, at least one lower die, a first dielectric layer, at least one first conductive line, a second dielectric layer, at least one second conductive line, at least one upper die, a third dielectric layer, at least one third conductive line, a fourth dielectric layer, at least one fourth conductive line, and an outer protective layer; wherein the carrier plate has a first surface; wherein each of the lower dies is divided from at least one wafer, each of the lower dies has a first surface and a second surface opposite thereto, and a plurality of pads are provided on the second surface of each of the lower dies, and the first surface of the lowermost one of the lower dies in each of the lower dies is fixedly provided on the first surface of the carrier plate; wherein the first dielectric layer correspondingly covers each of the lower dies, the first dielectric layer has a plurality of first grooves formed by extending horizontally, and each of the pads of each of the lower dies is electrically connected to the outside through the plurality of first grooves; wherein each of the first conductive lines is formed by filling a metal paste in each of the first grooves, and each of the first conductive lines is electrically connected to each of the pads of each of the lower dies; wherein the second dielectric layer correspondingly covers each of the lower dies and is disposed on the first dielectric layer, the second dielectric layer has a plurality of second grooves formed by extending horizontally, and each of the second grooves communicates with each of the first grooves; wherein each of the second conductive lines is formed by filling a metal paste in the plurality of second grooves, and each of the second conductive lines is electrically connected to each of the first conductive lines; wherein each of the upper dies is divided from at least one wafer, each of the upper dies has a first surface and a second surface opposite thereto, a plurality of pads are provided on the second surface of each of the upper dies, and the vertical chip area of the second surface of each of the upper dies is defined as a chip area, and the first surface of the lowermost one of the upper dies in each of the upper dies is fixedly provided on the second dielectric layer; wherein the third dielectric layer correspondingly covers each of the upper dies, the third dielectric layer has a plurality of third grooves formed by extending horizontally, and each of the pads of each of the upper dies is electrically connected to the outside through the plurality of third grooves; wherein each of the third conductive lines is formed by filling a metal paste in each of the third grooves, and each of the third conductive lines is electrically connected to each of the second conductive lines; wherein the fourth dielectric layer correspondingly covers each of the upper dies and is disposed on the third dielectric layer, the fourth dielectric layer has a plurality of fourth grooves formed by extending horizontally, and each of the fourth grooves communicates with each of the third grooves; wherein each of the fourth conductive lines is formed by filling a metal paste in the plurality of fourth grooves, and each of the fourth conductive lines is electrically connected to the third conductive line or electrically connected to each of the pads of each of the upper dies;The outer protective layer is disposed on the fourth dielectric layer. The outer protective layer has a plurality of openings, and at least one of the openings is around the chip region on the second surface of each of the lower bare dies and around the chip region on the second surface of each of the upper bare dies. Each of the fourth conductive lines is exposed to the outside through each of the openings to form a solder pad in the plurality of openings. The at least one lower bare die and the at least one upper bare die are in a one - on - one correspondence and are stacked on the carrier board at intervals. The at least one lower bare die can be electrically connected to the at least one upper bare die sequentially through each of the first conductive lines, each of the second conductive lines, each of the third conductive lines, and each of the fourth conductive lines. The at least one lower bare die can be electrically connected to the outside through each of the first conductive lines, each of the second conductive lines, each of the third conductive lines, each of the fourth conductive lines, and each solder pad around the chip region on the second surface of each of the lower bare dies. The at least one upper bare die can be electrically connected to the outside through each of the fourth conductive lines and each solder pad around the chip region on the second surface of each of the upper bare dies, thereby forming the fan - out wafer - level packaging unit.
[0007] In a preferred embodiment of the present utility model, the vertical chip region on the second surface of the at least one lower bare die is further defined as a chip region. The at least one lower bare die can be electrically connected to the outside sequentially through each of the first conductive lines, each of the second conductive lines, each of the third conductive lines, each of the fourth conductive lines, and each solder pad around the chip region on the second surface of each of the lower bare dies.
[0008] In a preferred embodiment of the present utility model, the at least one lower bare die and the at least one upper bare die are formed by dividing from the same wafer or different wafers.
[0009] In a preferred embodiment of the present utility model, the carrier board includes a silicon (Si) carrier board, a glass carrier board, or a ceramic carrier board.
[0010] In a preferred embodiment of the present utility model, the metal paste constituting each of the first conductive lines, each of the second conductive lines, each of the third conductive lines, and each of the fourth conductive lines includes silver paste, nano - silver paste, copper paste, or nano - copper paste.
[0011] In a preferred embodiment of the present utility model, the first surface of the at least one lower bare die is further disposed on the carrier board by using a die attach film (DAF). The first surface of the at least one lower bare die is further disposed on the second dielectric layer by using a die attach film.
[0012] In a preferred embodiment of the present utility model, a solder ball is further provided on each of the openings, and each solder ball can be electrically connected to each solder pad in each of the openings; wherein the fan-out wafer-level packaging unit can be disposed on an electronic component in an electrically connected manner by using each solder ball.
[0013] In a preferred embodiment of the present utility model, a bump is further provided on each of the openings, and each bump can be electrically connected to each solder pad in each of the openings; wherein the fan-out chip packaging unit can form solder joints on each of the bumps and an electronic component respectively through wire bonding operations and be electrically connected through a bonding wire. Brief Description of the Drawings
[0014] Figure 1 It is a schematic plan view of a side cross-section of the fan-out wafer-level packaging unit of the present utility model disposed on an electronic component.
[0015] Figure 2 It is a schematic plan view of a side cross-section of the fan-out wafer-level packaging unit of the present utility model electrically connected to an electronic component through wire bonding.
[0016] Figure 3 It is a schematic plan view of a side cross-section of the lower die of the present utility model disposed on a carrier.
[0017] Figure 4 It is Figure 3 a schematic plan view of a side cross-section of the lower die in being coated with a first dielectric layer.
[0018] Figure 5 It is Figure 4 a schematic plan view of a side cross-section of the metal paste being filled in the first groove of the first dielectric layer in .
[0019] Figure 6 It is Figure 5 a schematic plan view of a side cross-section of the metal paste higher than the surface of the first dielectric layer in being polished.
[0020] Figure 7 It is Figure 6 a schematic plan view of a side cross-section of a second dielectric layer being disposed on the first dielectric layer in .
[0021] Figure 8 It is Figure 7 a schematic plan view of a side cross-section of the metal paste being filled in the second groove of the second dielectric layer in .
[0022] Figure 9 It is Figure 8 a schematic plan view of a side cross-section of the metal paste higher than the surface of the second dielectric layer in being polished.
[0023] Figure 10 is Figure 9 A schematic plan view of a side cross-section of an upper die set on a second dielectric layer in
[0024] Figure 11 is Figure 10 A schematic plan view of a side cross-section of an upper die covered by a third dielectric layer in
[0025] Figure 12 is Figure 11 A schematic plan view of a side cross-section of a metal paste filled in a third groove of a third dielectric layer in
[0026] Figure 13 is Figure 12 A schematic plan view of a side cross-section of a metal paste ground above the surface of a third dielectric layer in
[0027] Figure 14 is Figure 13 A schematic plan view of a side cross-section of a fourth dielectric layer set on a third dielectric layer in
[0028] Figure 15 is Figure 14 A schematic plan view of a side cross-section of a metal paste filled in a fourth groove of a fourth dielectric layer in
[0029] Figure 16 is Figure 15 A schematic plan view of a side cross-section of a metal paste ground above the surface of a fourth dielectric layer in
[0030] Figure 17 is Figure 16 A schematic plan view of a side cross-section of an outer protective layer set on a fourth dielectric layer in
[0031] Figure 18 is Figure 17 A schematic plan view of a side cross-section of solder balls provided on each opening of
[0032] Figure 19 is Figure 17 A schematic plan view of a side cross-section of bumps provided on each opening of
[0033] Explanation of reference numerals: 1-fan-out wafer-level packaging unit; 1a-chip area; 1b-chip area; 10-carrier; 11-first surface; 20-lower bare crystal; 21-first surface; 22-second surface; 23-crystal pad; 30-first dielectric layer; 31-first groove; 40-first conductive line; 40a-metal paste; 50-second dielectric layer; 51-second groove; 60-second conductive line; 60a-metal paste; 70-upper bare crystal ;71-first surface;72-second surface;73-crystal pad;80-third dielectric layer;81-third groove;90-third conductive line;90a-metal paste;100-fourth dielectric layer;101-fourth groove;110-fourth conductive line;110a-metal paste;111-soldering pad;120-outer protective layer;121-opening;130-chip bonding film;140-solder ball;150-bump;2-electronic component;3-soldering wire. DETAILED DESCRIPTION
[0034] With the help of illustrations, the structure and technical features of the present invention are described in detail as follows, wherein each illustration is only used to illustrate the structural relationship and related functions of the present invention, so the size of each element in each illustration is not drawn according to the actual scale and is not used to limit the present invention.
[0035] refer to Figure 17 A fan-out wafer-level packaging unit 1 includes a carrier 10, at least one lower die 20 (die), a first dielectric layer 30, at least one first conductive circuit 40, a second dielectric layer 50, at least one second conductive circuit 60, at least one upper die 70, a third dielectric layer 80, at least one third conductive circuit 90, a fourth dielectric layer 100, at least one fourth conductive circuit 110 and an outer protective layer 120.
[0036] The at least one lower layer bare die 20 and the at least one upper layer bare die 70 are stacked on the carrier 10 in a corresponding relationship and spaced apart. Figure 17 As shown, no matter whether the number of layers of each lower-layer bare die 20 is 3 layers, 4 layers, or more than 5 layers, each lower-layer bare die 20 is located below each upper-layer bare die 70. Conversely, the same is true for each upper-layer bare die 70. No matter whether the number of layers of each upper-layer bare die 70 is 3 layers, 4 layers, or more than 5 layers, each upper-layer bare die 70 is located above each lower-layer bare die 20.
[0037] In addition, in each layer of arrangement of each lower layer bare die 20, multiple lower layer bare die 20 can be arranged in parallel and spaced apart in the horizontal direction, such as 3, 4 or 5 or more bare die arranged in the horizontal direction in one layer (not shown). Correspondingly, in each layer of arrangement of each upper layer bare die 70, multiple upper layer bare die 70 can be arranged in parallel and spaced apart in the horizontal direction, such as 3, 4 or 5 or more bare die arranged in the horizontal direction in one layer (not shown).
[0038] The carrier board 10 has a first surface 11, as Figure 3 shown.
[0039] Each lower die 20 is divided from at least one wafer. Each lower die 20 has a first surface 21 and a second surface 22 opposite thereto. A plurality of pads 23 are provided on the second surface 22 of each lower die 20, as Figure 3 shown; wherein the first surface 21 of the lowermost lower die 20 among each lower die 20 is fixedly provided on the first surface 11 of the carrier board 10, as Figure 3 shown. In Figure 3 each lower die 20, two pads 23 are taken as an example for the pads 23 of each lower die 20, but it is not intended to limit the present invention.
[0040] The first dielectric layer 30 correspondingly covers each lower die 20. The first dielectric layer 30 has a plurality of first grooves 31 formed by extending horizontally, as Figure 4 shown; wherein each pad 23 of each lower die 20 is electrically connected to the outside through each first groove 31, as Figure 4 shown.
[0041] Each first conductive line 40 is composed of a metal paste 40a filled in each first groove 31, as Figure 6 shown; wherein each first conductive line 40 is electrically connected to each pad 23 of each lower die 20, as Figure 6 shown; wherein the metal paste 40a forming each first conductive line 40 includes silver paste, nano - silver paste, copper paste or nano - copper paste, but is not limited thereto. The nano - silver paste material has characteristics such as low cost, high conductivity and the ability to sinter at low temperature. However, since the nano - silver paste material is a common existing material, it will not be elaborated here.
[0042] The second dielectric layer 50 correspondingly covers each lower die 20 and is disposed on the first dielectric layer 30. The second dielectric layer 50 has a plurality of second grooves 51 formed by extending horizontally, as Figure 7 shown; wherein each second groove 51 communicates with each first groove 31, as Figure 7 shown.
[0043] Each second conductive line 60 is composed of a metal paste 60a filled in each second groove 51, as Figure 9 shown; wherein each second conductive line 60 is electrically connected to each first conductive line 40, as Figure 9 shown; wherein the metal paste 60a forming each second conductive line 60 includes silver paste, nano - silver paste, copper paste or nano - copper paste, but is not limited thereto.
[0044] Each upper die 70 is separated from at least one wafer. Each upper die 70 has a first surface 71 and a second surface 72 opposite thereto. A plurality of pads 73 are provided on the second surface 72 of each upper die 70, as Figure 10 shown, and the vertical chip area of the second surface 72 of each upper die 70 is defined as a chip area 1a, as Figure 11 shown; wherein the first surface 71 of the lowermost upper die 70 in each upper die 70 is fixedly provided on the second dielectric layer 50, as Figure 10 shown. In Figure 11 each upper die 70, two pads 23 are taken as an example for the pads 73 of each upper die 70, but it is not intended to limit the present invention.
[0045] The third dielectric layer 80 correspondingly covers each upper die 70. The third dielectric layer 80 has a plurality of third grooves 81 formed by extending horizontally, as Figure 11 shown; wherein the pads 73 of each upper die 70 are electrically connected to the outside through the third grooves 81, as Figure 11 shown.
[0046] Each third conductive line 90 is composed of a metal paste 90a filled in each third groove 81, as Figure 13 shown; wherein each third conductive line 90 is electrically connected to each second conductive line 60, as Figure 13 shown; wherein the metal paste 90a constituting each third conductive line 90 includes silver paste, nano-silver paste, copper paste or nano-copper paste, but is not limited thereto.
[0047] The fourth dielectric layer 100 correspondingly covers each upper die 70 and is disposed on the third dielectric layer 80. The fourth dielectric layer 100 has a plurality of fourth grooves 101 formed by extending horizontally, as Figure 14 shown; wherein each fourth groove 101 communicates with each third groove 81, as Figure 14 shown.
[0048] Each fourth conductive line 110 is composed of a metal paste 110a filled in each fourth groove 101, as Figure 16 shown; wherein each fourth conductive line 100 is electrically connected to the third conductive line 90 or electrically connected to the pads 73 of each upper die 70, as Figure 16 shown; wherein the metal paste 110a constituting each fourth conductive line 110 includes silver paste, nano-silver paste, copper paste or nano-copper paste, but is not limited thereto.
[0049] The outer protective layer 120 is disposed on the fourth dielectric layer 100. The outer protective layer 120 has a plurality of openings 121, and at least one of the openings 121 is around the chip region 1a on the second surface 22 of each of the lower dies 20 and around the chip region 1a on the second surface 72 of each of the upper dies 70, as Figure 17 shown; wherein each of the fourth conductive lines 110 is exposed to the outside through each of the openings 121 to form a solder pad 111 within each of the openings 121, as Figure 17 shown.
[0050] The at least one lower die 20 can be electrically connected to the at least one upper die 70 sequentially through the respective first conductive lines 40, the respective second conductive lines 60, the respective third conductive lines 90, and the respective fourth conductive lines 110, as Figure 17 shown; wherein the at least one lower die 20 can be electrically connected to the outside through the respective first conductive lines 40, the respective second conductive lines 60, the respective third conductive lines 90, and the respective fourth conductive lines 110 to the respective solder pads 111 around the chip region 1a on the second surface 72 of each of the upper dies 70, as Figure 17 shown; wherein the at least one upper die 70 can be electrically connected to the outside through the respective fourth conductive lines 110 to the respective solder pads 111 around the chip region 1a on the second surface 72 of each of the upper dies 70, thereby forming the fan-out wafer-level packaging unit 1, as Figure 17 shown.
[0051] The method for manufacturing the fan-out wafer-level packaging unit 1 may include the following steps, but is not limited to:
[0052] Step S1: Provide a carrier 10, as Figure 3 shown.
[0053] Step S2: Dispose a plurality of lower dies 20 separated from at least one wafer on the carrier 10, and fix a first surface 21 of each of the lowermost lower dies 20 among the lower dies 20 on the carrier 10, as Figure 3 shown; wherein each of the lower dies 20 has a second surface 22 opposite to the first surface 21, and a plurality of die pads 23 are provided on the second surface 22 of each of the lower dies 20, as Figure 3 shown.
[0054] Step S3: First, cover a first dielectric layer 30 on the at least one lower die 20, as Figure 4 shown, and form a plurality of first grooves 31 horizontally on the first dielectric layer 30, as Figure 4 shown, so that each of the die pads 23 of each of the lower dies 20 can be exposed to the outside through each of the first grooves 31 of the first dielectric layer 30, asFigure 4 As shown, next, the metal paste 40a is filled into each of the first grooves 31 of the first dielectric layer 30, as Figure 5 shown, and the thickness of the metal paste 40a is higher than the surface of the first dielectric layer 30, as Figure 5 shown, and the metal paste 40a that is higher than the surface of the first dielectric layer 30 is ground, as Figure 6 shown, so that the surface of the metal paste 40a is flush with the surface of the first dielectric layer 30 to form a plurality of first connection lines 40, as Figure 6 shown. After that, a second dielectric layer 50 is covered on the first dielectric layer 30, as Figure 7 shown, and a plurality of second grooves 51 are formed horizontally on the second dielectric layer 50, as Figure 7 shown, so that each of the first connection lines 40 in each of the first grooves 31 of the first dielectric layer 30 can be exposed to the outside through each of the second grooves 51 of the second dielectric layer 50, as Figure 7 shown. Finally, the metal paste 60a is filled into each of the second grooves 51 of the second dielectric layer 50, as Figure 8 shown, and the thickness of the metal paste 60a is higher than the second dielectric layer 50, as Figure 8 shown, and the metal paste 60a that is higher than the surface of the second dielectric layer 50 is ground, as Figure 9 shown, so that the surface of the metal paste 60a is flush with the surface of the second dielectric layer 50 to form a plurality of second connection lines 60, as Figure 9 shown.
[0055] Step S4: A plurality of upper bare dies 70 separated from at least one wafer are disposed on the second dielectric layer 50 on each of the lower bare dies 20, as Figure 10 shown; wherein each upper bare die 70 has a first surface 71 and a second surface 72 opposite thereto, and a plurality of pads 73 are provided on the second surface 72 of each upper bare die 70, as Figure 10 shown, and the vertical chip area of the second surface 72 of each upper bare die 70 is defined as a chip area 1a, as Figure 11 shown.
[0056] Step S5: First, a third dielectric layer 80 is covered on the at least one upper bare die 70, as Figure 11 shown, and a plurality of third grooves 81 are formed horizontally on the third dielectric layer 80, as Figure 11 shown, so that each of the pads 73 of each upper bare die 70 can be exposed to the outside through each of the third grooves 81 of the third dielectric layer 80, as Figure 11 shown. Next, the metal paste 90a is filled into each of the third grooves 81 of the third dielectric layer 80, as Figure 12 shown, and the thickness of the metal paste 90a is higher than the surface of the third dielectric layer 80, asFigure 12 as shown, and grind the metal paste 90a that is higher than the surface of the third dielectric layer 80, as Figure 13 shown, so that the surface of the metal paste 90a is flush with the surface of the third dielectric layer 80 to form a plurality of third connection lines 90, as Figure 13 shown. After that, cover a fourth dielectric layer 100 on the third dielectric layer 80, as Figure 14 shown, and form a plurality of fourth grooves 101 horizontally on the fourth dielectric layer 100, as Figure 14 shown, so that each of the third connection lines 90 in each of the fourth grooves 101 of the fourth dielectric layer 100 can be exposed to the outside through each of the fourth grooves 101 of the fourth dielectric layer 100, as Figure 14 shown. Finally, fill the metal paste 110a into each of the fourth grooves 101 of the fourth dielectric layer 100, as Figure 15 shown, and the thickness of the metal paste 110a is higher than that of the fourth dielectric layer 100, as Figure 15 shown, and grind the metal paste 110a that is higher than the surface of the fourth dielectric layer 100, as Figure 16 shown, so that the surface of the metal paste 110a is flush with the surface of the fourth dielectric layer 100 to form a plurality of fourth connection lines 110, as Figure 16 shown.
[0057] Step S6: Lay an outer protective layer 120 on the fourth dielectric layer 100, as Figure 17 shown.
[0058] Step S7: Form a plurality of openings 121 in the outer protective layer 120 and make at least one of the openings 121 formed around a chip area 1a on the second surface 72 of each upper die 70, as Figure 17 shown, so that each of the fourth connection lines 110 can be exposed to the outside through each of the openings 121 to form a solder pad 111 in each of the openings 121, as Figure 17 shown.
[0059] Step S8: Perform a dicing operation to dice and form a plurality of fan-out wafer-level packaging units 1, as Figure 17 shown.
[0060] In the manufacturing process of steps S3 and S5 in the method for manufacturing the fan-out wafer-level packaging unit 1, it can be regarded as the key steps for fabricating the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1. Among them, in step S3, the metal paste 40a is filled into each of the first grooves 31 of the first dielectric layer 30, as Figure 5 shown, and the thickness of the metal paste 40a is higher than the surface of the first dielectric layer 30, as Figure 5As shown, the metal paste 40a above the surface of the first dielectric layer 30 is ground, as Figure 6 shown, and the metal paste 60a is filled into each second groove 51 of the second dielectric layer 50, as Figure 8 shown, and the thickness of the metal paste 60a is higher than that of the second dielectric layer 50, as Figure 8 shown, and the metal paste 60a above the surface of the second dielectric layer 50 is ground, as Figure 9 shown; wherein in step S5, the metal paste 90a is filled into each third groove 81 of the third dielectric layer 80, as Figure 12 shown, and the thickness of the metal paste 90a is higher than the surface of the third dielectric layer 80, as Figure 12 shown, and the metal paste 90a above the surface of the third dielectric layer 80 is ground, as Figure 13 shown, and the metal paste 110a is filled into each fourth groove 101 of the fourth dielectric layer 100, as Figure 15 shown, and the thickness of the metal paste 110a is higher than that of the fourth dielectric layer 100, as Figure 15 shown, and the metal paste 110a above the surface of the fourth dielectric layer 100 is ground, as Figure 16 shown. Since both step S3 and step S5 are processes that are easy to implement precisely, the process is relatively simplified, sufficient to enable each first conductive line 40, each second conductive line 60, each third conductive line 90, and each fourth conductive line 110 in the redistribution layer to generate XY-plane electrical extension and interconnection effects, and at the same time enable the fabricated fan-out wafer-level packaging unit 1 to still maintain or achieve a certain degree of thin, light, short, and small specific effects. And in the case where the at least one lower die 20 and the at least one upper die 70 in the fan-out wafer-level packaging unit 1 form a one-up-one-down corresponding relationship and are stacked on the carrier 10 at intervals, it still maintains or achieves a certain degree of thin, light, short, and small effects.
[0061] Refer to Figure 17 , wherein the vertical chip area of the second surface 22 of the at least one lower die 20 is further defined as a chip area 1b but not limited; wherein the at least one lower die 20 can be electrically connected to the outside in sequence through each first conductive line 40, each second conductive line 60, each third conductive line 90, each fourth conductive line 110, and each pad 111 around the chip area 1b on the second surface 22 of each lower die 20 but not limited, so as to increase the market competitiveness of the product.
[0062] Refer to Figure 17 , the at least one lower die 20 and the at least one upper die 70 are formed by dividing from the same wafer or different wafers but not limited, which is conducive to diversified product development applications.
[0063] Reference Figure 3 , the carrier substrate 10 includes a silicon (Si) carrier substrate, a glass carrier substrate, or a ceramic carrier substrate, but is not limited thereto, to facilitate diversified product development applications.
[0064] Reference Figure 3 , the first surface 21 of the at least one lower die 20 is further disposed on the carrier substrate 10 by using a die attach film (DAF), but is not limited thereto.
[0065] Reference Figure 10 , the first surface 71 of the at least one lower die 70 is further disposed on the second dielectric layer 50 by using a die attach film 130, but is not limited thereto.
[0066] Reference Figure 18 , a solder ball 140 is further provided on each opening 121, but is not limited thereto. Each solder ball 140 can be electrically connected to each pad 111 in each opening 121; wherein the fan-out wafer-level packaging unit 1 can be electrically connected and disposed on an electronic component 2 by using each solder ball 140 (such as by flip-chip technology to cover the fan-out wafer-level packaging unit 1 on the electronic component 2), as Figure 1 shown.
[0067] Reference Figure 19 , a bump 150 is further provided on each opening 121, but is not limited thereto. Each bump 150 can be electrically connected to each pad 111 in each opening 121; wherein the fan-out chip packaging unit 1 can form solder joints on each bump 150 and on an electronic component 2 respectively through wire bonding operations and be electrically connected through a bonding wire 3, as Figure 2 shown; wherein each bump 150 further bears the positive pressure generated during wire bonding operations or when forming solder joints, so that the internal circuit will not be damaged due to the positive pressure, and the internal circuit (such as each fourth conductive line 110 and each pad 111 around the chip area 1b on the second surface 22 of each lower die 20) can be allowed to pass through or be arranged under each bump 150.
[0068] In addition, the bonding wire 3 can further form solder joints on each bump 150 respectively through wire bonding operations, so that each bump 150 can also be electrically connected to each other through the bonding wire 3 (not shown in the figure), so that the dies at different locations can be electrically connected to each other. The wire bonding described above is a common existing technique and will not be elaborated here.
[0069] In order to illustrate the structural relationship and related functions of the present invention, in the present invention's Figure 1 , Figure 2 and Figures 10 to 19In the illustrated embodiment, the die on the carrier 10 further includes one lower die 20 in one layer and one upper die 70 in one layer. However, this is not restrictive. That is, the dies on the carrier 10 are stacked vertically with two dies as an example for illustration, but it is not intended to limit the present invention. It is only a preferred embodiment of the present invention, which is illustrative rather than restrictive to the present invention.
[0070] Compared with the existing fan-out wafer-level packaging unit technology, the fan-out wafer-level packaging unit 1 of the present invention has the following advantages:
[0071] (1) In steps S3 and S5 of the method for manufacturing the fan-out wafer-level packaging unit 1 of the present invention in the above example, compared with the related technologies for manufacturing existing fan-out wafer-level packaging units, when manufacturing the present invention, through the production of each conductive line in the RDL, each conductive line in the RDL can maintain or achieve a certain degree of thin, light, short, and small effects while generating XY-plane electrical extension and interconnection effects. These are all simplified and easily precisely implemented steps, especially beneficial for reducing the thickness of the packaging unit. Therefore, the manufacturing process of the present invention is not only more simplified and cost-saving, but also can effectively improve the usage efficiency and reliability of the fan-out wafer-level packaging unit 1.
[0072] (2) In the forming process of the conductive lines of the fan-out wafer-level packaging unit 1 of the present invention, the metal paste 40a can be filled into each first groove 31 of the first dielectric layer 30, as Figure 5 shown, and the thickness of the metal paste 40a is higher than the surface of the first dielectric layer 30, as Figure 5 shown, and the metal paste 40a higher than the surface of the first dielectric layer 30 is ground, as Figure 6 shown, and the metal paste 60a is filled into each second groove 51 of the second dielectric layer 50, as Figure 8 shown, and the thickness of the metal paste 60a is higher than the second dielectric layer 50, as Figure 8 shown, and the metal paste 60a higher than the surface of the second dielectric layer 50 is ground, as Figure 9 shown, and the metal paste 90a is filled into each third groove 81 of the third dielectric layer 80, as Figure 12 shown, and the thickness of the metal paste 90a is higher than the surface of the third dielectric layer 80, as Figure 12 shown, and the metal paste 90a higher than the surface of the third dielectric layer 80 is ground, as Figure 13 shown, and the metal paste 110a is filled into each fourth groove 101 of the fourth dielectric layer 100, as Figure 15 shown, and the thickness of the metal paste 110a is higher than the fourth dielectric layer 100, as Figure 15as shown, and grind the metal paste 110a that is higher than the surface of the fourth dielectric layer 100, as Figure 16 shown. Therefore, the present utility model can effectively solve the problems of high manufacturing cost and environmental unfriendliness that are prone to occur in the existing fan-out package technology when manufacturing each conductive line.
[0073] (3) The at least one lower die 20 of the fan-out wafer-level package unit 1 of the present utility model can be electrically connected to the at least one upper die 70 in sequence through each first conductive line 40, each second conductive line 60, each third conductive line 90, and each fourth conductive line 110 (formed by RDL technology), as Figure 17 shown; wherein the at least one lower die 20 can be electrically connected to each pad 111 around the chip area 1a on the second surface 72 of each upper die 70 in sequence through each first conductive line 40, each second conductive line 60, each third conductive line 90, and each fourth conductive line 110 (formed by RDL technology) for external electrical connection, as Figure 17 shown; wherein the at least one upper die 70 can be electrically connected to each pad 111 around the chip area 1a on the second surface 72 of each upper die 70 through each fourth conductive line 110 (formed by RDL technology) for external electrical connection, thereby forming the fan-out wafer-level package unit 1, as Figure 17 shown. That is, in the state where each conductive line in the RDL generates XY-plane electrical extension and interconnection effects, it can also enable the fan-out wafer-level package unit in a multi-chip form to maintain or achieve a certain degree of thin, light, short, and small integration effect, so as to provide a product with higher performance (such as the at least one lower die 20 and the at least one upper die 70 are all dies with the same specifications, performance, or intended functions) or more functions (such as the at least one lower die 20 and the at least one upper die 70 are all dies with different specifications, performance, or intended functions), increasing the market competitiveness of the product.
[0074] (4) The fan-out wafer-level package unit 1 of the present utility model can be electrically connected and disposed on an electronic component 2 by using each solder ball 140, such as by flip-chip technology to cover the fan-out wafer-level package unit 1 on the electronic component 2, as Figure 1 shown, to increase more diversified applications of the product, which is beneficial to increasing the market competitiveness of the product.
[0075] (5) The fan-out chip package unit 1 of the present utility model can use wire bonding operations to form solder joints on each bump 150 and on an electronic component 2 respectively and be electrically connected through a bonding wire 3, as Figure 2 shown, to increase more diversified applications of the product, which is beneficial to increasing the market competitiveness of the product.
[0076] The above are only the preferred embodiments of the present utility model, which are illustrative rather than restrictive to the present utility model; those of ordinary skill in the art understand that many changes, modifications, and even equivalent changes can be made to it within the spirit and scope defined by the claims of the present utility model, but all will fall within the protection scope of the present utility model.
Claims
1. A fan-out wafer-level packaging unit, characterized in that: Include: A carrier having a first surface; At least one lower layer bare die, each of which is split from at least one wafer, each of which has a first surface and an opposite second surface, and each of which has a plurality of pads on the second surface; wherein the first surface of the lower layer bare die located at the bottom of each of the lower layer bare die is fixedly disposed on the first surface of the carrier; A first dielectric layer, the first dielectric layer correspondingly covers each of the lower-layer bare die, the first dielectric layer having a plurality of first grooves extending in a horizontal direction; wherein each of the pads of each of the lower-layer bare die is electrically connected to the outside through the plurality of first grooves; At least one first conducting circuit, each of the first conducting circuits is formed by metal paste filled in each of the first grooves; wherein each of the first conducting circuits is electrically connected to each of the die pads of each of the lower-layer bare die; A second dielectric layer, the second dielectric layer correspondingly covers each of the lower bare chips and is disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves extending in a horizontal direction; wherein each of the second grooves is connected to each of the first grooves; At least one second conducting circuit, each of the second conducting circuits is formed by metal paste filled in each of the second grooves; wherein each of the second conducting circuits is electrically connected to each of the first conducting circuits; At least one upper die, each of which is split from at least one wafer, each of which has a first surface and an opposite second surface, each of which has a plurality of pads on the second surface, and a vertical chip region of the second surface of each of which is defined as a chip region; wherein the first surface of the lowermost upper die in each of which is fixedly disposed on the second dielectric layer; A third dielectric layer, the third dielectric layer correspondingly covers each of the upper bare die, the third dielectric layer having a plurality of third grooves extending in a horizontal direction; wherein each of the die pads of each of the upper bare die is electrically connected to the outside through the plurality of third grooves; At least one third conducting circuit, each of the third conducting circuits is formed by metal paste filled in each of the third grooves; wherein each of the third conducting circuits is electrically connected to each of the second conducting circuits; a fourth dielectric layer, the fourth dielectric layer correspondingly covering each of the upper bare chips and covering the third dielectric layer, the fourth dielectric layer having a plurality of fourth grooves extending in a horizontal direction; wherein each of the fourth grooves is connected to each of the third grooves; at least one fourth conducting circuit, each of the fourth conducting circuits being formed by metal paste filled in each of the fourth grooves; wherein each of the fourth conducting circuits is electrically connected to the third conducting circuit, or is electrically connected to each of the die pads of each of the upper bare die; and an outer protective layer, which is disposed on the fourth dielectric layer, the outer protective layer having a plurality of openings, and at least one of the openings is located around the chip region on the second surface of each of the lower die and around the chip region on the second surface of each of the upper die; Each of the fourth conducting lines is exposed to the outside through each of the openings and a welding pad is formed in each of the openings; The at least one lower layer bare die and the at least one upper layer bare die form a corresponding relationship and are stacked on the carrier at intervals; The at least one lower-layer bare die can be electrically connected to the at least one upper-layer bare die in sequence through each of the first conductive circuits, each of the second conductive circuits, each of the third conductive circuits, and each of the fourth conductive circuits; the at least one lower-layer bare die can be electrically connected to each of the bonding pads around the chip area on the second surface of each of the upper-layer bare die in sequence through each of the first conductive circuits, each of the second conductive circuits, each of the third conductive circuits, and each of the fourth conductive circuits; the at least one upper-layer bare die can be electrically connected to each of the bonding pads around the chip area on the second surface of each of the upper-layer bare die in sequence through each of the fourth conductive circuits, thereby forming the fan-out wafer-level packaging unit.
2. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The vertical chip area on the second surface of the at least one lower-layer bare crystal is defined as a chip area; wherein the at least one lower-layer bare crystal can be electrically connected to the outside via each of the first conductive circuits, each of the second conductive circuits, each of the third conductive circuits, each of the fourth conductive circuits and each of the bonding pads located around the chip area on the second surface of each of the lower-layer bare crystals in sequence.
3. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The at least one lower bare die and the at least one upper bare die are formed by being separated from the same wafer or different wafers.
4. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The carrier includes a silicon carrier, a glass carrier or a ceramic carrier.
5. The fan-out wafer level packaging unit according to claim 1, characterized in that: The metal paste constituting each of the first conducting circuits, each of the second conducting circuits, each of the third conducting circuits and each of the fourth conducting circuits includes silver paste, nano silver paste, copper paste or nano copper paste.
6. The fan-out wafer level packaging unit according to claim 1, characterized in that: The first surface of the at least one lower layer bare die is disposed on the carrier by using a chip bonding film; wherein the first surface of the at least one lower layer bare die is disposed on the second dielectric layer by using a chip bonding film.
7. The fan-out wafer level packaging unit according to claim 1, characterized in that: A solder ball is also disposed on each of the openings, and each of the solder balls can be electrically connected to each of the pads in each of the openings; wherein the fan-out wafer-level packaging unit can be electrically connected to an electronic component by utilizing each of the solder balls.
8. The fan-out wafer-level packaging unit according to claim 1, characterized in that: Each of the openings is also provided with a bump, and each of the bumps can be electrically connected to each of the pads in each of the openings; wherein the fan-out chip packaging unit can utilize wire bonding operations to form solder joints on each of the bumps and an electronic component respectively and electrically connect them through a solder wire.