Oscillator circuit, chip, and electronic device
By designing an oscillator circuit including even N inverters, using the coupling relationship between the output and input terminal of the inverter, combining the connection method of the first resistor and the first capacitor, and setting a bias voltage supply terminal, the problem that the ring oscillator circuit in the prior art cannot adjust the duty cycle, and the duty cycle adjustability after the structure is fixed is achieved.
Patent Information
- Application Number
- CN202421642734.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-11
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-07-11
AI Technical Summary
The existing ring oscillator circuit cannot adjust the duty cycle after the structure is fixed, limiting its application in electronic systems.
By designing an oscillator circuit including even N inverters, the coupling relationship between the output and input of the inverter is used to combine the connection mode of the first resistor and the first capacitor, and a bias voltage supply terminal is provided to achieve the adjustment of the duty cycle.
With the fixed circuit structure of the ring oscillator, the duty cycle is adjustable, and the flexibility and adaptability of the circuit are improved.
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Figure CN222928372U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of electronic technologies, and more particularly, to an oscillator circuit, a chip, and an electronic device. Background Art
[0002] Oscillators are widely used in electronic systems to provide clock signals and are commonly used high-precision clock references in electronic systems. For example, a ring oscillator is usually used as a key component in the clock and data recovery unit of a radio frequency circuit. The structure of a ring oscillator in related technologies usually consists of an odd number of inverters connected end to end in a "ring" in sequence. When the circuit structure is fixed, the duty cycle cannot be adjusted.
[0003] As described above, how to provide an oscillator circuit with an adjustable duty cycle has become an urgent problem to be solved.
[0004] The above information disclosed in the background art section is only used to enhance the understanding of the background of the present disclosure, and thus it may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention
[0005] The purpose of the present disclosure is to provide an oscillator circuit, a chip, and an electronic device, which can achieve an adjustable duty cycle after the circuit structure is fixed.
[0006] Other features and advantages of the present disclosure will become apparent through the following detailed description, or will be learned in part through the practice of the present disclosure.
[0007] According to an aspect of the present disclosure, an oscillator circuit is provided, including: N inverters, at least one bias voltage supply terminal, a first resistor, and a first capacitor, where N is an even number greater than 1, and: the output terminal of the nth inverter among the N inverters is coupled to the input terminal of the (n + 1)th inverter, the input terminal of the first inverter is coupled to the output terminal of the Nth inverter, the output terminal of the Nth inverter is coupled to the output terminal of the oscillator circuit, and n is a positive integer greater than or equal to 1 and less than N; the bias voltage supply terminal is coupled to the input terminal of at least one inverter; the output terminal of the first inverter among the N inverters is coupled to the input terminal of the (N / 2 + 1)th inverter through the first resistor, and the output terminal of the (N / 2)th inverter is coupled to the input terminal of the (N / 2 + 1)th inverter through the first capacitor.
[0008] According to an embodiment of the present disclosure, the number of the bias voltage supply terminals is N, and: the nth bias voltage supply terminal among the N bias voltage supply terminals is coupled to the input terminal of the nth inverter, and the Nth bias voltage supply terminal is coupled to the input terminal of the Nth inverter.
[0009] According to an embodiment of the present disclosure, any one of the N inverters includes a PMOS transistor, an NMOS transistor, and a capacitor unit. The drain of the PMOS transistor is coupled to the drain of the NMOS transistor, and the gates of the PMOS transistor and the NMOS transistor are coupled to the input terminal of the inverter where they are located through the capacitor unit.
[0010] According to an embodiment of the present disclosure, the capacitor unit includes two identical capacitors, and the gates of the PMOS transistor and the NMOS transistor are respectively coupled to the input terminal of the inverter where they are located through one capacitor of the capacitor unit.
[0011] According to an embodiment of the present disclosure, the oscillator circuit further includes a resistor unit, and the gates of the PMOS transistor and the NMOS transistor of at least one inverter are coupled to the bias voltage providing terminal through the resistor unit.
[0012] According to an embodiment of the present disclosure, the resistor unit includes two identical resistors, and the gates of the PMOS transistor and the NMOS transistor of at least one inverter are respectively coupled to the bias voltage providing terminal through one resistor of the resistor unit.
[0013] According to an embodiment of the present disclosure, the oscillator circuit further includes 2N resistors, and the gates of the PMOS transistor and the NMOS transistor of each of the N inverters are respectively coupled to the corresponding bias voltage providing terminal through one resistor.
[0014] According to an embodiment of the present disclosure, the bias voltage provided by the bias voltage providing terminal is configured according to the power supply voltage.
[0015] According to an embodiment of the present disclosure, the bias voltage provided by the bias voltage providing terminal is configured according to the power supply voltage multiplied by a preset ratio, and the preset ratio is between 0.4 and 0.6.
[0016] According to an embodiment of the present disclosure, N is not less than 8.
[0017] According to an embodiment of the present disclosure, the output terminal of the Nth inverter is coupled to the output terminal of the oscillator circuit through at least one inverter.
[0018] According to another aspect of the present disclosure, there is provided a chip including any one of the oscillator circuits as described above.
[0019] According to another aspect of the present disclosure, there is provided an electronic device including the chip as described above.
[0020] The oscillator circuit provided by the embodiments of the present disclosure realizes adjustable duty cycle when the structure of the ring oscillator circuit is fixed by coupling the output terminal of the n-th inverter among an even number N of inverters to the input terminal of the (n + 1)-th inverter, coupling the input terminal of the first inverter to the output terminal of the N-th inverter, coupling the output terminal of the N-th inverter to the output terminal of the oscillator circuit, coupling the output terminal of the first inverter among the N inverters to the input terminal of the (N / 2 + 1)-th inverter through a first resistor, coupling the output terminal of the (N / 2)-th inverter to the input terminal of the (N / 2 + 1)-th inverter through a first capacitor, and providing at least one bias voltage terminal coupled to the input terminal of at least one inverter.
[0021] It should be understood that the above general description and the following detailed description are exemplary only and do not limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The above and other objects, features and advantages of the present disclosure will become more apparent by referring to the accompanying drawings and describing its exemplary embodiments in detail.
[0023] Figure 1 is a schematic diagram of an oscillator circuit shown according to an exemplary embodiment.
[0024] Figure 2 is another schematic diagram of an oscillator circuit shown according to an exemplary embodiment.
[0025] Figure 3 Exemplarily shows a schematic diagram of an inverter that can be applied to the oscillator circuit in the embodiments of the present disclosure.
[0026] Figure 4 According to Figure 3 Shows an example of an inverter in which the capacitor unit includes two capacitors.
[0027] Figure 5 Exemplarily shows another schematic diagram of an inverter that can be applied to the oscillator circuit in the embodiments of the present disclosure.
[0028] Figure 6 According to Figure 5 Shows an example of an inverter in which the resistor unit includes two resistors.
[0029] Figure 7 is according to Figures 1 to 6 Shows an example of an oscillator circuit. DETAILED DESCRIPTION
[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures denote the same or similar parts, and thus repeated descriptions thereof will be omitted.
[0031] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will recognize that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, devices, steps, etc. may be employed. In other cases, well-known structures, methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.
[0032] Furthermore, terms such as "first", "second", etc. are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. The symbol " / " generally indicates that the related objects before and after are in an "or" relationship.
[0033] In the present disclosure, unless otherwise clearly defined and limited, terms such as "connection" should be understood in a broad sense. For example, it may be an electrical connection or may communicate with each other; it may be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.
[0034] In the related art, the structure of a ring oscillator usually consists of an odd number of inverters connected end to end in sequence to form a "ring". By controlling the inverter current with an input voltage, the frequency of the output square wave can be adjusted, but the duty cycle cannot be changed.
[0035] Therefore, the present disclosure provides an oscillator circuit. By coupling the output terminal of the n-th inverter among an even number N of inverters to the input terminal of the (n + 1)-th inverter, coupling the input terminal of the first inverter to the output terminal of the N-th inverter, and coupling the output terminal of the N-th inverter to the output terminal of the oscillator circuit, coupling the output terminal of the first inverter among the N inverters to the input terminal of the (N / 2 + 1)-th inverter through a first resistor, coupling the output terminal of the (N / 2)-th inverter to the input terminal of the (N / 2 + 1)-th inverter through a first capacitor, and providing at least one bias voltage supply terminal coupled to the input terminal of at least one inverter, it is possible to achieve an adjustable duty cycle while the structure of the ring oscillator circuit remains fixed.
[0036] Figure 1 is a schematic diagram of an oscillator circuit shown according to an exemplary embodiment. As Figure 1 shown, the oscillator circuit may include N (N is an even number greater than 1) inverters and at least one bias voltage V CM supply terminal, a first resistor R1, and a first capacitor C1.
[0037] Referring to Figure 1 , the output terminal on of the n-th (n is a positive integer greater than or equal to 1 and less than N) inverter among the N inverters is coupled to the input terminal in+1 of the (n + 1)-th inverter, the input terminal i1 of the first inverter is coupled to the output terminal oN of the N-th inverter, and the output terminal of the N-th inverter is coupled to the output terminal of the oscillator circuit, that is, the N inverters are connected end to end in sequence to form a "ring" shape.
[0038] In some embodiments, N is not less than 8. For example, N may be 8, 10, 12, 16, etc. Figure 7 shows an exemplary embodiment where N is 8.
[0039] In some embodiments, as Figure 1 shown, each of the N inverters may be composed of an up - pulling PMOS device and a down - pulling NMOS device.
[0040] In other embodiments, the inverters among the N inverters may be high - frequency filtering inverters, where one PMOS device and one NMOS device are respectively coupled to the input terminal through a capacitor unit. The specific implementation may refer to Figure 3 .
[0041] As Figure 1As shown, the output terminal of the first inverter among the N inverters is coupled to the input terminal of the (N / 2 + 1)-th inverter through a first resistor, and the output terminal of the N / 2-th inverter is coupled to the input terminal of the (N / 2 + 1)-th inverter through a first capacitor. The first resistor and the first capacitor are used to control the inverter current through the input voltage, thereby adjusting the frequency of the square wave output by the oscillator circuit.
[0042] Bias voltage V CM The supply terminal is coupled to the input terminal of at least one inverter. For example, Figure 1 exemplarily, the bias voltage V is coupled to the input terminal i1 of the first inverter and the input terminal iN / 2 of the N / 2-th inverter. CM Supply terminal. Figure 2 Exemplarily shown is the coupling of the bias voltage V supply terminal to the input terminals of each inverter among the N inverters. CM Example of the supply terminal.
[0043] In some embodiments, the bias voltage V provided by the bias voltage supply terminal CM can be configured according to the power supply voltage. For example, the bias voltage V provided by the bias voltage supply terminal CM can be configured by multiplying the power supply voltage by a preset ratio, and the preset ratio is between 0.4 and 0.6. For example, when the power supply voltage is 1.6V, the bias voltage V CM can be half of the power supply voltage, i.e., 0.8V.
[0044] In some embodiments, the output terminal of the N-th inverter can be coupled to the output terminal of the oscillator circuit through at least one inverter for pulse shaping. Figure 7 Exemplarily shown is that the output of the N-th inverter is coupled to the output terminal of the oscillator circuit through two inverters.
[0045] According to the oscillator circuit provided by the embodiments of the present disclosure, by coupling the output terminal of the n-th inverter among the even N inverters to the input terminal of the (n + 1)-th inverter, the input terminal of the first inverter to the output terminal of the N-th inverter, and the output terminal of the N-th inverter to the output terminal of the oscillator circuit, coupling the output terminal of the first inverter among the N inverters to the input terminal of the (N / 2 + 1)-th inverter through a first resistor, coupling the output terminal of the N / 2-th inverter to the input terminal of the (N / 2 + 1)-th inverter through a first capacitor, and providing at least one bias voltage supply terminal coupled to the input terminal of at least one inverter, by adjusting the magnitude of the bias voltage provided by the bias voltage supply terminal, the duty cycle can be adjusted while the structure of the ring oscillator circuit is fixed.
[0046] In the related art, the ring oscillator still has disadvantages such as high power consumption, large frequency variation, and being easily affected by process, voltage, and temperature. According to the oscillator circuit provided by the embodiments of the present disclosure, by reasonably setting the sizes of the first capacitor and the first resistor, the switching frequency can be reduced, thereby reducing the power consumption of the circuit.
[0047] Figure 2 It is a schematic diagram of another oscillator circuit shown according to an exemplary embodiment. Figure 2 Differing from Figure 1 is that a bias voltage V CM providing terminal is coupled to the input terminal of each of the N inverters, that is, the bias voltage V CM providing terminal is coupled to the input terminal in of the nth inverter.
[0048] Figure 3 An exemplary schematic diagram of an inverter applicable to the oscillator circuit in the embodiments of the present disclosure is shown. Figure 3 The inverter in Figure 1 and Figure 2 can be any one of the inverters in Figure 3 and Figure 1 , 2 for example, the nth inverter. The difference between the inverter in
[0049] and the nth inverter in Figure 4 According to Figure 3 Figure 4 shows an example of an inverter in which the capacitor unit includes two capacitors. As Figure 3 shown, the capacitor unit 302 (refer to ) can include two identical capacitors Cn1 and Cn2. The gate of the PMOS transistor Pn is coupled to the input terminal in of its corresponding inverter through the capacitor Cn1, and the gate of the NMOS transistor Nn is coupled to the input terminal in of its corresponding inverter through the capacitor Cn2 respectively.
[0050] For the inverter in the oscillator circuit provided by the embodiments of the present disclosure, by coupling the gates of the PMOS and NMOS in the inverter to the input terminal through a capacitor respectively, the small-signal noise is amplified through the PMOS and NMOS, realizing a high-pass filter inverter structure.
[0051] In some embodiments, the bias voltage V CM providing terminal can be coupled to the gates of the PMOS transistor and the NMOS transistor of the inverter through a resistor unit.Figure 5 Schematic diagram exemplarily showing another inverter applicable to the oscillator circuit in the embodiments of the present disclosure. Figure 5 The inverter in can be Figure 1 and Figure 2 any one of the inverters in, for example, the nth inverter. Figure 5 The difference between the inverter in and Figure 1 , 2 the nth inverter in is that, in addition to including PMOS transistor Pn and NMOS transistor Nn, it further includes a resistor unit 502, and the gates of PMOS transistor Pn and NMOS transistor Nn are coupled to the bias voltage V CM supply terminal through the resistor unit 502.
[0052] In some embodiments, the resistor unit may include at least one resistor. Figure 6 According to Figure 5 shows an example of an inverter in which the resistor unit includes two resistors. As Figure 6 shown, the resistor unit 502 (refer to Figure 5 ) may include resistor Rn1 and resistor Rn2, and the gate of PMOS transistor Pn of the nth inverter is coupled to the bias voltage V CM supply terminal through resistor Rn1, and the gate of NMOS transistor Nn is coupled to the bias voltage V CM supply terminal through resistor Rn2. Resistor Rn1 and resistor Rn2 may be two identical resistors or different resistors, and the magnitudes of the resistors can be set as required.
[0053] In some embodiments, when the input terminals of N inverters in the oscillator circuit are all coupled to the bias voltage supply terminal, the oscillator circuit may further include 2N resistors, and the gates of the PMOS transistors and the gates of the NMOS transistors of each inverter among the N inverters are respectively coupled to the corresponding bias voltage supply terminal through a resistor.
[0054] For the inverter in the oscillator circuit provided by the embodiments of the present disclosure, by arranging a resistor unit between the gates of the PMOS transistor and the NMOS transistor of the inverter whose input terminal is coupled to the bias voltage supply terminal and the bias voltage supply terminal, the common-mode voltages of the gates of the input PMOS transistor and the NMOS transistor can be balanced, and the adjustment accuracy of the duty cycle can be improved.
[0055] Figure 7 is an example of an oscillator circuit according to Figures 1 to 6 shown. In Figure 7 , N = 8 high-frequency filtering inverters are arranged in series end to end in a "ring" shape. As Figure 7As shown, the PMOS and NMOS gates of each of the eight inverters are each capacitively coupled to the input terminal and connected as a high-pass filter structure. Taking the nth inverter as an example, the gate of the PMOS transistor Pn is capacitively coupled to the input terminal in of the inverter where it is located through a capacitor Cn1, and the gates of the NMOS transistors Nn are each capacitively coupled to the input terminal in of the inverter where they are located through a capacitor Cn2. The PMOS and NMOS gates of each inverter are each connected to a bias voltage V through a resistor. CM A supply terminal provides a common-mode bias and can adjust the duty cycle of the clock. Still taking the nth inverter as an example, the gate of the PMOS transistor Pn is coupled to the bias voltage V through a resistor Rn1. CM A supply terminal, and the gate of the NMOS transistor Nn is coupled to the bias voltage V through a resistor Rn2. CM A supply terminal. For example, when the power supply voltage Vdd is 1.6V, the bias voltage V CM can be half of the power supply voltage, 0.8V. In this case, the duty cycle of the oscillator circuit is 50%.
[0056] Referring to Figure 7 , the oscillator circuit consists of eight high-frequency filtering inverters connected end to end. A capacitor C1 is connected between the output terminal o4 of the fourth high-frequency filtering inverter and the input terminal i5 of the fifth high-frequency filtering inverter. A resistor R1 is connected between the output terminal o1 of the first high-frequency filtering inverter and the input terminal i5 of the fifth high-frequency filtering inverter to provide a low-frequency path. Two ordinary inverters 702 are connected to the output of the eighth high-frequency filtering inverter and then the Clock signal is output for pulse shaping. Each stage of the high-frequency filtering inverter provides a 180° phase shift. The first high-frequency filtering inverter, the resistor R1, and the fifth to eighth high-frequency filtering inverters form a low-frequency path, and the loop has a total of five inversions. The capacitor C1 can provide a maximum phase shift of 90°. The high-frequency path consists of eight stages of high-frequency filtering inverters and the capacitor C1. The initial bias voltage V CM can make each output node be at the intermediate potential, and after introducing a little noise, it starts to oscillate gradually.
[0057] As another aspect, the present disclosure also provides a chip including the oscillator circuit of any one of the above. The chip can be, for example, a microcontroller unit (MCU), a central processing unit (CPU), or a system on chip (SoC) and other chips. The chip 20 can be installed on a printed circuit board (PCB).
[0058] As another aspect, the present disclosure also provides an electronic device including the above chip. The electronic device may include a device body, and the above chip may be disposed within the device body. The electronic device may be, but is not limited to, a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless earphone, a car center console screen, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, a cervical massager. The mobile terminal includes, but is not limited to, a smart phone, a laptop computer, a tablet computer, a POS (Point Of Sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, a smart light.
[0059] The exemplary embodiments of the present disclosure have been specifically shown and described above. It should be understood that the present disclosure is not limited to the detailed structures, arrangements or implementation methods described herein; on the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims
1. An oscillator circuit, characterized in that: The invention comprises N inverters and at least one bias voltage supply terminal, a first resistor and a first capacitor, wherein N is an even number greater than 1, wherein: The output terminal of the nth inverter among the N inverters is coupled to the input terminal of the n+1th inverter, the input terminal of the 1st inverter is coupled to the output terminal of the Nth inverter, the output terminal of the Nth inverter is coupled to the output terminal of the oscillator circuit, and n is a positive integer greater than or equal to 1 and less than N; The bias voltage supply terminal is coupled to the input terminal of at least one inverter; The output end of the 1st inverter among the N inverters is coupled to the input end of the N / 2+1th inverter through the first resistor, and the output end of the N / 2th inverter is coupled to the input end of the N / 2+1th inverter through the first capacitor.
2. The oscillator circuit according to claim 1, characterized in that The number of the bias voltage supply terminals is N, where: The nth bias voltage supply terminal among the N bias voltage supply terminals is coupled to the input terminal of the nth inverter, and the Nth bias voltage supply terminal is coupled to the input terminal of the Nth inverter.
3. The oscillator circuit according to claim 1 or 2, characterized in that: Any one of the N inverters includes a PMOS tube, an NMOS tube and a capacitor unit, the drain of the PMOS tube is coupled to the drain of the NMOS tube, and the gate of the PMOS tube and the gate of the NMOS tube are coupled to the input end of the inverter where they are located through the capacitor unit.
4. The oscillator circuit according to claim 3, characterized in that The capacitor unit includes two identical capacitors, and the gate of the PMOS tube and the gate of the NMOS tube are each coupled to the input end of the inverter where they are located through a capacitor of the capacitor unit.
5. The oscillator circuit according to claim 1, characterized in that It also includes a resistance unit, through which the gate of the PMOS tube and the gate of the NMOS tube of the at least one inverter are coupled to the bias voltage supply terminal.
6. The oscillator circuit according to claim 5, characterized in that The resistance unit includes two identical resistors, and the gate of the PMOS tube and the gate of the NMOS tube of the at least one inverter are each coupled to the bias voltage supply terminal through a resistor of the resistance unit.
7. The oscillator circuit according to claim 2, characterized in that It also includes 2N resistors, and the gate of the PMOS tube and the gate of the NMOS tube of each inverter in the N inverters are each coupled to the corresponding bias voltage supply terminal through a resistor.
8. The oscillator circuit according to claim 1 or 2, characterized in that: The bias voltage provided by the bias voltage providing terminal is configured according to the power supply voltage.
9. The oscillator circuit according to claim 8, characterized in that The bias voltage provided by the bias voltage providing end is configured by multiplying the power supply voltage by a preset ratio, and the preset ratio is between 0.4 and 0.
6.
10. The oscillator circuit according to claim 1 or 2, characterized in that: N is not less than 8.
11. The oscillator circuit according to claim 1 or 2, characterized in that: The output terminal of the Nth inverter is coupled to the output terminal of the oscillator circuit through at least one inverter.
12. A chip, characterized in that: Comprising an oscillator circuit according to any one of claims 1 to 11.
13. An electronic device, characterized in that: Comprising the chip according to claim 12.