Digital signal synchronization device, power module and new energy product

Abstract

The utility model discloses a digital signal synchronization device, a power module and a new energy product. The digital signal synchronization device comprises a first high-voltage isolation optocoupler, a second high-voltage isolation optocoupler, an isolation conversion chip and a common-mode interference resistance circuit. When the host sends a host step signal, a first differential signal and a second differential signal which are synchronous are formed between the first output end and the second output end of the anti-common-mode interference circuit and are transmitted to the slave through the bus, and the slave receives the first differential signal and the second differential signal at the moment and generates a synchronous slave step signal; and the slave computer adjusts the own signal to be consistent with the host computer through the slave computer step signal so as to realize synchronization. According to the utility model, the consistency of module signals can be ensured, high frequency and power frequency of a plurality of power modules are synchronized, high-frequency ring current and low-frequency ring current are eliminated, the power module can still work normally in a complex environment, efficient and stable operation of new energy products is facilitated, and the power module has the advantages of being low in delay, strong in anti-interference capability, universal for master and slave machines, simple in wiring and the like.

Description

Technical Field

[0001] The utility model relates to the field of signal processing, and particularly relates to a digital signal synchronization device, a power module and a new energy product. Background Art

[0002] In order to cope with global climate change and promote green and low-carbon development, new energy products have been vigorously laid out everywhere. Modularization of new energy products can improve the flexibility of power configuration. When a certain module fails, it can be replaced in time without affecting the system operation. The modular design can also reduce the pressure on individual power devices. In short, modularization of new energy products is the most commonly used method at present.

[0003] During the implementation of the digital signal synchronization device, power module and new energy product in the embodiments of the present utility model by the inventors of this patent, at least the following technical problems in the prior art are found:

[0004] The power module mainly consists of power switching tubes and high-frequency components. As Figure 1 shown, when multiple power modules operate in parallel with load, high-frequency circulating current will occur between modules when the on or off signals of switching devices are asynchronous, and low-frequency circulating current will occur when the output power-frequency AC voltage or current is asynchronous. Specifically, the digital control chip controls the on and off of the switching tubes. When the high-frequency switching tubes between power modules act asynchronously, high-frequency circulating current will be generated between power modules. The high-frequency circulating current will generate additional losses between power modules, causing the power switching tubes to heat up. Seriously, it may even damage the switching tubes, resulting in module downtime. When the power module is of AC type, the asynchrony of AC signals will generate low-frequency circulating current between modules, increasing the operating current of the modules, which is not conducive to the long-term stable operation of the product.

[0005] In summary, circulating current will be generated between existing power modules, affecting the long-term stable operation of new energy products. Summary of the Utility Model

[0006] The embodiments of the present utility model provide a digital signal synchronization device, a power module and a new energy product, which solve the problem that circulating current will be generated between existing power modules, affecting the long-term stable operation of new energy products. When multiple power modules operate in parallel, through the digital signal synchronization device provided by the present utility model, the consistency of module signals can be ensured, the occurrence of circulating current can be avoided, and it is beneficial to the efficient and stable operation of new energy products.

[0007] One aspect of the embodiments of the present utility model provides a digital signal synchronization device, including:

[0008] A first high-voltage isolation optocoupler, whose third pin receives the host step signal;

[0009] The second high-voltage isolation optocoupler, whose sixth pin transmits the slave step signal;

[0010] The isolation conversion chip, whose first pin is electrically connected to the sixth pin of the first high-voltage isolation optocoupler, and whose fourth pin is electrically connected to the third pin of the second high-voltage isolation optocoupler;

[0011] The common-mode interference rejection circuit, whose first input terminal is electrically connected to the seventh pin of the isolation conversion chip, whose second input terminal is electrically connected to the sixth pin of the isolation conversion chip, whose first output terminal forms a first differential signal, whose second output terminal forms a second differential signal, and whose first output terminal and second output terminal are electrically connected through a sixth resistor;

[0012] When the host sends a host step signal, a synchronous first differential signal and second differential signal will be formed between the first output terminal and the second output terminal of the common-mode interference rejection circuit and transmitted to the slave through the bus. At this time, the slave receives the first differential signal and the second differential signal, generates a synchronous slave step signal, and the slave adjusts its own signal to be consistent with the host through the slave step signal to achieve synchronization.

[0013] Optionally, the common-mode interference rejection circuit specifically includes: an LC filter circuit and a synchronous signal bus surge protection circuit.

[0014] Optionally, the LC filter circuit specifically includes:

[0015] The common-mode filter inductor, whose first end is electrically connected to the seventh pin of the isolation conversion chip, whose second end is electrically connected to the sixth pin of the isolation conversion chip, whose third end forms a second differential signal, and whose fourth end forms a first differential signal;

[0016] The third capacitor, whose first end is electrically connected to the first end of the common-mode filter inductor, and whose second end is electrically connected to the common ground terminal;

[0017] The fourth capacitor, whose first end is electrically connected to the second end of the common-mode filter inductor, and whose second end is electrically connected to the common ground terminal.

[0018] Optionally, the synchronous signal bus surge protection circuit specifically includes:

[0019] The first diode, whose first end is electrically connected to the seventh pin of the isolation conversion chip;

[0020] The second diode, whose first end is electrically connected to the sixth pin of the isolation conversion chip;

[0021] The third diode, whose first end is electrically connected to the common ground terminal, and whose second end is electrically connected to the seventh pin of the isolation conversion chip;

[0022] A fourth diode, having its first end electrically connected to a common ground terminal and its second end electrically connected to the sixth pin of the isolation conversion chip;

[0023] An avalanche breakdown diode, having its first end electrically connected to the second ends of the first diode and the second diode and its second end electrically connected to the common ground terminal.

[0024] Optionally, the device further includes:

[0025] A first resistor, having its first end electrically connected to an input voltage and its second end electrically connected to the second pin of the first high-voltage isolation optocoupler;

[0026] A first capacitor, having its first end electrically connected to the eighth pin of the first high-voltage isolation optocoupler and a common terminal voltage and its second end electrically connected to the fifth pin of the first high-voltage isolation optocoupler and the common ground terminal.

[0027] Optionally, the device further includes:

[0028] A seventh resistor, having its first end electrically connected to the common terminal voltage and its second end electrically connected to the second pin of the second high-voltage isolation optocoupler;

[0029] A fifth capacitor, having its first end electrically connected to the input voltage and the eighth pin of the second high-voltage isolation optocoupler and its second end electrically connected to the fifth pin of the second high-voltage isolation optocoupler and the ground.

[0030] Optionally, the device further includes:

[0031] A third resistor, having its first end electrically connected to the common ground terminal and its second end electrically connected to the eighth pin of the isolation conversion chip;

[0032] A fourth resistor, having its first end electrically connected to the seventh pin of the isolation conversion chip and its second end electrically connected to the first input terminal of the common-mode interference rejection circuit;

[0033] A fifth resistor, having its first end electrically connected to the sixth pin of the isolation conversion chip and its second end electrically connected to the second input terminal of the common-mode interference rejection circuit;

[0034] A second capacitor, having its first end electrically connected to the common terminal voltage and the third pin of the isolation conversion chip and its second end electrically connected to the second pin of the isolation conversion chip and the common ground terminal.

[0035] Optionally, the device further includes: a second resistor, having its first end electrically connected to the sixth pin of the first high-voltage isolation optocoupler and its second end electrically connected to the first pin of the isolation conversion chip.

[0036] On the other hand, an embodiment of the present utility model further provides a power module, including: the digital signal synchronization device described in the foregoing embodiment; a power module main body, electrically connected to the digital signal synchronization device.

[0037] In a third aspect, an embodiment of the present utility model further provides a new energy product, including: the power module described in the foregoing embodiment; a product main body, electrically connected to the power module.

[0038] One or more technical solutions provided in the embodiments of the present utility model have at least the following technical effects or advantages:

[0039] Through the digital signal synchronization device provided by the present utility model, the consistency of module signals can be ensured, enabling high-frequency and power-frequency synchronization among multiple power modules, eliminating high-frequency and low-frequency circulating currents, and still working normally in a complex environment, which is beneficial to the efficient and stable operation of new energy products and has the advantages of low delay, strong anti-interference ability, general use of master and slave machines, and simple wiring. Description of the Drawings

[0040] Figure 1 It is a schematic diagram of multiple power modules operating in parallel with load in the background technology;

[0041] Figure 2 It is a circuit schematic diagram of the digital signal synchronization device in an embodiment of the present utility model;

[0042] In the figure:

[0043] SYN_TX, host step signal;

[0044] R33, first resistor;

[0045] U11, first high-voltage isolation optocoupler;

[0046] C35, first capacitor;

[0047] COM_GND, common ground terminal;

[0048] R36, second resistor;

[0049] C36, second capacitor;

[0050] U12, isolation conversion chip;

[0051] R34, third resistor;

[0052] R37, fourth resistor;

[0053] R39, fifth resistor;

[0054] L8, common-mode filter inductor;

[0055] R38, sixth resistor;

[0056] SYN_H, the first differential signal;

[0057] SYN_L, the second differential signal;

[0058] D9, the first diode;

[0059] D10, the second diode;

[0060] D12, the third diode;

[0061] D11, the fourth diode;

[0062] TVS3, the avalanche breakdown diode;

[0063] C37, the third capacitor;

[0064] C38, the fourth capacitor;

[0065] R40, the seventh resistor;

[0066] U13, the second high-voltage isolation optocoupler;

[0067] C39, the fifth capacitor;

[0068] SYN_RX, the slave step signal. Detailed implementation manner

[0069] The embodiment of the present utility model provides a digital signal synchronization device, a power module and a new energy product, which solves the problem that existing power modules will generate circulating current, affecting the long-term stable operation of new energy products. When multiple power modules operate in parallel, through the digital signal synchronization device provided by the present utility model, the consistency of module signals can be ensured, avoiding the occurrence of circulating current, which is beneficial to the efficient and stable operation of new energy products.

[0070] In order to better understand the above digital signal synchronization device, the above digital signal synchronization device will be described in detail below in conjunction with the specification drawings and specific implementation manners. Obviously, the embodiments described in the present utility model are a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.

[0071] (I) Structure of the digital signal synchronization device

[0072] Please refer to Figure 2, a digital signal synchronization device of the present utility model includes: a first high-voltage isolation optocoupler U11, a second high-voltage isolation optocoupler U13, an isolation conversion chip U12, and a common-mode interference rejection circuit. The device further includes: a second resistor R36, whose first end is electrically connected to the sixth pin of the first high-voltage isolation optocoupler U11, and whose second end is electrically connected to the first pin of the isolation conversion chip U12. That is to say, the first high-voltage isolation optocoupler U11 and the isolation conversion chip U12 are electrically connected through the second resistor R36.

[0073] The digital signal synchronization device can both send step signals and receive synchronization signals. Therefore, the host and the slave share the same digital synchronization device. From a hardware perspective, the host and the slave are exactly the same. The synchronization device has a small transmission delay for step synchronization signals and strong anti-interference ability, and still works normally in a complex environment.

[0074] 1) The first high-voltage isolation optocoupler U11

[0075] The third pin of the first high-voltage isolation optocoupler U11 receives the host step signal SYN_TX. The host step signal SYN_TX is the step signal sent by the host. The first high-voltage isolation optocoupler U11 can isolate the power module and the external synchronization signal bus. Since there is often high voltage inside the power module, it plays a safety protection role.

[0076] The device further includes a first resistor R33 and a first capacitor C35. The first end of the first resistor R33 is electrically connected to the input voltage, and its second end is electrically connected to the second pin of the first high-voltage isolation optocoupler U11; the first end of the first capacitor C35 is electrically connected to the eighth pin of the first high-voltage isolation optocoupler U11 and the common terminal voltage, and its second end is electrically connected to the fifth pin of the first high-voltage isolation optocoupler U11 and the common ground terminal COM_GND.

[0077] 2) The second high-voltage isolation optocoupler U13

[0078] The sixth pin of the second high-voltage isolation optocoupler U13 sends the slave step signal SYN_RX. The slave step signal SYN_RX is the step signal received by the slave. The second high-voltage isolation optocoupler U13 can isolate the power module and the external synchronization signal bus. Since there is often high voltage inside the power module, it plays a safety protection role.

[0079] The digital signal synchronization device further includes: a seventh resistor R40 and a fifth capacitor C39. The first end of the seventh resistor R40 is electrically connected to the common terminal voltage, and its second end is electrically connected to the second pin of the second high-voltage isolation optocoupler U13; the first end of the fifth capacitor C39 is electrically connected to the input voltage and the eighth pin of the second high-voltage isolation optocoupler U13, and its second end is electrically connected to the fifth pin of the second high-voltage isolation optocoupler U13 and the ground.

[0080] 3) Isolation conversion chip U12

[0081] The first pin of the isolation conversion chip U12 is electrically connected to the sixth pin of the first high-voltage isolation optocoupler U11, and its fourth pin is electrically connected to the third pin of the second high-voltage isolation optocoupler U13. The isolation conversion chip U12 can convert the host step signal SYN_TX or the slave step signal SYN_RX signal to GND into a first differential signal SYN_H and a second differential signal SYN_L with stronger anti-interference ability.

[0082] The digital signal synchronization device further includes a third resistor R34, a fourth resistor R37, a fifth resistor R39, and a second capacitor C36. The first end of the third resistor R34 is electrically connected to the common ground terminal COM_GND, and its second end is electrically connected to the eighth pin of the isolation conversion chip U12; the first end of the fourth resistor R37 is electrically connected to the seventh pin of the isolation conversion chip U12, and its second end is electrically connected to the first input terminal of the common-mode interference rejection circuit; the first end of the fifth resistor R39 is electrically connected to the sixth pin of the isolation conversion chip U12, and its second end is electrically connected to the second input terminal of the common-mode interference rejection circuit; the first end of the second capacitor C36 is electrically connected to the common terminal voltage and the third pin of the isolation conversion chip U12, and its second end is electrically connected to the second pin of the isolation conversion chip U12 and the common ground terminal COM_GND.

[0083] 4) Common-mode interference rejection circuit

[0084] The first input terminal of the common-mode interference rejection circuit is electrically connected to the seventh pin of the isolation conversion chip U12, its second input terminal is electrically connected to the sixth pin of the isolation conversion chip U12, its first output terminal forms a first differential signal SYN_H, its second output terminal forms a second differential signal SYN_L, and its first output terminal and its second output terminal are electrically connected through a sixth resistor R38. The common-mode interference rejection circuit has a bus surge and short-circuit protection function, and the chip will not be damaged when there is a surge and short-circuit on the bus.

[0085] The common-mode interference rejection circuit specifically includes: an LC filter circuit and a synchronous signal bus surge protection circuit.

[0086] The LC filter circuit includes a common-mode filter inductor L8, a third capacitor C37, and a fourth capacitor C38, and the LC filter circuit further enhances the anti-interference ability of the synchronization device. The common-mode filter inductor L8 is used to suppress the common-mode interference signal between the first differential signal SYN_H and the second differential signal SYN_L. Its first end is electrically connected to the seventh pin of the isolation conversion chip U12, its second end is electrically connected to the sixth pin of the isolation conversion chip U12, its third end forms the second differential signal SYN_L, and its fourth end forms the first differential signal SYN_H. The first end of the third capacitor C37 is electrically connected to the first end of the common-mode filter inductor L8, and its second end is electrically connected to the common ground terminal COM_GND. The first end of the fourth capacitor C38 is electrically connected to the second end of the common-mode filter inductor L8, and its second end is electrically connected to the common ground terminal COM_GND. It should be noted that since the first high-voltage isolation optocoupler U11, the second high-voltage isolation optocoupler U13, and the isolation conversion chip U12 have a very small signal delay, and the capacitance values of the third capacitor C37 and the fourth capacitor C38 are small, in the nF level, the signal delay is very small.

[0087] The surge protection circuit for the synchronization signal bus specifically includes: a first diode D9, a second diode D10, a third diode D12, a fourth diode D11, and an avalanche breakdown diode TVS3. The first end of the first diode D9 is electrically connected to the seventh pin of the isolation conversion chip U12; the first end of the second diode D10 is electrically connected to the sixth pin of the isolation conversion chip U12; the first end of the third diode D12 is electrically connected to the common ground terminal COM_GND, and its second end is electrically connected to the seventh pin of the isolation conversion chip U12; the first end of the fourth diode D11 is electrically connected to the common ground terminal COM_GND, and its second end is electrically connected to the sixth pin of the isolation conversion chip U12; the first end of the avalanche breakdown diode TVS3 is electrically connected to the second ends of the first diode D9 and the second diode D10, and its second end is electrically connected to the common ground terminal COM_GND. When there is a positive surge voltage on the bus, it will form a loop through the first diode D9 or the second diode D10, the avalanche breakdown diode TVS3, and the common ground terminal COM_GND; when there is a negative surge voltage on the bus, the GND will clamp the voltage of the first differential signal SYN_H or the second differential signal SYN_L to the common ground terminal COM_GND through the third diode D12 or the fourth diode D11, both of which can protect the isolation conversion chip U12 and the pre-stage circuit.

[0088] (2) Operating conditions of the digital signal synchronization device

[0089] When the host sends the host step signal SYN_TX, a synchronous first differential signal SYN_H and a second differential signal SYN_L are formed between the first output terminal and the second output terminal of the common-mode interference rejection circuit, and are transmitted to the slave through the bus. At this time, the slave receives the first differential signal SYN_H and the second differential signal SYN_L, generates a synchronous slave step signal SYN_RX, and the slave adjusts its own signal to be consistent with the host through the slave step signal SYN_RX to achieve synchronization.

[0090] An embodiment of the present invention further provides a power module, including: the digital signal synchronization device of the foregoing embodiment; a power module main body, electrically connected to the digital signal synchronization device.

[0091] An embodiment of the present invention further provides a new energy product, including: the power module of the foregoing embodiment; a product main body, electrically connected to the power module.

[0092] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A digital signal synchronization device, characterized in that: include: A first high-voltage isolation optical coupler, a third pin of which receives a host step signal; A second high-voltage isolation optical coupler, whose sixth pin sends a slave step signal; An isolation conversion chip, wherein a first pin of the isolation conversion chip is electrically connected to a sixth pin of the first high-voltage isolation optocoupler, and a fourth pin of the isolation conversion chip is electrically connected to a third pin of the second high-voltage isolation optocoupler; An anti-common mode interference circuit, wherein a first input end thereof is electrically connected to the seventh pin of the isolation conversion chip, a second input end thereof is electrically connected to the sixth pin of the isolation conversion chip, a first output end thereof forms a first differential signal, a second output end thereof forms a second differential signal, and the first output end thereof and the second output end thereof are electrically connected via a sixth resistor; When the host sends a host step signal, a synchronized first differential signal and a second differential signal are formed between the first output terminal and the second output terminal of the anti-common mode interference circuit and transmitted to the slave through the bus. The slave then receives the first differential signal and the second differential signal and generates a synchronized slave step signal. The slave adjusts its own signal to be consistent with the host through the slave step signal to achieve synchronization.

2. The device according to claim 1, characterized in that The anti-common mode interference circuit specifically includes: an LC filter circuit and a synchronous signal bus surge protection circuit.

3. The device according to claim 2, characterized in that The LC filter circuit specifically includes: A common mode filter inductor, wherein a first end of the common mode filter inductor is electrically connected to the seventh pin of the isolation conversion chip, a second end of the common mode filter inductor is electrically connected to the sixth pin of the isolation conversion chip, a third end of the common mode filter inductor forms a second differential signal, and a fourth end of the common mode filter inductor forms a first differential signal; a third capacitor, a first end of which is electrically connected to the first end of the common mode filter inductor, and a second end of which is electrically connected to the common ground terminal; A fourth capacitor has a first end electrically connected to the second end of the common mode filter inductor, and a second end electrically connected to the common ground terminal.

4. The device according to claim 2, characterized in that The synchronous signal bus surge protection circuit specifically includes: A first diode, a first end of which is electrically connected to the seventh pin of the isolation conversion chip; A second diode, a first end of which is electrically connected to the sixth pin of the isolation conversion chip; a third diode, a first end of which is electrically connected to the common ground terminal, and a second end of which is electrically connected to the seventh pin of the isolation conversion chip; a fourth diode, a first end of which is electrically connected to the common ground terminal, and a second end of which is electrically connected to the sixth pin of the isolation conversion chip; An avalanche breakdown diode has a first end electrically connected to the second end of the first diode and the second end of the second diode, and a second end electrically connected to a common ground terminal.

5. The device according to claim 1, characterized in that The device also includes: A first resistor, a first end of which is electrically connected to the input voltage, and a second end of which is electrically connected to the second pin of the first high-voltage isolation optocoupler; A first capacitor has a first end electrically connected to the eighth pin of the first high-voltage isolation optocoupler and a common voltage, and a second end electrically connected to the fifth pin of the first high-voltage isolation optocoupler and a common ground terminal.

6. The device according to claim 1, characterized in that The device also includes: a seventh resistor, a first end of which is electrically connected to the common voltage, and a second end of which is electrically connected to the second pin of the second high-voltage isolation optocoupler; A fifth capacitor has a first end electrically connected to the input voltage and the eighth pin of the second high-voltage isolation optocoupler, and a second end electrically connected to the fifth pin of the second high-voltage isolation optocoupler and the ground.

7. The device according to claim 1, characterized in that The device also includes: a third resistor, a first end of which is electrically connected to the common ground terminal, and a second end of which is electrically connected to the eighth pin of the isolation conversion chip; a fourth resistor, a first end of which is electrically connected to the seventh pin of the isolation conversion chip, and a second end of which is electrically connected to the first input end of the anti-common mode interference circuit; a fifth resistor, a first end of which is electrically connected to the sixth pin of the isolation conversion chip, and a second end of which is electrically connected to the second input end of the anti-common mode interference circuit; A second capacitor has a first end electrically connected to the common voltage and the third pin of the isolation conversion chip, and a second end electrically connected to the second pin of the isolation conversion chip and the common ground terminal.

8. The device according to claim 1, characterized in that The device further includes: a second resistor, a first end of which is electrically connected to the sixth pin of the first high-voltage isolation optocoupler, and a second end of which is electrically connected to the first pin of the isolation conversion chip.

9. A power module, characterized in that: include: The digital signal synchronization device according to any one of claims 1 to 8; The power module body is electrically connected to the digital signal synchronization device.

10. A new energy product, characterized in that: include: The power module according to claim 9; The product body is electrically connected to the power module.

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