In-situ gated memory

Abstract

The embodiment of the utility model provides an in-situ strobe memory. The in-situ strobe memory comprises a substrate; a plurality of storage arrays located on the substrate; the storage array comprises a plurality of in-situ gating units; at least one heat dissipation structure; the heat dissipation structure comprises a first heat dissipation unit and a second heat dissipation unit, wherein the first heat dissipation unit is adjacent to the first side surface of at least one storage array; and / or the second heat dissipation unit is adjacent to the second side surface of at least one storage array.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular, to an in-situ gated memory. Background Art

[0002] With the popularization of artificial intelligence applications, especially the rapid development of fields such as deep learning, natural language processing, and computer vision, the demand for data storage and computing power has increased sharply. The storage device based on the in-situ gating principle uses the method of threshold voltage regulation to achieve the gating-storage function in a single device. It has the advantages of simple structure, high scalability, fast read and write speed, etc., and shows great potential under the background of the development of artificial intelligence and computing-in-memory technology. Especially in application fields such as Compute Express Link (CXL) and High Bandwidth Memory (HBM), it has obvious advantages. How to enhance the stability of new memories and accelerate the development and application of new storage devices is one of the important research directions in the industry. Summary of the Utility Model

[0003] In view of this, the embodiments of the present application provide an in-situ gated memory. The technical solution of the embodiments of the present application is realized as follows:

[0004] The embodiments of the present application provide an in-situ gated memory, including:

[0005] A substrate;

[0006] A plurality of memory arrays located on the substrate; the memory arrays include a plurality of in-situ gated units;

[0007] At least one heat dissipation structure; the heat dissipation structure includes: a first heat dissipation unit adjacent to the first side of at least one of the memory arrays; and / or, a second heat dissipation unit adjacent to the second side of at least one of the memory arrays.

[0008] In some embodiments, the first heat dissipation unit, and / or the second heat dissipation unit includes a grid structure composed of a plurality of first heat dissipation fins arranged at intervals.

[0009] In some embodiments, the first heat dissipation fin is parallel to the first side, or parallel to the second side, or parallel to the surface of the substrate.

[0010] In some embodiments, at least one end of the plurality of first heat dissipation fins arranged at intervals is connected to each other.

[0011] In some embodiments, the first heat dissipation unit, and / or the second heat dissipation unit further includes at least one second heat sink, and the second heat sink is perpendicular to the first heat sink; one of the second heat sinks is used to connect the ends of two of the first heat sinks.

[0012] In some embodiments, the plurality of heat dissipation structures include: one or more rectangular structures; the rectangular structures surround a plurality of memory arrays;

[0013] The rectangular structures are alternately connected end to end by the first heat dissipation unit and the second heat dissipation unit.

[0014] In some embodiments, the plurality of rectangular structures are sequentially surrounded layer by layer.

[0015] In some embodiments, the plurality of memory arrays include a multi-layer structure stacked in a direction perpendicular to the substrate;

[0016] The heat dissipation structure includes a first heat dissipation unit adjacent to a first side of one or more of the memory arrays in at least one layer of the multi-layer structure; and / or, a second heat dissipation unit adjacent to a second side of one or more of the memory arrays in at least one layer of the multi-layer structure.

[0017] In some embodiments, in a direction perpendicular to the second side, the first heat dissipation unit includes a plurality of first sub-heat dissipation units arranged at intervals, and the length of the first sub-heat dissipation unit is less than or equal to the length of the memory array;

[0018] In a direction perpendicular to the first side, the second heat dissipation unit includes a plurality of second sub-heat dissipation units arranged at intervals, and the length of the second sub-heat dissipation unit is less than or equal to the length of the memory array.

[0019] In some embodiments, the in-situ strobing unit includes a first electrode layer, a storage functional layer, and a second electrode layer stacked in sequence in a direction perpendicular to the substrate surface, and the storage functional layer has a bi-directional threshold switching characteristic.

[0020] The in-situ strobing memory provided by the embodiments of the present application can provide more heat dissipation channels through the first heat dissipation unit and the second heat dissipation unit located on different sides of the array structure, which is beneficial to accelerating the heat transfer of the in-situ strobing unit in the memory array and improving the thermal reliability of the in-situ strobing memory. Since the memory array has a high degree of repetition and the heat dissipation structure has no direct electrical coupling with the memory array, the first heat dissipation unit and the second heat dissipation unit are relatively independent, so the positions thereof can be flexibly designed according to different heat dissipation requirements. Description of the Drawings

[0021] Figure 1 Schematic diagram of the structure of the in-situ strobing memory in the embodiments of the present applicationFigure 1 ;

[0022] Figure 2 Schematic cross-section of the in-situ gated memory in the embodiment of the present application Figure 1 ;

[0023] Figure 3 Schematic cross-section of the in-situ gated memory in the embodiment of the present application Figure 2 ;

[0024] Figure 4 Schematic structure of the in-situ gated memory in the embodiment of the present application Figure 2 ;

[0025] Figure 5 Schematic structure of the in-situ gated memory in the embodiment of the present application Figure 3 ;

[0026] Figure 6A Schematic structure of the in-situ gated memory in the embodiment of the present application Figure 4 ;

[0027] Figures 6B - 6C In the embodiment of the present application Figure 6A Schematic cross-sectional view of the in-situ gated memory shown;

[0028] Figure 7 Schematic structure of the in-situ gated memory in the embodiment of the present application Figure 5 ;

[0029] Figure 8 Schematic structure diagram six of the in-situ gated memory in the embodiment of the present application;

[0030] Figure 9 Schematic structure of the in-situ gated memory in the embodiment of the present application Figure 7 ;

[0031] Figure 10A Schematic structure of the in-situ gated memory in the embodiment of the present application Figure 8 ;

[0032] Figures 10B - 10C In the embodiment of the present application Figure 10A Schematic cross-sectional view of the in-situ gated memory shown;

[0033] Figure 11 Top view of the heat dissipation structure of the in-situ gated memory in the embodiment of the present application Figure 1 ;

[0034] Figure 12 Top view of the heat dissipation structure of the in-situ gated memory in the embodiment of the present application Figure 2 ;

[0035] Figure 13ASchematic structure of the in-situ gated memory in the embodiments of the present application Figure 9 ;

[0036] Figure 13B In the embodiments of the present application Figure 13A Cross-sectional schematic diagram of the in-situ gated memory shown

[0037] Figure 14 Schematic diagram ten of the structure of the in-situ gated memory in the embodiments of the present application;

[0038] Figure 15 Top view of the heat dissipation structure of the in-situ gated memory in the embodiments of the present application Figure 3 ;

[0039] Figure 16 Top view of the heat dissipation structure of the in-situ gated memory in the embodiments of the present application Figure 4 ;

[0040] Figure 17 Top view of the heat dissipation structure of the in-situ gated memory in the embodiments of the present application Figure 5 . Detailed implementation manners

[0041] Next, in combination with the embodiments of the present application and the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0042] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. When used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the related listed items.

[0044] To thoroughly understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this application. The preferred embodiments of this application are described in detail below. However, in addition to these detailed descriptions, this application may have other implementation manners.

[0045] In-situ Selector Only Memory (SOM) is a new type of memory technology, which is characterized by using only selector elements to achieve data storage and reading. Compared with dynamic random access memory that realizes storage through a combination of capacitors and transistors, and phase change memory that realizes storage through phase change materials and selectors, SOM devices have higher integration and faster read / write speeds. However, SOM devices generate a large amount of heat, and their materials usually cannot withstand high temperatures, which requires a higher level of heat management for in-situ selector memories.

[0046] An embodiment of this application provides an in-situ selector memory. Refer to Figures 1 - 3 , the in-situ selector memory includes: a substrate 201, a plurality of memory arrays 101 located on the substrate 201, and at least one heat dissipation structure 102;

[0047] The memory array 101 includes a plurality of in-situ selector units;

[0048] The heat dissipation structure 102 includes: a first heat dissipation unit 1021 adjacent to the first side of at least one of the memory arrays; and / or, a second heat dissipation unit 1022 adjacent to the second side of at least one of the memory arrays.

[0049] Continuing to refer to Figure 1 , the memory array 101 has a first side and a second side that are perpendicular to each other. Among them, the first side of the memory array 101 is parallel to the AAˋ cross-section, and the second side of the memory array 101 is parallel to the BBˋ cross-section. Figure 2 And Figure 3 respectively show a partial schematic diagram of the in-situ selector memory along the AAˋ cross-section and a partial schematic diagram along the BBˋ cross-section.

[0050] The heat dissipation structure includes a first heat dissipation unit and / or a second heat dissipation unit. The first heat dissipation unit covers the first side of one memory array; or, the first heat dissipation unit covers the first sides of multiple memory arrays in the same column. The second heat dissipation unit covers the second side of one memory array; or, the second heat dissipation unit covers the second sides of multiple memory arrays in the same row. Adding a heat dissipation structure around the memory array to transfer the heat generated during the operation of the memory from the memory array can reduce the risk of performance degradation of the memory caused by heat generation in the memory array.

[0051] In some embodiments, the heat dissipation structure can exist alone on a certain side of the storage array. Exemplarily, as Figure 4 shown, the heat dissipation structure includes a first heat dissipation unit 1021 adjacent to the first side of the storage array 101. The first heat dissipation unit 1021 covers the first sides of two adjacent storage arrays 101. A dielectric material layer 401 can be provided between two adjacent storage arrays front and back. In another embodiment, as Figure 5 shown, the heat dissipation structure includes a second heat dissipation unit 1022 adjacent to the second side of the storage array 101. The second heat dissipation unit 1022 covers the second sides of two adjacent storage arrays 101. A dielectric material layer 401 can be provided between two adjacent storage arrays 101 on the left and right. In another embodiment, continuing to refer to Figure 1 , the heat dissipation structure 102 can exist on different sides of the storage array 101 at the same time. The heat dissipation structure 102 includes a first heat dissipation unit 1021 adjacent to the first side of the storage array and a second heat dissipation unit 1022 adjacent to the second side of the storage array.

[0052] The in-situ strobing memory provided by the embodiments of the present application can provide more heat dissipation channels through the first heat dissipation unit and the second heat dissipation unit located on different sides of the array structure, which is beneficial to accelerating the heat transfer of the in-situ strobing unit in the storage array and improving the thermal reliability of the in-situ strobing memory. Since the storage array has high repeatability and the heat dissipation structure has no direct electrical coupling with the storage array, the first heat dissipation unit and the second heat dissipation unit are relatively independent and can be flexibly designed according to different heat dissipation requirements. In addition, the in-situ strobing memory can be improved based on the existing storage architecture, utilize the peripheral area of the storage array, and select materials commonly used in semiconductor processes, with low requirements for process development, high process compatibility, and can be applied to different storage architectures. It should be emphasized that the heat dissipation structure is located inside the packaging structure, and the preparation process of the heat dissipation structure is part of the preparation of the storage array.

[0053] In some embodiments, the in-situ strobing unit includes a first electrode layer, a storage functional layer, and a second electrode layer stacked in sequence along a direction perpendicular to the surface of the substrate, and the storage functional layer has a bi-directional threshold switching characteristic.

[0054] The in-situ strobing unit includes a first electrode layer, a storage functional layer, and a second electrode layer stacked in sequence, and its storage functional layer has a bi-directional threshold switching characteristic. Specifically, under the electric field in the first polarity direction, the in-situ strobing unit has a first threshold voltage; under the electric field opposite to the first polarity, the in-situ strobing unit has a second threshold voltage. The in-situ strobing unit realizes strobing and storage by adopting the method of threshold voltage regulation. Specifically, the in-situ strobing unit can realize the transition between the high-resistance state and the low-resistance state under the control of an externally applied electric field, so as to realize the storage and reading of data.

[0055] Continue to refer to Figures 2 to 3 , the in-situ strobing unit includes a first electrode layer 1011, a storage functional layer 1012, and a second electrode layer 1013 stacked in sequence from bottom to top. An interlayer dielectric material is provided between the first electrode layer 1011 and the storage functional layer 1012, and between the storage functional layer 1012 and the second electrode layer 1013. Continue to refer to Figure 2 , when observing the storage array 101 along the direction perpendicular to the AAˋ section, adjacent multiple in-situ strobing units have interconnected first electrode layers 1011. Continue to refer to Figure 3 , when observing the storage array 101 along the direction perpendicular to the BBˋ section, adjacent multiple in-situ strobing units have interconnected second electrode layers 1013.

[0056] The heat dissipation structure can be formed by depositing a high thermal conductivity material, and its forming materials include but are not limited to the following materials: metal materials such as tungsten, aluminum, aluminum nitride, tungsten nitride, etc., and semiconductors such as polysilicon. In addition, considering that the resistivity of common high thermal conductivity materials is relatively low, in some embodiments, a dielectric material layer can be provided between the storage array and the heat dissipation structure to effectively reduce the risk of leakage of the in-situ strobing unit.

[0057] In some embodiments, the first heat dissipation unit, and / or the second heat dissipation unit includes a grid structure composed of a plurality of first heat dissipation fins arranged at intervals.

[0058] The first heat dissipation unit includes a grid structure composed of a plurality of first heat dissipation fins arranged at intervals; the second heat dissipation unit includes a grid structure composed of a plurality of first heat dissipation fins arranged at intervals. The grid structure composed of a plurality of first heat dissipation fins arranged at intervals, such as dense grid bars, and a plurality of first heat dissipation fins parallel to each other can effectively increase the heat dissipation area of the heat dissipation structure, and can provide a larger surface area for heat exchange with the dielectric material layer, thereby improving the heat dissipation capacity.

[0059] It should be noted that in some embodiments, the first heat dissipation unit, and / or the second heat dissipation unit can be an integral block structure. In the same in-situ strobing memory, according to the design requirements, the heat dissipation structure of the grid structure and the heat dissipation structure of the block structure can be combined and designed. For example, the first heat dissipation unit is a grid structure composed of a plurality of first heat dissipation fins arranged at intervals, and the second heat dissipation unit is an integral block structure.

[0060] In some embodiments, the first heat dissipation fin is parallel to the first side surface, or parallel to the second side surface, or parallel to the surface of the substrate.

[0061] Such as Figure 6AAs shown, the direction of the plane where the first heat sink is located is parallel to the first side surface of the memory array 101, and a plurality of first heat sinks 601 parallel to the first side surface form a grid structure. A dielectric material layer may be provided between the first heat sinks. Figure 6B and Figure 6C are respectively the cross-sectional views corresponding to the CCˋ section and the DDˋ section of the in-situ strobing memory.

[0062] As Figure 7 shown, the direction of the plane where the first heat sink is located is parallel to the second side surface, and a plurality of first heat sinks 601 parallel to the second side surface form a grid structure. A dielectric material layer may be provided between the first heat sinks. As Figure 8 shown, the direction of the plane where the first heat sink is located is parallel to the upper surface of the substrate, and a plurality of first heat sinks 601 parallel to the substrate form a grid structure. A dielectric material layer may be provided between the first heat sinks.

[0063] In some embodiments, at least one end of a plurality of spaced-apart first heat sinks is connected to each other.

[0064] Exemplarily, as Figure 9 shown, a plurality of first heat sinks 601 arranged parallel to each other are spaced apart, and at the side close to the substrate (the bottom of the memory array), the ends of the plurality of first heat sinks 601 are connected to each other. It should be noted that the embodiments of the present application do not limit the specific number of the connected first heat sinks. The ends of the plurality of first heat sinks in the first heat dissipation unit 1021 may all be connected to each other, or may be partially connected to each other.

[0065] It can be understood that the ends of the plurality of first heat sinks may also be connected to each other on the side far from the substrate.

[0066] In some embodiments, the first heat dissipation unit, and / or the second heat dissipation unit further includes at least one second heat sink, and the second heat sink is perpendicular to the first heat sink; one second heat sink is used to connect the ends of two first heat sinks.

[0067] In some embodiments, the first heat dissipation unit may also include a plurality of first heat sinks and one second heat sink, and the second heat sink is perpendicular to the first heat sink. Among them, the second heat sink is used to connect the ends of two adjacent first heat sinks.

[0068] It should be noted that the thickness of the first heat sink and the thickness of the second heat sink can be set separately.

[0069] In some other embodiments, the first heat dissipation unit includes a plurality of second heat sinks, and the planes where the plurality of second heat sinks are located are parallel to each other. The second heat sinks are perpendicular to the first heat sinks. The second heat sinks close to the substrate side are connected to the two first heat sinks at the distal ends, and the second heat sinks away from the substrate surface are connected to the two first heat sinks on the inner side. A dielectric material layer is further included between different second heat sinks. As Figure 10A shown, the first heat dissipation unit includes five first heat sinks 601 parallel to the first side surface, and a dielectric material layer is included between different first heat sinks. Two second heat sinks 1001 parallel to the substrate surface, and a dielectric material layer is included between different second heat sinks. The second heat sinks 1001 extending horizontally are perpendicular to the first heat sinks 601 extending vertically. The lowermost second heat sink 1001 is connected to the two first heat sinks 601 on the leftmost and rightmost sides, and the upper second heat sink 1001 is connected to the two first heat sinks 601 inside. Figure 10B and Figure 10C are respectively the cross-sectional views corresponding to the EEˋ section and the FFˋ section of the in-situ strobing memory.

[0070] It can be understood that the second heat dissipation unit may also include at least one second heat sink. Specifically, the second heat dissipation unit includes a second heat sink connected to a plurality of first heat sinks. Alternatively, the second heat dissipation unit includes a plurality of second heat sinks respectively connected to a plurality of first heat sinks.

[0071] It should be noted that, in some embodiments, the heat dissipation structure includes a first heat dissipation unit and a second heat dissipation unit, wherein the first heat dissipation unit includes one or more second heat sinks. The second heat dissipation unit may include one or more second heat sinks, or may not include a second heat sink.

[0072] In some embodiments, the plurality of heat dissipation structures include: one or more rectangular structures; the rectangular structures surround a plurality of memory arrays;

[0073] The rectangular structure is formed by alternately connecting the first heat dissipation unit and the second heat dissipation unit end to end.

[0074] A plurality of first heat dissipation units and a plurality of second heat dissipation units are alternately connected end to end to form a plurality of rectangular structures, and each rectangular structure surrounds the same number of memory arrays. Exemplarily, as Figure 11 shown, every two first heat dissipation units 1021 and every two second heat dissipation units 1022 are alternately connected end to end to form a rectangular structure. A plurality of rectangular structures are arranged in an array, and each rectangular structure surrounds two memory arrays 101.

[0075] In some embodiments, the plurality of rectangular structures surround layer by layer in sequence.

[0076] A plurality of first heat dissipation units and a plurality of second heat dissipation units are alternately connected end to end to form a plurality of rectangular structures, and the plurality of rectangular structures enclose a plurality of memory arrays with different quantities. Exemplarily, as Figure 12 shown, every two first heat dissipation units 1021 and every two second heat dissipation units 1022 are alternately connected end to end to form a rectangular structure. The plurality of rectangular structures are surrounded layer by layer in sequence. From the inside to the outside, each rectangular structure encloses different quantities of memory structures. The first layer of rectangular structure encloses two memory arrays 101, and the second layer of rectangular structure encloses twelve memory arrays. It should be noted that the embodiments of the present application do not limit the specific quantity of memory arrays enclosed by each rectangular structure, and this quantity can be flexibly set according to actual needs.

[0077] In some embodiments, the plurality of memory arrays include a multi-layer structure stacked in a direction perpendicular to the substrate;

[0078] The heat dissipation structure includes a first heat dissipation unit adjacent to a first side surface of one or more of the memory arrays in at least one layer of the multi-layer structure; and / or, a second heat dissipation unit adjacent to a second side surface of one or more of the memory arrays in at least one layer of the multi-layer structure.

[0079] In a direction perpendicular to the plane where the substrate is located, a plurality of stacked memory arrays form a multi-layer structure. For a memory of the multi-layer structure, different heat dissipation structures can be set between the memory arrays of different layers. In a specific embodiment, as Figure 13A shown, a first heat dissipation unit 1021 adjacent to the left side surface is set between the lower-layer memory arrays, and a dielectric material layer 401 is set on the right side surface; a first heat dissipation unit 1021 adjacent to the right side surface is set between the upper-layer memory arrays, and a dielectric material layer 401 is set on the left side surface. Figure 13B This is a cross-sectional view corresponding to the GGˋ section of the in-situ gated memory. In another specific embodiment, as Figure 14 shown, second heat dissipation units 1022 adjacent to the front and rear side surfaces are set between the lower-layer memory arrays, and dielectric material layers 401 are set on the left and right side surfaces. First heat dissipation units 1021 adjacent to the left and right side surfaces are set between the upper-layer memory arrays, and dielectric material layers 401 are set on the front and rear side surfaces.

[0080] In some embodiments, in a direction perpendicular to the second side surface, the first heat dissipation unit includes a plurality of first sub-heat dissipation units arranged at intervals, and the length of the first sub-heat dissipation unit is less than or equal to the length of the memory array;

[0081] In a direction perpendicular to the first side surface, the second heat dissipation unit includes a plurality of second sub-heat dissipation units arranged at intervals, and the length of the second sub-heat dissipation unit is less than or equal to the length of the memory array.

[0082] In a direction perpendicular to the second side surface, the first heat dissipation unit includes a plurality of first sub-heat dissipation units arranged at intervals, and the length of each first sub-heat dissipation unit is less than or equal to the length of the storage array in this direction. Exemplarily, as Figure 15 shown, the first heat dissipation unit 1021 includes a plurality of first sub-heat dissipation units 1501 arranged at intervals, and the length of each first sub-heat dissipation unit 1501 in the vertical direction is equal to the length of the storage array 101 in this direction.

[0083] In a direction perpendicular to the first side surface, the second heat dissipation unit includes a plurality of second sub-heat dissipation units arranged at intervals, and the length of each second sub-heat dissipation unit is less than or equal to the length of the storage array in this direction. As shown in the figure, the second heat dissipation unit includes second sub-heat dissipation units arranged at intervals, and the length of each second sub-heat dissipation unit is equal to the length of the storage array in this direction. Exemplarily, as Figure 16 shown, the second heat dissipation unit 1022 includes a plurality of second sub-heat dissipation units 1601 arranged at intervals, and the length of each second sub-heat dissipation unit 1601 in the horizontal direction is equal to the length of the storage array 101 in this direction.

[0084] In another embodiment, as Figure 17 shown, the heat dissipation structure includes both first sub-heat dissipation units 1501 arranged longitudinally at intervals and second sub-heat dissipation units 1601 arranged transversely at intervals.

[0085] The various embodiments / implementations provided in this application can be combined with each other without conflict.

[0086] The above are only the preferred embodiments of this application and are not used to limit this application. For those skilled in the art, this application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims

1. An in-situ gated memory, characterized in that: include: substrate; A plurality of storage arrays located on the substrate; The storage array includes a plurality of in-situ gating units; at least one heat dissipation structure; The heat dissipation structure comprises: a first heat dissipation unit adjacent to a first side surface of at least one of the storage arrays; and / or, a second heat dissipation unit adjacent to a second side surface of at least one of the storage arrays.

2. The in-situ gating memory according to claim 1, characterized in that: The first heat dissipation unit and / or the second heat dissipation unit include a grid structure consisting of a plurality of first heat dissipation fins arranged at intervals.

3. The in-situ gating memory according to claim 2, characterized in that: The first heat sink is parallel to the first side surface, or parallel to the second side surface, or parallel to the surface of the substrate.

4. The in-situ gating memory according to claim 2, characterized in that: At least one end portion of a plurality of first heat sinks arranged at intervals is connected to each other.

5. The in-situ gating memory according to claim 2, characterized in that: The first heat dissipation unit and / or the second heat dissipation unit further includes at least one second heat dissipation fin, wherein the second heat dissipation fin and the first heat dissipation fin are perpendicular to each other; and one second heat dissipation fin is used to connect the ends of two first heat dissipation fins.

6. The in-situ gating memory according to any one of claims 1 to 5, characterized in that: The plurality of heat dissipation structures include: one or more rectangular structures; the rectangular structures surround a plurality of storage arrays; The rectangular structure is formed by alternately connecting the first heat dissipation units and the second heat dissipation units end to end.

7. The in-situ gating memory according to claim 6, characterized in that: The plurality of rectangular structures are surrounded layer by layer in sequence.

8. The in-situ gating memory according to any one of claims 1 to 5, characterized in that: A plurality of the memory arrays include a multi-layer structure stacked in a direction perpendicular to the substrate; The heat dissipation structure includes a first heat dissipation unit adjacent to a first side of one or more storage arrays of at least one layer in the multi-layer structure; and / or a second heat dissipation unit adjacent to a second side of one or more storage arrays of at least one layer in the multi-layer structure.

9. The in-situ gating memory according to any one of claims 1 to 5, characterized in that: In a direction perpendicular to the second side surface, the first heat dissipation unit includes a plurality of first sub-heat dissipation units arranged at intervals, and the length of the first sub-heat dissipation unit is less than or equal to the length of the storage array; In a direction perpendicular to the first side surface, the second heat dissipation unit includes a plurality of second sub-heat dissipation units arranged at intervals, and the length of the second sub-heat dissipation unit is less than or equal to the length of the storage array.

10. The in-situ gating memory according to any one of claims 1 to 5, characterized in that: The in-situ gating unit comprises a first electrode layer storage function layer and a second electrode layer sequentially stacked in a direction perpendicular to the substrate surface, and the storage function layer has a bidirectional threshold switching characteristic.

Images