Fan-out wafer level packaging unit

Abstract

The utility model discloses a fan-out type wafer level packaging unit. The fan-out type wafer level packaging unit comprises a carrier plate, at least one first bare chip, a first dielectric layer, a plurality of first conducting circuits, a second dielectric layer, a plurality of second conducting circuits and at least one second bare chip, wherein the vertical chip area of the second surface of each first die is defined as a chip area; wherein the second dielectric layer is provided with a plurality of second grooves for exposing the second conductive connection lines to form welding pads, and the welding pads around the chip area are the first welding pads; wherein each second bare crystal is arranged above the second dielectric layer by using a flip chip technology and is electrically connected with each first bare crystal; wherein each first bare crystal can be electrically connected with the outside through each first welding pad pair so as to solve the problems that the existing fan-out type packaging technology is easy to generate higher manufacturing cost and is not beneficial to environmental protection when each conducting circuit is manufactured.

Description

Technical Field

[0001] The utility model relates to a packaging unit, in particular to a fan-out wafer-level packaging unit. Background Art

[0002] The development trend of the semiconductor industry is towards thin, light, short, and small packaging technologies with high efficiency and high reliability. Among them, fan-out wafer-level packaging (FOWLP) is an existing packaging technology.

[0003] In advanced packaging FOWLP, the redistribution layer (RDL) is the most crucial. Because each conductive connection line in the RDL can enable multiple pads on the bare die to generate XY-plane electrical extension and interconnection effects, so that a plurality of relatively dispersed pads can be formed around the bare die, thereby effectively improving the design space and reliability of each conductive connection line. However, how to make each conductive connection line in the RDL maintain or achieve a certain degree of thin, light, short, and small effect while generating XY-plane electrical extension and interconnection effects, the manufacturing of each conductive connection line in the RDL is the most crucial.

[0004] However, the forming method of each conductive connection line in the RDL technology applied in the existing FOWLP packaging technology is to use chemical plating forming technology or electroplating forming technology for manufacturing. In this way, in addition to the relatively high material cost and manufacturing cost, the existing manufacturing process also does not meet or is not conducive to environmental protection requirements.

[0005] In addition, when the FOWLP packaging unit needs to increase performance or computing power, it is necessary to additionally increase the number of bare dies. How to perform external or internal electrical connections between the bare dies inside and outside the packaging unit is also an important problem that needs to be solved. Summary of the Utility Model

[0006] The main purpose of the utility model is to provide a fan-out wafer-level packaging unit, including a carrier board, at least one first bare die, a first dielectric layer, a plurality of first conductive connection lines, a second dielectric layer, a plurality of second conductive connection lines, and at least one second bare die; wherein the vertical chip area on the second surface of each first bare die is defined as the chip area; wherein the second dielectric layer has a plurality of second grooves for each second conductive connection line to be externally exposed to form pads, and each pad located around the chip area is a first pad; wherein each second bare die is disposed above the second dielectric layer by using flip-chip technology and is electrically connected to each first bare die; wherein each first bare die can be externally electrically connected by each first pad, effectively solving the problem that the fan-out packaging technology in the existing module is prone to high manufacturing costs and is not conducive to environmental protection when manufacturing each conductive connection line.

[0007] To achieve the above object, the present utility model provides a fan-out wafer-level packaging unit, which includes a carrier plate, at least one first die, a first dielectric layer, a plurality of first connection lines, a second dielectric layer, a plurality of second connection lines and at least one second die; wherein each of the first dies is separated from a wafer, each of the first dies has a first surface and a second surface opposite thereto, the first surface of each of the first dies is fixedly disposed on the carrier plate, a plurality of pads are provided on the second surface of each of the first dies, and the vertical chip area of the second surface is defined as a chip area; wherein the first dielectric layer is disposed on the carrier plate and the second surface of each of the first dies, the first dielectric layer has a plurality of first grooves formed by extending horizontally, and each of the pads of each of the first dies is exposed to the outside by the plurality of first grooves; wherein each of the first connection lines is formed by filling metal paste in the plurality of first grooves, and each of the first connection lines is electrically connected to the plurality of pads of each of the first dies; wherein the second dielectric layer is disposed on the first dielectric layer, the second dielectric layer has a plurality of second grooves formed by extending horizontally, and each of the second grooves communicates with each of the first grooves; wherein each of the second connection lines is formed by filling metal paste in the plurality of second grooves, and each of the second connection lines is electrically connected to each of the first connection lines, and each of the second grooves exposes the plurality of second connection lines to the outside to form solder pads therein, and the solder pads formed in the plurality of second grooves around the chip area on the second surface of each of the first dies are a first solder pad, and each of the first solder pads is further electrically connected to each of the first connection lines around the chip area; the solder pads formed in the plurality of second grooves within the chip area on the second surface of each of the first dies are a second solder pad, and each of the second solder pads is further electrically connected to the plurality of first connection lines within the chip area; wherein each of the second dies is separated from a wafer, each of the second dies has a first surface and a second surface opposite thereto, and at least two pads are provided on the second surface of each of the second dies, and at least two of the pads of each of the second dies are electrically connected by flip-chip technology to be disposed on at least two of the second solder pads, so that each of the second dies is located above the second dielectric layer, and each of the second dies can be electrically connected to each of the first dies through the plurality of first connection lines within the chip area; wherein each of the first dies can be electrically connected to the outside in sequence through the plurality of pads of each of the first dies, the plurality of first connection lines around the chip area, the plurality of second connection lines and the plurality of first solder pads around the chip area on the second surface of each of the first dies, thereby forming the fan-out wafer-level packaging unit.

[0008] In a preferred embodiment of the present utility model, each of the first bare dies and each of the second bare dies are further formed by dividing from the same wafer.

[0009] In a preferred embodiment of the present utility model, each of the first bare dies and each of the second bare dies are further formed by dividing from different wafers.

[0010] In a preferred embodiment of the present utility model, the carrier plate includes a silicon (Si) carrier plate, a glass carrier plate or a ceramic carrier plate.

[0011] In a preferred embodiment of the present utility model, the metal paste forming each of the first conductive lines includes silver paste, nano silver paste, copper paste or nano copper paste.

[0012] In a preferred embodiment of the present utility model, the metal paste forming each of the second conductive lines includes silver paste, nano silver paste, copper paste or nano copper paste.

[0013] In a preferred embodiment of the present utility model, the first surface of each of the first bare dies is further disposed on the carrier plate by using a die attach film (DAF).

[0014] In a preferred embodiment of the present utility model, each of the pads of each of the second bare dies is further electrically connected to at least two of the pads via a solder ball.

[0015] In a preferred embodiment of the present utility model, a solder ball is further disposed on each of the second grooves, and each solder ball can be electrically connected to a plurality of the pads in a plurality of the second grooves.

[0016] In a preferred embodiment of the present utility model, the fan-out wafer-level packaging unit can be electrically connected and disposed on a printed circuit board (PCB) by using each of the solder balls. Description of the Drawings

[0017] Figure 1 is a schematic plan view of a side cross-section of an application embodiment of the fan-out wafer-level packaging unit of the present utility model.

[0018] Figure 2 is a schematic plan view of a side cross-section of the carrier plate of the present utility model.

[0019] Figure 3 is in Figure 2 a schematic plan view of a side cross-section of laying a first dielectric layer on the carrier plate in.

[0020] Figure 4 is in Figure 3 a schematic plan view of a side cross-section of filling a metal paste in each of the first grooves in.

[0021] Figure 5 is a schematic plan view of a side cross-section for grinding a metal paste that is above the surface of a first dielectric layer in Figure 4 .

[0022] Figure 6 is a schematic plan view of a side cross-section for laying a second dielectric layer on a first dielectric layer in Figure 5 .

[0023] Figure 7 is a schematic plan view of a side cross-section for filling a metal paste into each second groove in Figure 6 .

[0024] Figure 8 is a schematic plan view of a side cross-section for grinding a metal paste that is above the surface of a second dielectric layer in Figure 7 .

[0025] Figure 9 is a schematic plan view of a side cross-section for disposing a second bare die above a second dielectric layer using flip-chip technology in Figure 8 .

[0026] Figure 10 is a schematic plan view of a side cross-section for providing solder balls on each second groove in Figure 9 .

[0027] Explanation of reference numerals: 1 - Fan-out wafer-level packaging unit; 1a - Chip area; 10 - Carrier board; 20 - First bare die; 21 - First surface; 22 - Second surface; 23 - Bonding pad; 30 - First dielectric layer; 31 - First groove; 40 - First connection line; 40a - Metal paste; 50 - Second dielectric layer; 51 - Second groove; 60 - Second connection line; 60a - Metal paste; 61 - First solder pad; 62 - Second solder pad; 70 - Chip bonding film; 80 - Second bare die; 81 - First surface; 82 - Second surface; 83 - Bonding pad; 90 - Solder ball; 2 - Printed circuit board. Detailed implementation manners

[0028] In conjunction with the drawings, the structure and its technical features of the present invention are described in detail as follows. Each drawing is only used to illustrate the structural relationship and related functions of the present invention. Therefore, the dimensions of each component in each drawing are not drawn according to the actual ratio and are not used to limit the present invention.

[0029] Refer to Figure 1 and Figure 9, the present utility model provides a fan-out wafer-level packaging unit 1, which includes a carrier 10, at least one first bare die 20, a first dielectric layer 30, a plurality of first connection lines 40, a second dielectric layer 50, a plurality of second connection lines 60, a chip bonding film 70, and at least one second bare die 80, but not limited thereto.

[0030] Each of the first bare dies 20 is separated from a wafer. Each first bare die 20 has a first surface 21 and a second surface 22 opposite thereto. The first surface 21 of each first bare die 20 is fixedly disposed on the carrier 10. A plurality of pads 23 are provided on the second surface 22 of each first bare die 20, and the vertical chip area of the second surface 22 is defined as a chip area 1a, as Figure 2 shown; wherein the first surface 21 of each first bare die 20 is further disposed on the carrier 10 by using the chip bonding film (DAF, Die Attach Film) 70, but not limited thereto, as Figure 2 shown; in Figure 2 , taking 4 pads 23 of each first bare die 20 as an example for illustration, but not intended to limit the present utility model.

[0031] The first dielectric layer 30 is disposed on the carrier 10 and the second surfaces 22 of each first bare die 20. The first dielectric layer 30 has a plurality of first grooves 31 formed by extending horizontally, as Figure 3 shown; wherein each pad 23 of each first bare die 20 is exposed to the outside through each first groove 31, as Figure 3 shown.

[0032] Each of the first connection lines 40 is composed of a metal paste 40a filled in each first groove 31. Each first connection line 40 is electrically connected to each pad 23 of each first bare die 20, as Figure 5 shown.

[0033] The second dielectric layer 50 is disposed on the first dielectric layer 30. The second dielectric layer 50 has a plurality of second grooves 51 formed by extending horizontally. Each second groove 51 communicates with each first groove 31, as Figure 6 shown.

[0034] Each of the second connection lines 60 is composed of a metal paste 60a filled in each second groove 51. Each second connection line 60 is electrically connected to each first connection line 40, as Figure 8 shown; wherein the solder pads formed in each second groove 51 around the chip area 1a on the second surface 22 of each first bare die 20 are first solder pads 61, and each first solder pad 61 is further electrically connected to each first connection line 40 around the chip area 1a, asFigure 9 As shown; the solder pads formed in each of the second grooves 51 within the range of the chip region 1a on the second surface 22 of each of the first dies 20 are second solder pads 62, and each of the second solder pads 62 is further electrically connected to each of the first connection lines 40 within the range of the chip region 1a, as Figure 9 shown.

[0035] Each of the second dies 80 is separated from a wafer. Each of the second dies 80 has a first surface 81 and a second surface 82 opposite thereto. At least two pad electrodes 83 are provided on the second surface 82 of each of the second dies 80, as Figure 9 shown; wherein at least two of the pad electrodes 83 of each of the second dies 80 are disposed on at least two of the second solder pads 62 in a flip-chip bonding manner, so that each of the second dies 80 is located above the second dielectric layer 70, and each of the second dies 80 can be electrically connected to each of the first dies 20 via each of the first connection lines 40 within the range of the chip region 1a, as Figure 9 shown. In Figure 9 this, two of the pad electrodes 83 of the second die 80 are taken as an example for illustration, but it is not intended to limit the present invention.

[0036] Each of the first dies 20 can be electrically connected to the outside in sequence via each of the pad electrodes 23 of each of the first dies 20, each of the first connection lines 40 around the chip region 1a, each of the second connection lines 60, and each of the first solder pads 61 around the chip region 1a on the second surface 22 of each of the first dies 20, thereby forming the fan-out wafer-level packaging unit 1, as Figure 9 shown.

[0037] The process of manufacturing the fan-out wafer-level packaging unit 1 may include the following steps, but is not limited thereto:

[0038] Step S1: Provide a carrier substrate 10, as Figure 2 shown.

[0039] Step S2: Dispose a plurality of first dies 20 separated from at least one wafer (Wafer) on the carrier substrate 10 at intervals, as Figure 2 shown; wherein each of the first dies 20 has a first surface 21 and a second surface 22 opposite thereto. The first surface 21 of each of the first dies 20 is disposed on the carrier substrate 10. A plurality of pad electrodes 23 are provided on the second surface 22 of each of the first dies 20, and the vertical chip region of the second surface 22 is defined as a chip region 1a, as Figure 2 shown.

[0040] Step S3: Using the technique of first filling the metal paste into the grooves and then grinding and forming the conductive lines to form a plurality of first conductive lines 40 on the second surface 22 of each first die 20: First, a first dielectric layer 30 is laid on the carrier plate 10 and the second surface 22 of each first die 20, and then a plurality of first grooves 31 are formed horizontally on the first dielectric layer 30, so that each pad 23 of each first die 20 can be exposed to the outside through each first groove 31, as Figure 3 shown. Then, the metal paste 40a is filled into each first groove 31, and the thickness of the metal paste 40a is higher than the surface of the first dielectric layer 30, as Figure 4 shown. Finally, the metal paste 40a higher than the surface of the first dielectric layer 30 is ground so that the surface of the metal paste 40a is flush with the surface of the first dielectric layer 30 to form a plurality of the first conductive lines 40, as Figure 5 shown.

[0041] Step S4: Using the technique of first filling the metal paste into the grooves and then grinding and forming the conductive lines to form a plurality of second conductive lines 60 on the first dielectric layer 30: First, a second dielectric layer 50 is laid on the first dielectric layer 30, and then a plurality of second grooves 51 are formed horizontally on the second dielectric layer 50, and each second groove 51 can communicate with each first groove 31, as Figure 6 shown. Then, the metal paste 60a is filled into each second groove 51, and the thickness of the metal paste 60a is higher than the surface of the second dielectric layer 50, as Figure 7 shown. Finally, the metal paste 60a higher than the surface of the second dielectric layer 50 is ground so that the surface of the metal paste 60a is flush with the surface of the second dielectric layer 50 to form a plurality of the second conductive lines 60, as Figure 8 shown; wherein each second groove 51 allows each second conductive line 60 to be exposed to the outside and forms a solder pad in each second groove 51, as Figure 8 shown; wherein the solder pads formed in each second groove 51 around the chip area 1a on the second surface 22 of each first die 20 are a first solder pad 61, and each first solder pad 61 is further electrically connected to each first conductive line 40 around the chip area 1a, as Figure 9 shown; wherein the solder pads formed in each second groove 51 within the chip area 1a on the second surface 22 of each first die 20 are a second solder pad 62, and each second solder pad 62 is further electrically connected to each first conductive line 40 within the chip area 1a, as Figure 9 shown.

[0042] Step S5: The plurality of second dies 80 separated from at least one wafer are disposed at intervals above the second dielectric layer 70 by using the flip-chip technology, asFigure 9 as shown; each second die 80 has a first surface 81 and a second surface 82 opposite thereto, and at least two pads 83 are provided on the second surface 82 of each second die 80, as Figure 9 shown; at least two of the pads 83 of each second die 80 are electrically connected to at least two of the second pads 62 by using flip-chip technology, and each second die 80 can be electrically connected to each first die 20 through each first conductive line 40 within the range of the chip region 1a, as Figure 9 shown.

[0043] Step S6: Perform a dicing operation to dice and form a plurality of fan-out wafer-level packaging units 1, as Figure 9 shown.

[0044] The processes of step S3 to step S4 in the above-mentioned preferred process for manufacturing the fan-out wafer-level packaging unit 1 can be regarded as the key steps for fabricating the redistribution layer (RDL, Redistribution Layer) of the fan-out wafer-level packaging unit 1. In step S3, a plurality of the first conductive lines 40 are formed on the second surface 22 of each first die 20 by using a technique of first injecting metal paste into the grooves and then grinding and forming the conductive lines. In step S4, a plurality of the second conductive lines 60 are formed on the second dielectric layer 50 and the plurality of the first conductive lines 40 by using a technique of first injecting metal paste into the grooves and then grinding and forming the conductive lines. Since both step S3 and step S4 are processes that are easy to implement precisely, the process is relatively simplified, which is sufficient to enable each first conductive line 40 and each second conductive line 60 in the redistribution layer to generate XY-plane electrical extension and interconnection effects, and at the same time, the fabricated fan-out wafer-level packaging unit 1 can still maintain or achieve a certain degree of thin, light, short, and small specific effects.

[0045] Referring to Figure 9 , each first die 20 and each second die 80 are further formed by dicing from the same wafer, but it is not limited that the specifications of the dies are the same, which is beneficial to the performance of stacked operations.

[0046] Referring to Figure 9 , each first die 20 and each second die 80 are further formed by dicing from different wafers, but it is not limited that the specifications of the dies are different, which is beneficial to increasing the diversified applications of the product.

[0047] Referring to Figure 2 , the carrier 10 includes a silicon (Si) carrier, a glass carrier, or a ceramic carrier, but it is not limited, which is beneficial to increasing the diversified applications of the product.

[0048] Referring to Figure 5, the metal paste 40a that constitutes each first conductive line 40 includes silver paste, nano silver paste, copper paste, or nano copper paste, but is not limited thereto. The nano silver paste material has characteristics such as low cost, high conductivity, and the ability to sinter at low temperatures. However, since the nano silver paste material is a common existing material, it will not be elaborated here.

[0049] Reference Figure 8 , the metal paste 60a that constitutes each second conductive line 60 includes silver paste, nano silver paste, copper paste, or nano copper paste, but is not limited thereto.

[0050] Reference Figure 9 , each pad 83 of each second die 80 is further electrically connected to at least two of the pads 61 through a solder ball 90, but is not limited thereto.

[0051] Reference Figure 10 , a solder ball 90 is further provided on each second groove 51, but is not limited thereto. Each solder ball 90 can be electrically connected to each pad 61 in each second groove 51.

[0052] Reference Figure 1 , the fan - out wafer - level packaging unit 1 can be electrically connected and disposed on a printed circuit board (PCB) 2 by using each solder ball 90, but is not limited thereto.

[0053] Compared with the existing fan - out wafer - level packaging unit technology, the fan - out wafer - level packaging unit 1 of the present utility model has the following advantages:

[0054] (1) In steps S3 to S4 of the preferred process for manufacturing the fan - out wafer - level packaging unit 1 of the present utility model, compared with the related technologies for manufacturing existing fan - out wafer - level packaging units, when manufacturing the present utility model, through the production of each conductive line in the RDL, each conductive line in the RDL can have an XY - plane electrical extension and interconnection effect, and at the same time, it can also maintain or achieve a certain degree of thin, light, short, and small effect. These are all simplified and easily precisely implemented steps, especially beneficial for reducing the thickness of the packaging unit. Therefore, the manufacturing process of the present utility model is not only more simplified and cost - saving, but also can effectively improve the usage efficiency and reliability of the fan - out wafer - level packaging unit 1.

[0055] (2) Multiple first conductive lines 40 of the present utility model are formed on the second surface 22 of each first die 20 by using the technology of first injecting metal paste into the grooves and then grinding and forming the conductive lines. Therefore, the present utility model can effectively solve the problems of high manufacturing cost and environmental unfriendliness that are prone to occur in the production of each conductive line in the existing fan - out packaging technology.

[0056] (3) The multiple second conductive lines 60 of the present utility model are fabricated on the second dielectric layer 50 and the multiple first conductive lines 40 by a technique of first injecting metal paste into the grooves and then grinding and forming the conductive lines. Therefore, the present utility model can effectively solve the problems of high manufacturing cost and environmental unfriendliness easily generated in the existing fan-out packaging technology when fabricating each conductive line.

[0057] (4) At least two of the pads 83 of each second die 80 of the present utility model are electrically connected to at least two of the second solder pads 62 by flip-chip technology, so that each second die 80 is located above the second dielectric layer 70, and each second die 80 can be electrically connected to each first die 20 through each first conductive line 40 within the range of the chip region 1a, as Figure 9 shown, increasing the multiple die bonding forms of the product, which is beneficial to enhancing the market competitiveness of the product.

[0058] The above are only the preferred embodiments of the present utility model, which are illustrative rather than restrictive to the present utility model; those of ordinary skill in the art understand that many changes, modifications, and even equivalent changes can be made to it within the spirit and scope defined by the claims of the present utility model, but all will fall within the protection scope of the present utility model.

Claims

1. A fan-out wafer-level packaging unit, characterized in that: Include: a carrier board; At least one first die, each of which is split from a wafer, each of which has a first surface and an opposite second surface, the first surface of each of which is fixed on the carrier, the second surface of each of which has a plurality of pads, and a vertical chip area on the second surface is defined as a chip area; A first dielectric layer is disposed on the carrier and the second surface of each of the first bare crystals, the first dielectric layer having a plurality of first grooves extending in a horizontal direction; wherein each of the crystal pads of each of the first bare crystals is exposed to the outside by the plurality of the first grooves; A plurality of first conducting circuits, each of which is formed by metal paste filled in a plurality of the first grooves, and each of which is electrically connected to a plurality of the die pads of each of the first bare die; A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves extending in a horizontal direction, each of the second grooves being connected to each of the first grooves; a plurality of second conducting circuits, each of which is formed by metal paste filled in the plurality of second grooves, and each of which is electrically connected to each of the first conducting circuits; wherein each of the second grooves allows the plurality of second conducting circuits to be exposed to the outside and forms bonding pads in the plurality of second grooves; wherein the bonding pads formed in the plurality of second grooves around the chip region on the second surface of each of the first bare crystals are first bonding pads, and each of the first bonding pads is electrically connected to the plurality of first conducting circuits around the chip region; wherein the bonding pads formed in the plurality of second grooves within the chip region on the second surface of each of the first bare crystals are second bonding pads, and each of the second bonding pads is electrically connected to the plurality of first conducting circuits within the chip region; and At least one second die, each of the first die is split from a wafer, each of the second die has a first surface and an opposite second surface, and each of the second die has at least two pads on the second surface; wherein the at least two pads of each second die are electrically connected on at least two second pads by using a flip chip process, so that each of the second die is located above the second dielectric layer, and each of the second die can be electrically connected to each of the first die via a plurality of the first conductive lines located within the chip region; Each of the first bare crystals can be electrically connected to the outside in sequence through the multiple crystal pads of each of the first bare crystals, the multiple first conductive lines around the chip area, the multiple second conductive lines, and the multiple first welding pads around the chip area on the second surface of each of the first bare crystals, thereby forming the fan-out wafer-level packaging unit.

2. The fan-out wafer-level packaging unit according to claim 1, characterized in that: Each of the first bare die and each of the second bare die are formed by being separated from the same wafer.

3. The fan-out wafer-level packaging unit according to claim 1, characterized in that: Each of the first bare die and each of the second bare die are separated from different wafers.

4. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The carrier includes a silicon carrier, a glass carrier or a ceramic carrier.

5. The fan-out wafer level packaging unit according to claim 1, characterized in that: The metal paste constituting each of the first conducting circuits includes silver paste, nano silver paste, copper paste or nano copper paste.

6. The fan-out wafer level packaging unit according to claim 1, characterized in that: The metal paste constituting each of the second conducting circuits includes silver paste, nano silver paste, copper paste or nano copper paste.

7. The fan-out wafer level packaging unit according to claim 1, characterized in that: The first surface of each first bare die is disposed on the carrier by using a chip bonding film.

8. The fan-out wafer level packaging unit according to claim 1, characterized in that: The plurality of die pads of each second bare die are electrically connected to at least two of the bonding pads via a solder ball.

9. The fan-out wafer-level packaging unit according to claim 1, characterized in that: A solder ball is disposed on each of the second grooves, and each of the solder balls can be electrically connected to a plurality of the solder pads in a plurality of the second grooves.

10. The fan-out wafer level packaging unit according to claim 9, characterized in that: The fan-out wafer-level packaging unit can be electrically connected and arranged on a printed circuit board using a plurality of solder balls.

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