Display panel and display device

Abstract

The utility model provides a display panel and a display device, and relates to the technical field of display, and the display panel comprises a substrate, a power supply signal line, an initialization signal line and a wire. The power signal lines are arranged on the substrate and located in the display area, each power signal line extends in the first direction, the power signal lines are arranged in the second direction, and the second direction intersects with the first direction. The multiple initialization signal lines are arranged on the substrate and located in the display area, each initialization signal line extends in the first direction, and the multiple initialization signal lines are arranged in the second direction. The multiple wires are arranged on the substrate and located in the display area, each wire extends in the first direction, and the multiple wires are arranged in the second direction. One initialization signal line is electrically connected with one wire, and the orthographic projection of the wire on the substrate is at least partially overlapped with the orthographic projection of the power signal line on the substrate. The display panel is used for displaying pictures.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display panels have attracted much attention due to their excellent display performance. However, while achieving high-performance display, they also cause some display quality problems. For example, when the display brightness of the display panel is low, the display screen will produce horizontal line mura. Utility Model Content

[0003] The present application provides a display panel and a display device, aiming to improve the phenomenon of display transverse line mura.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, a display panel is provided, which includes a substrate, a power signal line, an initialization signal line and a routing line. A plurality of power signal lines are arranged on the substrate and located in a display area, each power signal line extends along a first direction, and a plurality of power signal lines are arranged along a second direction, and the second direction intersects with the first direction. A plurality of initialization signal lines are arranged on the substrate and located in the display area, each initialization signal line extends along the first direction, and a plurality of initialization signal lines are arranged along the second direction. A plurality of routing lines are arranged on the substrate and located in the display area, each routing line extends along the first direction, and a plurality of routing lines are arranged along the second direction. An initialization signal line is electrically connected to a routing line, and the orthographic projection of the routing line on the substrate at least partially overlaps with the orthographic projection of the power signal line on the substrate.

[0006] In the display panel provided by the embodiment of the present application, the routing is connected to the initialization signal line to transmit the anode initialization voltage signal (VAR signal), and the power signal line transmits the voltage signal (ELVSS signal). The positive projection of each routing line on the substrate overlaps at least partially with the positive projection of the power signal line on the substrate, that is, the routing line and the power signal line are opposite to each other to generate capacitance, and the capacitance of the layer where the VAR signal and the ELVSS signal are located is increased without interfering with other signals, so as to appropriately increase the influence of this capacitance on the VAR signal, increase the influence of the waveform of the ELVSS signal on the waveform of the VAR signal, and reduce the difference between the equivalent voltage of the VAR signal and the equivalent voltage of the ELVSS signal.

[0007] During the resetting process of a row of sub-pixels, the anode of the light-emitting device in the row of sub-pixels receives the VAR signal, and the cathode receives the ELVSS signal. The voltage difference (Voled) between the anode and the cathode is reduced, so that the current (Ioled) in the light-emitting functional layer is reduced, and the brightness difference between the sub-pixels in this row and the sub-pixels in other rows is reduced, thereby improving the phenomenon of displaying lateral line mura.

[0008] In some embodiments, the display panel further includes a peripheral area surrounding the display area, and an initialization signal bus disposed in the peripheral area. The initialization signal line extends from the display area to the peripheral area and is electrically connected to the initialization signal bus. The routing line extends from the display area to the peripheral area and is electrically connected to the initialization signal bus.

[0009] In some embodiments, the display panel further includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer stacked sequentially on the substrate. The routing is located in the first conductive layer, the initialization signal line and the power signal line are located in the second conductive layer, and the initialization signal bus is located in the third conductive layer. The display panel further includes a first connection pattern, and the first connection pattern is located in the second conductive layer.

[0010] The initialization signal bus penetrates the second dielectric layer and is electrically connected to the initialization signal line, and the initialization signal bus penetrates the second dielectric layer and is electrically connected to the first connection pattern, and the first connection pattern penetrates the first dielectric layer and is electrically connected to the routing line.

[0011] In some embodiments, the display panel includes a first gate layer, a second gate layer, a third gate layer and a first source-drain conductive layer stacked in sequence on a substrate, and the initialization signal line is located in the first source-drain conductive layer. One of the routing line and the power signal line is located in the third gate layer, and the other is located in the first source-drain conductive layer.

[0012] In some embodiments, the initialization signal line is located in the first source-drain conductive layer, one of the routing line and the power signal line is located in the first gate layer or the second gate layer, and the other is located in the third gate layer.

[0013] In some embodiments, the display panel further includes a plurality of sub-pixels arranged in an array in the display area, the plurality of sub-pixels include a plurality of rows and a plurality of columns, each row of sub-pixels extends along a first direction, and each column of sub-pixels extends along a second direction. The sub-pixels include a pixel driving circuit, each row of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the pixel driving circuits of the first sub-pixel and the third sub-pixel are electrically connected to the initialization signal line, and the pixel driving circuit of the second sub-pixel is electrically connected to the routing line.

[0014] In some embodiments, the pixel driving circuit includes an active layer, and the display panel further includes an insulating layer, a first conductive layer, a first dielectric layer, and a second conductive layer stacked in sequence on a side of the active layer away from the substrate. The routing line is located in the first conductive layer, and the initialization signal line is located in the second conductive layer. The display panel further includes a second connection pattern, and the second connection pattern is located in the second conductive layer.

[0015] The initialization signal line passes through the first dielectric layer and the insulating layer to be electrically connected to the active layer of the first sub-pixel, and the initialization signal line passes through the first dielectric layer and the insulating layer to be electrically connected to the active layer of the third sub-pixel. The second connection pattern passes through the first dielectric layer and the insulating layer to be electrically connected to the active layer of the second sub-pixel, and the second connection pattern passes through the first dielectric layer to be electrically connected to the routing line.

[0016] In some embodiments, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0017] On the other hand, a display device is provided. The display device includes the display panel in the above embodiment and a controller electrically connected to the display panel.

[0018] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solution in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, not the actual size of the product involved in the embodiments of the present application, or the actual process of the method.

[0020] Figure 1 A structural diagram of a mobile phone provided in an embodiment of the present application;

[0021] Figure 2 A top view of a display panel provided in an embodiment of the present application;

[0022] Figure 3 for Figure 2 A partial cross-sectional view of a sub-pixel of a display panel;

[0023] Figure 4 for Figure 2 A partial enlarged view of the display panel at position M;

[0024] Figure 5 for Figure 4 A partial cross-sectional view of the panel along section line AA' is shown in FIG.

[0025] Figure 6 The waveform diagram of the ELVSS signal and the VAR signal caused by the touch signal provided in the embodiment of the present application;

[0026] Figure 7 for Figure 2 A partial enlarged view of the display panel at position N;

[0027] Figure 8 A partial enlarged view of another display panel at position M provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0029] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0030] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0031] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0032] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0033] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0034] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0035] Embodiments of the present application provide a display device, which can be any device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0036] Take a mobile phone as an example for explanation. Figure 1 This is a structural diagram of a mobile phone provided in an embodiment of the present application.

[0037] See also Figure 1 The mobile phone 1 includes a display panel 10, and the display panel 10 may be an organic light emitting diode (OLED) display panel.

[0038] The display panel 10 has a display side and a non-display side, and the display device 100 further includes a circuit board 11 disposed on the non-display side of the display panel 10, and a controller 12 disposed on the circuit board 11, and the controller 12 is electrically connected to the display panel 10. The controller 12 is used to output a timing control signal to control the display panel 10 to display an image.

[0039] Figure 2 A top view of a display panel provided in an embodiment of the present application.

[0040] See also Figure 2The display panel 10 includes a display area A1 and a peripheral area A2, the peripheral area A2 surrounds the outside of the display area A1, a plurality of sub-pixels 2 are arranged in an array, the plurality of sub-pixels 2 arranged in an array include a plurality of rows and a plurality of columns, each row of sub-pixels 2 extends along a first direction X, each column of sub-pixels 2 extends along a second direction Y, and the second direction Y intersects with the first direction X.

[0041] For example, the second direction Y may be perpendicular to the first direction X.

[0042] A light-emitting device L and a pixel driving circuit 3 for controlling the light-emitting device L are provided in the sub-pixel 2. The pixel driving circuit 3 includes transistors and capacitors. Exemplarily, the pixel driving circuit 3 can be 3T1C, 5T2C, 7T1C, etc., wherein "T" is a transistor and "C" is a capacitor. For example, 7T1C means that the pixel driving circuit 3 includes 7 transistors and 1 capacitor.

[0043] Figure 3 for Figure 2 A partial cross-sectional view of a sub-pixel of a display panel.

[0044] See also Figure 3 The display panel 10 includes a substrate 20, and a barrier layer 21, a buffer layer 22, an active film layer ACT, a first gate insulating layer 23, a first gate layer Gate1, a second gate insulating layer 24, a second gate layer Gate2, a third gate insulating layer 25, a third gate layer Gate3, an interlayer dielectric layer 26, a first source-drain conductive layer SD1, and a second source-drain conductive layer SD2 stacked on the substrate 20.

[0045] The material of the substrate 20 may include polyimide (PI).

[0046] The transistor T of the pixel driving circuit 3 includes an active layer T1, a gate G, a source S and a drain D. For example, the active layer T1 is located in the active film layer ACT, the gate G is located in the first gate layer Gate1, and the source S and the drain D are located in the first source-drain conductive layer SD1. The capacitor C of the pixel driving circuit 3 includes a first plate C1 and a second plate C2. For example, the first plate C1 is located in the first gate layer Gate1, and the second plate C2 is located in the second gate layer Gate2.

[0047] Continue to see Figure 3 The light emitting device L includes an anode 30, a light emitting functional layer 31 and a cathode 32 stacked in sequence, the anode 30 is electrically connected to the drain D of the transistor T, and the transistor T is used to transmit a voltage signal to the anode 30. The cathode 32 also receives the voltage signal, and an electric field is generated between the anode 30 and the cathode 32, and the light emitting functional layer 31 can emit light under the drive of the electric field.

[0048] See again Figure 3 The display panel 10 further includes an anode transfer structure 33 , which is located in the second source-drain conductive layer SD2 , and the anode 30 can be electrically connected to the drain D of the transistor T through the anode transfer structure 33 .

[0049] In addition, the display panel 10 further includes a passivation layer 27 and a first planarization layer 28 , which sequentially cover the transistor T. The anode transfer structure 33 penetrates the first planarization layer 28 and the passivation layer 27 and is electrically connected to the drain D of the transistor T.

[0050] In addition, the display panel 10 further includes a second planarization layer 29 , the second planarization layer 29 covers the anode switching structure 33 , and the anode 30 penetrates the second planarization layer 29 and is electrically connected to the anode switching structure 33 .

[0051] The display panel 10 also includes a pixel defining layer 34, which includes a plurality of openings, each of which exposes at least a portion of the anode 30 of each sub-pixel 2, and the light-emitting functional layer 31 of each sub-pixel 2 is arranged in an opening, and the light-emitting functional layer 31 is electrically contacted with the anode 30 through the opening of the pixel defining layer 34.

[0052] The display panel 10 further includes an encapsulation layer 35 and a touch control structure 36 . The encapsulation layer 35 covers the cathode 32 of the encapsulation layer 35 . The touch control structure 36 is disposed on the encapsulation layer 35 to realize a touch control function.

[0053] Figure 4 for Figure 2 A partial enlarged view of the display panel at M in FIG. Figure 4 4 adjacent sub-pixels 2 in a row of sub-pixels 2 are shown; Figure 5 for Figure 4 A partial cross-sectional view of the panel along section line AA' is shown in FIG.

[0054] See also Figure 4 The display panel 10 further includes a plurality of power signal lines 4 and a plurality of initialization signal lines 5. The plurality of power signal lines 4 are disposed on the substrate 20, and the plurality of power signal lines 4 are located in the display area A1. Each power signal line 4 extends along a first direction X, and the plurality of power signal lines 4 are arranged along a second direction Y ( Figure 4 A power signal line 4 is shown in FIG. 1 . It can be understood that each row of sub-pixels 2 corresponds to a power signal line 4). The second direction Y intersects the first direction X. For example, the second direction Y is perpendicular to the first direction X.

[0055] Exemplarily, the power signal line 4 may be an ELVSS line, the cathode 32 of the light emitting device L is electrically connected to the power signal line 4 , and the power signal line 4 is used to provide a voltage signal (ELVSS signal) to the cathode 32 .

[0056] Understandably, see Figure 4 In the process of pattern design, in order to allow the power signal line 4 to avoid other conductive patterns, the shape of the pattern of the power signal line 4 can be designed to be non-linear. Here, "each power signal line 4 extends along the first direction X" means that the entire power signal line 4 extends along the first direction X, and a part of the power signal line 4 can deviate from the first direction X and extend.

[0057] Continue to see Figure 4 , a plurality of initialization signal lines 5 are disposed on the substrate 20, and the plurality of initialization signal lines 5 are located in the display area A1. Each initialization signal line 5 extends along the first direction X, and the plurality of initialization signal lines 5 are arranged along the second direction Y ( Figure 4 An initialization signal line 5 is shown in the figure. It can be understood that each row of sub-pixels 2 corresponds to an initialization signal line 5).

[0058] Understandably, see Figure 4 In the process of pattern design, in order to allow the initialization signal line 5 to avoid other conductive patterns, the shape of the pattern of the initialization signal line 5 can be designed to be non-linear. Here, "each initialization signal line 5 extends along the first direction X" means that the entire initialization signal line 5 extends along the first direction X, and a part of the initialization signal line 5 can deviate from the first direction X and extend.

[0059] See also Figure 4 In the display area A1 , each initialization signal line 5 is electrically connected to the pixel driving circuit 3 of a row of sub-pixels 2 .

[0060] For example, see Figure 5 The initialization signal line 5 is located in the first source-drain conductive layer SD1. The first source-drain conductive layer SD1 and the active film layer ACT are separated by a first gate insulating layer 23, a second gate insulating layer 24, a third gate insulating layer 25 and an interlayer dielectric layer 26. The initialization signal line 5 penetrates the interlayer dielectric layer 26, the third gate insulating layer 25, the second gate insulating layer 24 and the first gate insulating layer 23 and is electrically connected to the active layer T1 of the pixel driving circuit 3.

[0061] For example, combined with Figure 4 and Figure 5 A first via hole H1 is provided in the first gate insulating layer 23 , the second gate insulating layer 24 , the third gate insulating layer 25 and the interlayer dielectric layer 26 , and the initialization signal line 5 is electrically connected to the active layer T1 of the pixel driving circuit 3 through the first via hole H1 .

[0062] See also Figure 4 and Figure 5 The display panel 10 further includes a reset signal line R, which is used to transmit a reset control signal. Exemplarily, the reset signal line R is located at the first gate layer Gate1. The reset signal line R overlaps with the active layer T1 to form a reset transistor. In the initial stage when the pixel driving circuit 3 drives the light-emitting device L, the reset transistor is turned on under the control of the reset control signal. The anode initialization voltage signal (VAR signal) transmitted by the initialization signal line 5 is transmitted to the pixel driving circuit 3 through the reset transistor. The anode initialization voltage signal is transmitted to the anode 30 through the pixel driving circuit 3 to reset the potential of the anode 30, thereby ensuring that the light-emitting device L can emit light normally in the subsequent light-emitting stage.

[0063] The inventor of the present application has found through research that when the display panel is at extremely low brightness, the display screen will produce horizontal line mura. The reason is that Figure 6 As shown, when the touch signal in the touch structure 36 is driven, a quasi-sine noise waveform is generated. There is a parasitic capacitance between the touch structure 36 and the cathode 32 which is close to it. The ELVSS signal in the cathode 32 is affected by the noise waveform and also presents a quasi-sine waveform. In addition, there is a parasitic capacitance between the cathode 32 and the power signal line 4 and the initialization signal line 5. The VAR signal in the initialization signal line 5 is also affected by the waveform of the ELVSS signal and presents a quasi-sine waveform.

[0064] However, since the capacitance (ELVSS-VAR cap) between the cathode 32 and the power signal line 4 and the initialization signal line 5 is small, the VAR signal is less affected by the waveform of the ELVSS signal, and the difference between the equivalent voltage of the VAR signal and the equivalent voltage of the ELVSS signal is large. In the initial stage of the light-emitting device L, multiple rows of sub-pixels 2 are reset row by row through multiple initialization signal lines 5. During the resetting process of one row of sub-pixels 2, the anode 30 of the light-emitting device L in the sub-pixels 2 in this row receives the VAR signal, and the cathode 32 receives the ELVSS signal. The voltage difference (Voled) between the anode 30 and the cathode 32 is large, so that the current (Ioled) in the light-emitting functional layer 31 is large, so that the luminous brightness of this row of sub-pixels 2 is greater than that of other rows of sub-pixels 2, resulting in a brightness difference, that is, horizontal line mura is generated.

[0065] To solve the above problems, in the embodiments of the present application, see Figure 4 and Figure 5 The display panel 10 further includes a plurality of wirings 6, which are disposed on the substrate 20 and are located in the display area A1. Each wiring 6 extends along a first direction X, and the plurality of wirings 6 are arranged along a second direction Y ( Figure 4 and Figure 5 A wiring line 6 is shown in the figure. It can be understood that each row of sub-pixels 2 corresponds to a wiring line 6).

[0066] Figure 7 for Figure 2 A partial enlarged view of the display panel at position N in FIG. Figure 7 , an initialization signal line 5 is electrically connected to a routing line 6.

[0067] Exemplarily, the display panel 10 further includes an initialization signal bus 7 disposed in the peripheral area A2 . The initialization signal bus 7 extends along the second direction Y. Along the first direction X, two initialization signal buses 7 are disposed at opposite sides of the display area A1 .

[0068] The initialization signal line 5 extends from the display area A1 to the peripheral area A2, and is electrically connected to the initialization signal bus 7, and the initialization signal bus 7 is used to transmit the VAR signal to the initialization signal line 5. In addition, the routing line 6 extends from the display area A1 to the peripheral area A2, and is electrically connected to the initialization signal bus 7, that is, the initialization signal line 5 is electrically connected to the routing line 6 through the initialization signal bus 7, and the initialization signal bus 7 is also used to transmit the VAR signal to the routing line 6.

[0069] See also Figure 4 , Figure 5 and Figure 7 The orthographic projection of each routing line 6 on the substrate 20 at least partially overlaps with the orthographic projection of the power signal line 4 on the substrate 20, that is, in the direction Z, the routing line 6 and the power signal line 4 are partially opposite to each other and generate capacitance. Since the routing line 6 transmits the VAR signal and the power signal line 4 transmits the ELVSS signal, the capacitance of the layer where the VAR signal and the ELVSS signal are located is increased without interfering with other signals (ELVSS-VAR cap).

[0070] See also Figure 6 By increasing the capacitance (ELVSS-VAR cap), when the capacitance (ELVSS-VAR cap) is large, the influence of this capacitance on the VAR signal can be appropriately increased, and the influence of the waveform of the ELVSS signal on the waveform of the VAR signal can be increased, and the difference between the equivalent voltage of the VAR signal and the equivalent voltage of the ELVSS signal can be reduced. During the resetting process of a row of sub-pixels 2, the anode 30 of the light-emitting device L in the row of sub-pixels 2 receives the VAR signal, and the cathode 32 receives the ELVSS signal. The voltage difference (Voled) between the anode 30 and the cathode 32 is reduced, so that the current (Ioled) in the light-emitting functional layer 31 is reduced, and the difference in the brightness of the sub-pixels 2 in this row and the sub-pixels 2 in other rows is reduced, thereby improving the phenomenon of displaying lateral line mura.

[0071] In some embodiments, see Figure 7 , the wiring 6 is located in the third gate layer Gate3, the power signal line 4 and the initialization signal line 5 are located in the first source-drain conductive layer SD1, and the initialization signal bus 7 is located in the second source-drain conductive layer SD2.

[0072] It can be understood that in the direction Z, the third gate layer Gate3 and the first source-drain conductive layer SD1 are adjacent conductive layers, and the distance between the third gate layer Gate3 and the first source-drain conductive layer SD1 is small. By setting the wiring 6 in the third gate layer Gate3 and setting the power signal line 4 in the first source-drain conductive layer SD1, the capacitance between the wiring 6 and the power signal line 4 is larger, which helps to improve the phenomenon of display lateral line mura.

[0073] See also Figure 7 A passivation layer 27 and a first planarization layer 28 are interposed between the second source-drain conductive layer SD2 and the first source-drain conductive layer SD1 , and the initialization signal bus 7 penetrates the first planarization layer 28 and the passivation layer 27 and is electrically connected to the initialization signal line 5 .

[0074] Exemplarily, the passivation layer 27 and the first planarization layer 28 are provided with a second via hole H2 penetrating both, and the initialization signal bus 7 is electrically connected to the initialization signal line 5 via the second via hole H2 .

[0075] Continue to see Figure 7 The display panel 10 further includes a first connection pattern 81, which is located in the first source-drain conductive layer SD1, and the initialization signal bus 7 penetrates the first planarization layer 28 and the passivation layer 27 and is electrically connected to the first connection pattern 81. An interlayer dielectric layer 26 is provided between the first source-drain conductive layer SD1 and the third gate layer Gate3, and the first connection pattern 81 penetrates the interlayer dielectric layer 26 and is electrically connected to the trace 6.

[0076] Exemplarily, a third via H3 penetrating the passivation layer 27 and the first planarization layer 28 is further provided, and the initialization signal bus 7 is electrically connected to the first connection pattern 81 via the third via H3. A fourth via H4 is provided in the interlayer dielectric layer 26, and the first connection pattern 81 is electrically connected to the trace 6 via the fourth via H4.

[0077] In some other embodiments, the initialization signal line 5 is located in the first source-drain conductive layer SD1 , and the layer where the power signal line 4 or the routing line 6 is located can be adjusted.

[0078] For example, the layers where the power signal line 4 and the routing line 6 are located are interchanged, the power signal line 4 is located in the third gate layer Gate3, and the routing line 6 is located in the first source-drain conductive layer SD1. Alternatively, the power signal line 4 is located in the first gate layer Gate1, and the routing line 6 is located in the third gate layer Gate3. Alternatively, the power signal line 4 is located in the second gate layer Gate2, and the routing line 6 is located in the third gate layer Gate3. Alternatively, the power signal line 4 is located in the third gate layer Gate3, and the routing line 6 is located in the first gate layer Gate1. Alternatively, the power signal line 4 is located in the third gate layer Gate3, and the routing line 6 is located in the second gate layer Gate2. Alternatively, the power signal line 4 is located in the first source-drain conductive layer SD1, and the routing line 6 is located in the first gate layer Gate1. Alternatively, the power signal line 4 is located in the first source-drain conductive layer SD1, and the routing line 6 is located in the second gate layer Gate2. Alternatively, the power signal line 4 is located in the first gate layer Gate1, and the routing line 6 is located in the first source-drain conductive layer SD1. Alternatively, the power signal line 4 is located in the second gate layer Gate2, and the wiring 6 is located in the first source-drain conductive layer SD1, which is not limited in the present application.

[0079] Figure 8 A local enlarged view of another display panel at M provided in an embodiment of the present application is different from the above-mentioned display panel 10 in that, in some sub-pixels 2, the active layer T1 of the pixel driving circuit 3 is not electrically connected to the initialization signal line 5, but is electrically connected to the wiring 6.

[0080] See also Figure 8 Each row of sub-pixels 2 includes a first sub-pixel 2a, a second sub-pixel 2b and a third sub-pixel 2c, and the first sub-pixel 2a, the second sub-pixel 2b and the third sub-pixel 2c can emit light of different colors.

[0081] As described above, both the initialization signal line 5 and the routing line 6 extend from the display area A1 to the peripheral area A2, and are electrically connected to the initialization signal bus 7, respectively. In the first sub-pixel 2a and the third sub-pixel 2c, the active layer T1 of the pixel driving circuit 3 is electrically connected to the initialization signal line 5 to receive the VAR signal from the initialization signal bus 7 through the initialization signal line 5. In the second sub-pixel 2b, the active layer T1 of the pixel driving circuit 3 is electrically connected to the routing line 6 to receive the VAR signal from the initialization signal bus 7 through the routing line 6.

[0082] It can be understood that the first sub-pixel 2a and the third sub-pixel 2c are both electrically connected to the wiring 6 through the initialization signal bus 7 of the peripheral area A2, and the conductive path between the first sub-pixel 2a and the third sub-pixel 2c and the wiring 6 is farther, while the second sub-pixel 2b is directly electrically connected to the wiring 6 in the display area A1, and the conductive path between the second sub-pixel 2b and the wiring 6 is closer. The capacitance of the VAR signal and the ELVSS signal received by the first sub-pixel 2a and the third sub-pixel 2c is smaller than the capacitance of the VAR signal and the ELVSS signal received by the second sub-pixel 2b. Therefore, the waveform of the ELVSS signal has less influence on the waveform of the VAR signal received by the first sub-pixel 2a and the third sub-pixel 2c, and the waveform of the ELVSS signal has greater influence on the waveform of the VAR signal received by the second sub-pixel 2b, so that Voled and Ioled in the first sub-pixel 2a and the third sub-pixel 2c are larger, and Voled and Ioled in the second sub-pixel 2b are smaller.

[0083] In the case where the luminous efficiency of the first sub-pixel 2a and the third sub-pixel 2c is lower than that of the second sub-pixel 2b, under the driving of the same size of Ioled, the luminous brightness of the first sub-pixel 2a and the third sub-pixel 2c is lower than that of the second sub-pixel 2b. Based on this, by making Voled and Ioled larger in the first sub-pixel 2a and the third sub-pixel 2c and Voled and Ioled smaller in the second sub-pixel 2b, the brightness difference between the first sub-pixel 2a and the third sub-pixel 2c and the second sub-pixel 2b can be reduced, and the phenomenon of displaying horizontal line mura can be further improved.

[0084] Exemplarily, the luminous efficiency of the green sub-pixel is greater than that of the red sub-pixel and the blue sub-pixel. In this case, the first sub-pixel 2a can be set as a red sub-pixel, the second sub-pixel 2b can be set as a green sub-pixel, and the third sub-pixel 2c can be set as a blue sub-pixel.

[0085] In some embodiments, see Figure 8 The initialization signal line 5 is located in the first source-drain conductive layer SD1 , and the first source-drain conductive layer SD1 and the active film layer ACT are separated by a first gate insulating layer 23 , a second gate insulating layer 24 , a third gate insulating layer 25 and an interlayer dielectric layer 26 .

[0086] The initialization signal line 5 passes through the interlayer dielectric layer 26 , the third gate insulating layer 25 , the second gate insulating layer 24 and the first gate insulating layer 23 and is electrically connected to the active layer T1 of the first sub-pixel 2 a .

[0087] Exemplarily, a fifth via hole H5 is provided through the first gate insulating layer 23 , the second gate insulating layer 24 , the third gate insulating layer 25 and the interlayer dielectric layer 26 , and the initialization signal line 5 is electrically connected to the active layer T1 of the first sub-pixel 2 a via the fifth via hole H5 .

[0088] Continue to see Figure 8 The initialization signal line 5 also penetrates the interlayer dielectric layer 26 , the third gate insulating layer 25 , the second gate insulating layer 24 and the first gate insulating layer 23 and is electrically connected to the active layer T1 of the third sub-pixel 2 c .

[0089] Exemplarily, a sixth via hole H6 is further provided through the first gate insulating layer 23, the second gate insulating layer 24, the third gate insulating layer 25 and the interlayer dielectric layer 26, and the initialization signal line 5 is electrically connected to the active layer T1 of the third sub-pixel 2c via the sixth via hole H6.

[0090] See again Figure 8 The display panel 10 further includes a second connection pattern 82, which is also located in the first source-drain conductive layer SD1. The wiring 6 is located in the third gate layer Gate3, and an interlayer dielectric layer 26 is provided between the first source-drain conductive layer SD1 and the third gate layer Gate3.

[0091] The second connection pattern 82 penetrates the interlayer dielectric layer 26 , the third gate insulating layer 25 , the second gate insulating layer 24 and the first gate insulating layer 23 to be electrically connected to the active layer T1 of the second sub-pixel 2 b , and the second connection pattern 82 penetrates the interlayer dielectric layer 26 to be electrically connected to the trace 6 .

[0092] Exemplarily, a seventh via hole H7 is further provided through the first gate insulating layer 23 , the second gate insulating layer 24 , the third gate insulating layer 25 and the interlayer dielectric layer 26 , and the second connection pattern 82 is electrically connected to the active layer T1 of the second sub-pixel 2 b via the seventh via hole H7 .

[0093] In addition, an eighth via hole H8 is provided in the interlayer dielectric layer 26 , and the second connection pattern 82 is electrically connected to the trace 6 via the eighth via hole H8 .

[0094] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: including a display area; The display panel comprises: substrate; A plurality of power signal lines are arranged on the substrate and located in the display area; the power signal lines extend along a first direction, and the plurality of power signal lines are arranged along a second direction, and the second direction intersects the first direction; A plurality of initialization signal lines are disposed on the substrate and located in the display area; the initialization signal lines extend along the first direction, and the plurality of initialization signal lines are arranged along the second direction; A plurality of wirings are arranged on the substrate and located in the display area; the wirings extend along the first direction, and the plurality of wirings are arranged along the second direction; Wherein, one of the initialization signal lines is electrically connected to one of the routing lines; The orthographic projection of the routing line on the substrate at least partially overlaps with the orthographic projection of the power signal line on the substrate.

2. The display panel according to claim 1, characterized in that: The display panel further includes a peripheral area surrounding the display area, and an initialization signal bus disposed in the peripheral area; The initialization signal line extends from the display area to the peripheral area and is electrically connected to the initialization signal bus; The wiring extends from the display area to the peripheral area and is electrically connected to the initialization signal bus.

3. The display panel according to claim 2, characterized in that: The display panel comprises a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer and a third conductive layer which are sequentially stacked on the substrate; The wiring is located in the first conductive layer, the initialization signal line and the power signal line are located in the second conductive layer, and the initialization signal bus is located in the third conductive layer; the display panel further includes a first connection pattern, and the first connection pattern is located in the second conductive layer; The initialization signal bus passes through the second dielectric layer and is electrically connected to the initialization signal line, and the initialization signal bus passes through the second dielectric layer and is electrically connected to the first connection pattern, and the first connection pattern passes through the first dielectric layer and is electrically connected to the routing line.

4. The display panel according to claim 1, characterized in that: The display panel comprises a first gate layer, a second gate layer, a third gate layer and a first source-drain conductive layer which are sequentially stacked on the substrate; The initialization signal line is located in the first source-drain conductive layer; One of the routing line and the power signal line is located in the third gate layer, and the other is located in the first source-drain conductive layer.

5. The display panel according to claim 1, characterized in that: The display panel comprises a first gate layer, a second gate layer, a third gate layer and a first source-drain conductive layer which are sequentially stacked on the substrate; The initialization signal line is located in the first source-drain conductive layer; One of the routing line and the power signal line is located in the first gate layer or the second gate layer, and the other is located in the third gate layer.

6. The display panel according to claim 1, characterized in that: The display panel further comprises a plurality of sub-pixels arranged in an array in the display area, the plurality of sub-pixels comprising a plurality of rows and a plurality of columns, each row of sub-pixels extending along the first direction, and each column of sub-pixels extending along the second direction; The sub-pixel includes a pixel driving circuit; Each row of sub-pixels includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the pixel driving circuits of the first sub-pixel and the third sub-pixel are electrically connected to the initialization signal line, and the pixel driving circuit of the second sub-pixel is electrically connected to the routing line.

7. The display panel according to claim 6, characterized in that: The pixel driving circuit includes an active layer, and the display panel also includes an insulating layer, a first conductive layer, a first dielectric layer, and a second conductive layer which are sequentially stacked on a side of the active layer away from the substrate; The wiring is located in the first conductive layer, and the initialization signal line is located in the second conductive layer; the display panel further includes a second connection pattern, and the second connection pattern is located in the second conductive layer; The initialization signal line passes through the first dielectric layer and the insulating layer to be electrically connected to the active layer of the first sub-pixel, and the initialization signal line passes through the first dielectric layer and the insulating layer to be electrically connected to the active layer of the third sub-pixel; the second connection pattern passes through the first dielectric layer and the insulating layer to be electrically connected to the active layer of the second sub-pixel, and the second connection pattern passes through the first dielectric layer to be electrically connected to the routing.

8. The display panel according to claim 6 or 7, characterized in that: The first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

9. A display device, characterized in that: include: The display panel according to any one of claims 1 to 8; A controller is electrically connected to the display panel.

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