Navigation and time service system based on domestic SoC core platform and multi-source combination

Abstract

The utility model provides a multi-source integrated navigation time service system based on a domestic SoC core platform. The core platform comprises an SoC fusion unit, a DDR unit, a Flash unit, an eMMC unit, a PHY unit and a DC / DC unit, the fusion unit serves as a core composition unit, and an ARM + FPGA framework fusion chip is adopted; the multi-source integrated navigation time service system is based on the core platform and further comprises a Beidou satellite receiver unit and an INS inertial navigation unit. The core platform is high in integration level, is convenient for miniaturization design, and can solve the problem of upgrading and updating of products caused by frequent demand changes. The multi-source combined navigation time service system can solve the problems of low integration level, poor expansibility, incapability of remote upgrading and maintenance and the like of the current navigation product. According to the utility model, the full-localization design is adopted, and the design requirements of data processing speed and logic functions at present are met.

Description

Technical Field

[0001] The utility model belongs to the field of navigation, and particularly relates to a SoC core platform and its navigation timing system. Background Art

[0002] China's Beidou-3 global satellite navigation system has been fully completed, the ground operation and control system has been mature and stable, the chip, antenna and modular design have been basically mature and stable, and the research, development, procurement and application of user terminal products will show an explosive growth trend. Currently, most navigation products are composed of an independent ARM processor and an FPGA logic unit architecture, with an external interface conversion chip. Such an architecture has limitations in terms of high integration, small size, high-speed complex data processing, and expandable application of functions.

[0003] For products that require data processing and logic processing capabilities, there are basically two architectures in the prior art. The first and most common architecture is composed of an ARM processor with a Cortex-M3 or M4 core and an FPGA logic unit chip. The second architecture is composed of an ARM with an ARM7 or ARM9 core and an FPGA logic unit chip. These two technical architectures have the characteristics of low integration and large volume. They can complete simple data processing and logic function implementation, but it is difficult to meet the requirements of small size, high-speed data processing, flexible function expansion, and remote upgrade of FPGA. Summary of the Utility Model

[0004] In view of this, the utility model proposes a domestic-based SoC core platform and a multi-source combined navigation timing system. As an advanced general core platform made in China, the utility model can solve the problems of product upgrade and replacement caused by frequent demand changes, reduce R & D investment, and greatly extend the product life cycle. The multi-source combined navigation timing system described in the utility model can solve the problems of low integration, poor scalability, and inability to be remotely upgraded and maintained in current navigation products.

[0005] A domestic-based SoC core platform includes a SoC fusion unit, a DDR unit, a Flash unit, an eMMC unit, a PHY unit, and a DC / DC unit;

[0006] The SoC fusion unit, as the core component unit, adopts an FMQL45T900 type ARM+FPGA architecture fusion chip;

[0007] The DDR unit includes a DDR chip and its dedicated voltage regulator chip, which are used to realize the on-chip operation of the stored linux system and the dynamic storage of parameters to prevent power loss;

[0008] The Flash unit is used to store the FPGA configuration file of the SoC fusion unit and store the linux kernel file at the same time;

[0009] The eMMC storage unit is used to store Linux system files, parameter configuration files, and data storage files;

[0010] The PHY unit includes multiple PHY chips, and the multiple PHY chips are connected to the GTX high-speed interface of the SoC fusion unit.

[0011] Furthermore, the SoC fusion unit can also select chips of the same series to meet the requirements of product data processing rate, logical resource requirements, number of IO interfaces, and required quality level;

[0012] Furthermore, the DDR chip adopts the DDR3 or DDR3L series, and the dedicated voltage regulator chip adopts the 51200DR series dedicated DDR voltage regulator chip;

[0013] Furthermore, the Flash unit adopts the JFM25QL256 type, or the EFM series and the 128M series in terms of capacity;

[0014] Furthermore, the eMMC storage unit adopts the SMFC32GBMP;

[0015] Furthermore, the DC / DC unit is used to meet the power supply requirements and is implemented by using a multi-channel module or a single-channel multi-chip.

[0016] A multi-source combined navigation and timing system based on a domestic SoC core platform. Based on the described core platform, it further includes a Beidou satellite receiver unit and an INS inertial navigation unit;

[0017] The Beidou satellite receiver is used for satellite navigation, positioning, short message communication, and timing, adopts the OEM form, and is installed on the core motherboard;

[0018] The INS inertial navigation unit is used for fully autonomous navigation and provides position, speed, and carrier attitude information;

[0019] Furthermore, the logic PL part in the fusion chip is used for phase discrimination of the 1PPS timing signal, implementation of the high-speed Serdes interface, NTP / PTP time stamping, serial data parsing, and IRIG-B time encoding and decoding; the PS part in the chip is used for navigation data processing, intelligent network management, PTP algorithm and data processing, NTP timing, online upgrade, time monitoring, ephemeris data processing, timing and timekeeping processing, implementation of the taming algorithm, and system scheduling and operation;

[0020] Furthermore, select the satellite receiver type according to requirements, and select and trim the navigation system according to user requirements or frequency points.

[0021] Furthermore, when used in combination with a satellite navigation system, the INS inertial navigation unit is used for correction when satellite signals are blocked or interfered with in the short term.

[0022] Furthermore, when the fusion chip uses the SGMII interface, data transmission is directly achieved by externally connecting termination matching capacitors at the fusion chip; when the fusion chip uses a high-speed interface, a corresponding matching clock source is selected according to the port rate and connected to the corresponding bank; when selecting a PHY chip, a corresponding model of PHY chip is selected according to the number of network interface ports.

[0023] Beneficial effects

[0024] 1. The present utility model first proposes the composition of the core platform, which has a high integration level and is convenient for miniaturized design;

[0025] 2. The present utility model first applies the core platform to the fields of navigation and timing;

[0026] 3. The present utility model first proposes the design of the core platform for network interface applications;

[0027] 4. The present utility model adopts a fully domestic design, which is suitable for current systems with data processing speed and logic function design, and has performance redundancy, facilitating function and performance upgrades.

[0028] 5. The present utility model has been productized. Description of the drawings

[0029] Figure 1 It is the system block diagram of the present utility model Detailed implementation manners

[0030] A multi-source combined navigation and timing system based on a domestic SoC core platform proposed by the present utility model is composed of an SoC fusion unit, a DDR unit, a Flash unit, an eMMC unit, a PHY unit, a Beidou satellite receiver unit, an INS inertial navigation unit and a DC / DC unit. The implementation block diagram is as shown in the figure:

[0031] (1) SoC fusion unit

[0032] Currently, there are very few options for domestic SoC architecture chips. This system uses the FMQL45T900 type ARM+FPGA architecture fusion chip developed and produced by Shanghai Fudan Microelectronics Group Co., Ltd. as the core component unit of the platform. When designing the system using this method, chips of the same series can be selected according to the data processing rate, logic resource requirements, number of IO interfaces and required quality level of its own products.

[0033] This system uses the logic PL part of the chip to perform phase detection of 1PPS signal, high-speed Serdes interface implementation, NTP / PTP time stamping, serial port data analysis and IRIG-B time encoding and decoding; the PS part is used for navigation data processing, intelligent network management, PTP algorithm and data processing, NTP timing, online upgrade, time monitoring, ephemeris data processing, timing and punctuality processing, taming algorithm implementation, system scheduling and operation and other functions.

[0034] (II) DDR unit

[0035] It is composed of DDR chip and its dedicated voltage regulator chip. There are relatively few domestic manufacturers to choose from, including Unigroup Guoxin, Unigroup Guoxin, etc. The current mainstream choices are DDR3 and DDR3L series, which mainly realize the on-chip operation and dynamic storage of parameters of the stored Linux system. The data will be lost in the event of power failure. The voltage regulator power supply is implemented using the 51200DR series dedicated DDR voltage regulator chip.

[0036] (III) Flash unit

[0037] It provides storage for the FPGA configuration files of the SoC core unit and also stores the Linux kernel files. It has a chip identification code and has restrictions on the manufacturer and model. This system uses the JFM25QL256 model developed and produced by Shanghai Fudan Microelectronics Group Co., Ltd. It is also applicable to the EFM series and the 128M series. You need to choose the design according to your own needs. The model with quality grade has high reliability design characteristics.

[0038] (IV) eMMC unit

[0039] The eMMC storage unit is a packaged memory that integrates a controller, a flash memory chip, and a flash memory interface. The Shenzhen Guowei SMFC32GBMP used in this system is used to store Linux system files, parameter configuration files, and data storage files. It has the function of storing LDPC error correction, uses a standard interface, and has the characteristics of wide temperature, large capacity, and long life.

[0040] (V) PHY unit

[0041] At present, the 1000M rate network in the communication industry usually uses the network interface conversion method to connect the MAC layer with the PHY chip using RGMII. The interfaces are numerous and the wiring requirements are complex. When used for multiple network ports, the design is even more complicated. This system uses the GTX high-speed interface of the SoC core chip to connect to the domestic 4-way PHY chip. The PHY chip supports SGMII and Base-T interface conversion. Single-way conversion can simplify the connection from 12 to 4. There are 8 network ports in this system, which greatly reduces the use of core unit IO.

[0042] When the SGMII interface is used in the system, it can be directly implemented by externally connecting termination matching capacitors at the core unit. When using high-speed interfaces, the corresponding clock source that matches the port rate needs to be selected and connected to the corresponding bank. When selecting a PHY chip, the corresponding model of PHY chip can be selected according to the number of network interfaces, greatly saving costs and product design complexity.

[0043] (6) Beidou satellite receiver

[0044] Most current domestic navigation receivers support the compatible use of the world's four major navigation systems, namely the US GPS, Russian GLONASS, European GALILEO, and Chinese BDS. The forms of satellite receivers are divided into chip level, module level, and OEM module level. The navigation baseband chip of this system is independently designed in the OEM form and installed on the core motherboard, which is convenient for modular design and use. At the same time, it supports the compatible use of civilian codes and authorized signals, and realizes functions such as satellite navigation, positioning, short message communication, and timing. When using this method, the navigation system can be selected according to user requirements or frequency points. Whether to support the short message receiver and trim the corresponding hardware and software designs can be selected according to whether the short message communication function is required. According to the designed product, the receiver with a particular functional emphasis can be selected. For example, if the key functions of the system are navigation and positioning, a receiver with excellent navigation and positioning performance can be selected; if the key function of the system is timing, a timing receiver can be selected.

[0045] (7) INS inertial navigation unit

[0046] The INS inertial navigation system is a relatively independent and fully autonomous navigation system that can output high-frequency signals of over 200 Hz and has high short-term measurement accuracy, providing position, velocity, and carrier attitude information. However, due to the integration in its internal algorithm, the integration error of inertial sensors will continuously accumulate, causing the long-term navigation error to increase without limit. When combined with a satellite navigation system in the system, it has good long-term accuracy retention. In case of satellite signal occlusion or interference in the short term, the INS inertial navigation can be used for correction, forming a good complementary characteristic, which plays an important role in improving the stability and continuity of the system.

[0047] (8) DC / DC unit

[0048] The core unit has strict requirements for its power supply, involving multiple different power consumption requirements. The use of the IO ports of some BANKs is different, and the power supply is also different. The main power supplies are 1V0, 1V2, 1V8, 2V5, and 3V3, which can be implemented using multiple modules or single-path multiple chips. In this system, the HCE4644 type DC / DC chip of North China Technology is adopted. A single chip supports 4-way 4A output. Each channel can be used independently or selectively in parallel. It has a wide input voltage range of 4V to 14V, and at the same time supports a wide temperature range of -55°C to +125°C for the working environment, which can meet the product design requirements with a high-temperature working environment. When designing, because it is a high-power device, attention should be paid to derating at high temperatures. Increasing the copper thickness, copper foil area, and the number of vias of the PCB can enhance the heat dissipation ability of the device.

[0049] The following explanations are made for the above description:

[0050] 1. The content in the assumption is for illustrative purposes and does not serve as a usage restriction condition.

[0051] 2. The Beidou Navigation System is used as the basis in this utility model, and other applications within the Beidou Navigation System are also within the scope of protection;

[0052] 3. The FMQL45T900 type SoC is used in this utility model, and the same applies to the selection of models in its same series, which is also within the scope of protection;

[0053] 4. This utility model involves a combination of multiple domestic chip devices, and the same type of series chips are also applicable and within the scope of protection;

[0054] 5. The SGMII network conversion and PTP / NTP implementation framework in this utility model are also within the scope of protection if the methods are the same.

[0055] 6. Currently, there are few documents on the design of multi-source integrated navigation systems based on domestic SoC core platforms. The relevant terms in this utility model can be found through web pages.

Claims

1. A domestically produced SoC core platform, characterized by: Including SoC fusion unit, DDR unit, Flash unit, eMMC storage unit, PHY unit, and DC / DC unit; The SoC fusion unit is used as a core component unit, and adopts the FMQL45T900 ARM+FPGA architecture fusion chip; The DDR unit includes a DDR chip and a dedicated voltage regulator chip, which are used to realize the on-chip operation of the stored Linux system and the dynamic storage of parameters to prevent power failure and loss; The Flash unit is used to provide storage for the FPGA configuration file of the SoC fusion unit and store the Linux kernel file at the same time; The eMMC storage unit is used to store Linux system files, parameter configuration files and data storage files; The PHY unit includes a plurality of PHY chips, and the plurality of PHY chips are connected to the GTX high-speed interface of the SoC fusion unit.

2. According to claim 1, a domestically produced SoC core platform is characterized in that: The SoC fusion unit can also select chips from the same series to meet the product data processing rate, logic resource requirements, IO interface quantity and required quality level requirements; The DDR chip adopts DDR3 or DDR3L series, and the dedicated voltage regulator chip adopts 51200DR series dedicated DDR voltage regulator chip; The Flash unit adopts JFM25QL256 type, or EFM series and 128M series; The eMMC storage unit adopts SMFC32GBMP; The DC / DC unit is used to meet power supply requirements and is implemented using a multi-channel module or a single-channel multi-chip.

3. A multi-source integrated navigation and timing system based on a domestic SoC core platform, based on the core platform described in claim 1 or 2, characterized in that: It also includes a BeiDou satellite receiver unit and an INS inertial navigation unit; The Beidou satellite receiver is used for satellite navigation, positioning, short message communication and timing, adopts OEM form, and is installed on the core motherboard; The INS inertial navigation unit is used for fully autonomous navigation and provides position, speed and carrier attitude information.

4. The multi-source integrated navigation and timing system based on the domestic SoC core platform according to claim 3 is characterized in that: When used in conjunction with a satellite navigation system, the INS inertial navigation unit is used to make corrections when satellite signals are blocked or interfered with in the short term.

5. The multi-source integrated navigation and timing system based on the domestic SoC core platform according to claim 4 is characterized in that: When the fusion chip uses the SGMII interface, data transmission is achieved directly by connecting the external termination matching capacitors of the fusion chip. When the fusion chip uses the high-speed interface, the corresponding matching clock source is selected according to the port rate and connected to the corresponding bank. When selecting the PHY chip, the corresponding model of PHY chip is selected according to the number of network ports.

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