Software rapid development and verification platform under DSP + FPGA architecture

Abstract

The utility model provides a software rapid development and verification platform under a DSP + FPGA architecture, and belongs to the technical field of embedded computers, the software rapid development and verification platform specifically comprises a DSP daughter card, a substrate, a PC and a cable, the substrate is provided with a power supply module, a DSP daughter card slot, a communication module, a first FPGA and a second FPGA, the DSP daughter card is connected with the DSP daughter card slot, the DSP daughter card slot, the second FPGA, the first FPGA and the PC are sequentially connected through the cable, and the DSP daughter card slot is connected with the communication module. The DSP daughter card slot is further connected with one end of the communication module through a cable, the other end of the communication module is connected with the PC through a cable, and the power module is used for supplying power to the DSP daughter card slot, the first FPGA, the second FPGA and the communication module. Through the processing scheme of the invention, the embedded computer has the capabilities of rapid development, advanced debugging and timely verification of DSP (Digital Signal Processor) software.

Description

Technical Field

[0001] This application relates to the field of embedded computer technology, and in particular to a rapid software development and verification platform based on a DSP+FPGA architecture. Background Technology

[0002] An embedded computer is an application-centric, computer technology-based, and customizable hardware and software computer designed for application systems with stringent requirements regarding functionality, reliability, cost, size, and power consumption. It typically consists of four parts: an embedded microprocessor, peripheral hardware devices, an embedded operating system, and user applications. The embedded microprocessor and peripheral hardware devices constitute the hardware subsystem, while the operating system and applications constitute the software subsystem. The hardware subsystem is the foundation for the embedded computer's software environment, providing the physical platform and communication interfaces for its operation. The application software and operating system are the control core of the entire computer, controlling its operation and providing human-computer interaction information. Generally, the development process of an embedded computer is divided into two steps: hardware development and software development. Software development is typically conducted after hardware production and debugging, which is not conducive to software development, debugging, and verification. Utility Model Content

[0003] In view of this, this application provides a rapid software development and verification platform under a DSP+FPGA architecture to solve the technical problem that embedded computers under the existing DSP+FPGA architecture cannot quickly develop, debug and verify DSP software before hardware resources are available.

[0004] This application provides a rapid software development and verification platform based on a DSP+FPGA architecture. The platform includes a DSP daughter card, a base plate, a PC, and cables. The base plate is provided with a power module, a DSP daughter card slot, a communication module, a first FPGA, and a second FPGA. The DSP daughter card is connected to the DSP daughter card slot. The DSP daughter card slot, the second FPGA, the first FPGA, and the PC are sequentially connected via the cables. The DSP daughter card slot is also connected to one end of the communication module via the cables, and the other end of the communication module is connected to the PC via the cables. The power module supplies power to the DSP daughter card slot, the first FPGA, the second FPGA, and the communication module.

[0005] According to one specific implementation of an embodiment of this application, the DSP daughter card includes a DSP chip, a clock circuit, a reset circuit, and a JTAG emulation and debugging interface.

[0006] According to a specific implementation of an embodiment of this application, the DSP daughter card is provided with pins, which are used to bring out the pins of the DSP chip. The DSP daughter card slot is provided with sockets, and the pins correspond one-to-one with the sockets. Pins with the same function on different DSP chips are brought out through the same pin.

[0007] According to a specific implementation of an embodiment of this application, the first FPGA is electrically connected to the motherboard in the PC via a PCIe cable; the communication module is electrically connected to the communication board in the PC via a communication cable.

[0008] According to a specific implementation of an embodiment of this application, the DSP daughter card is provided with a 3.3V power supply interface and a 1.8V power supply interface, and 1.8V and 3.3V power should be provided to the DSP daughter card through the DSP daughter card slot.

[0009] According to a specific implementation of an embodiment of this application, a pull-up / pull-down circuit is provided around the DSP daughter card slot, and the pull-up / pull-down configuration function of the DSP daughter card IO port is realized through the pull-up / pull-down circuit.

[0010] According to a specific implementation of an embodiment of this application, the power module converts a wide range of input DC power into the DC power required by the substrate, wherein the DC power required by the substrate includes 1.5V, 1.8V, 2.5V, 3.3V and 5V.

[0011] According to a specific implementation of an embodiment of this application, the external device interface of the DSP daughter card is connected to the second FPGA through the DSP daughter card slot.

[0012] Beneficial effects:

[0013] This application provides a rapid software development and verification platform under a DSP+FPGA architecture, comprising a DSP daughter card, a baseboard, a PC, and cables. The baseboard includes a power module, a DSP daughter card slot, a communication module, a first FPGA1, and a second FPGA. Through the design of the above-mentioned development and verification platform, the embedded computer under the DSP+FPGA architecture has the ability to rapidly develop, debug, and verify DSP software in advance, thus solving the technical problem that existing embedded computers under the DSP+FPGA architecture cannot rapidly develop, debug, and verify DSP software before hardware resources are available. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a structural diagram of a DSP+FPGA architecture-based rapid software development and verification platform according to an embodiment of the present invention. Detailed Implementation

[0016] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0017] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0019] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described may be practiced without these specific details.

[0021] The DSP+FPGA architecture is a commonly used embedded computer hardware subsystem architecture, which has a wide range of applications in industrial control, image processing, signal processing and other fields.

[0022] To address the shortcomings of existing DSP+FPGA architecture-based embedded computer DSP software development, debugging, and verification, a rapid software development and verification platform for DSP+FPGA architecture is needed. This platform would enable embedded computers with DSP+FPGA architecture to rapidly develop, debug, and verify DSP software in advance, thus solving the technical problem that existing DSP+FPGA architecture-based embedded computers cannot quickly develop, debug, and verify DSP software before hardware resources are available.

[0023] Therefore, this application provides a rapid software development and verification platform based on a DSP+FPGA architecture, as described below. Figure 1 The platform includes a DSP daughter card, a base plate, a PC, and cables. The base plate is equipped with a power module, a DSP daughter card slot, a communication module, a first FPGA, and a second FPGA. The DSP daughter card includes a DSP chip, a clock circuit, a reset circuit, and a JTAG emulation and debugging interface. The DSP daughter card is connected to the DSP daughter card slot. The DSP daughter card slot, the second FPGA, the first FPGA, and the PC are sequentially connected via the cables. The DSP daughter card slot is also connected to one end of the communication module via the cables, and the other end of the communication module is connected to the PC via the cables. The power module supplies power to the DSP daughter card slot, the first FPGA, the second FPGA, and the communication module.

[0024] In one embodiment, the DSP daughter card is provided with pins for bringing out the pins of the DSP chip. The DSP daughter card slot is provided with sockets, and the pins correspond one-to-one with the sockets. Pins with the same function on different DSP chips are brought out through the same pin. Specifically, the DSP daughter card brings out all the I / O ports of the DSP chip, and the I / O port definitions of the DSP daughter card are compatible with the standard definitions of the DSP daughter card slots in the substrate.

[0025] In one embodiment, the first FPGA is electrically connected to the motherboard of the PC via a PCIe cable; the communication module is electrically connected to the communication board of the PC via a communication cable.

[0026] Specifically, the substrate and the PC have at least two electrical connections: one is the electrical connection between the FPGA1 on the substrate and the motherboard in the PC via a PCIe cable; the other is the electrical connection between the communication module on the substrate and the communication board in the PC via a communication cable.

[0027] In one embodiment, the DSP daughter card is provided with a 3.3V power supply interface and a 1.8V power supply interface. The DSP daughter card slot is defined in a standard way, and 1.8V and 3.3V power should be provided to the DSP daughter card through the DSP daughter card slot.

[0028] In one embodiment, pull-up / pull-down circuits are provided around the DSP daughter card slot to enable pull-up / pull-down configuration of the DSP daughter card's I / O ports.

[0029] In one embodiment, the power module converts a wide range of input DC power into the DC power required by the substrate, including 1.5V, 1.8V, 2.5V, 3.3V, and 5V.

[0030] In one embodiment, the external device interface of the DSP daughter card is connected to the second FPGA via the DSP daughter card slot.

[0031] In practical implementation, the second FPGA allocates several I / O ports as external bus interfaces and connects to the DSP daughter card slot. I / O ports in the second FPGA not allocated as external bus interfaces are connected to the first FPGA. The first FPGA allocates several I / O ports as PCIe bus interfaces, and I / O ports in the first FPGA not allocated as PCIe interfaces are connected to the first FPGA. The communication module supports multiple external communication methods.

[0032] The PC has an external PCIe interface, which connects to the first FPGA on the substrate. The PC supports all communication modes of the communication module on the substrate. The PC is also connected to the communication module on the substrate via an external communication interface.

[0033] The embodiments provided by this utility model provide a rapid software development and verification platform under the DSP+FPGA architecture, which mainly includes a DSP daughter card, a base plate, a PC, and cables. The base plate includes a power module, a DSP daughter card slot, a communication module, a first FPGA1, and a second FPGA. Through the above-mentioned development and verification platform design, the embedded computer under the DSP+FPGA architecture has the ability to rapidly develop, debug, and verify DSP software in advance, thus solving the technical problem that the existing embedded computer under the DSP+FPGA architecture cannot quickly develop, debug, and verify DSP software before hardware resources are available.

[0034] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A rapid software development and verification platform based on a DSP+FPGA architecture, characterized in that, The platform includes a DSP daughter card, a base plate, a PC, and cables. The base plate is provided with a power module, a DSP daughter card slot, a communication module, a first FPGA, and a second FPGA. The DSP daughter card is connected to the DSP daughter card slot. The DSP daughter card slot, the second FPGA, the first FPGA, and the PC are connected sequentially via the cables. The DSP daughter card slot is also connected to one end of the communication module via the cables, and the other end of the communication module is connected to the PC via the cables. The power module is used to supply power to the DSP daughter card slot, the first FPGA, the second FPGA, and the communication module.

2. The rapid software development and verification platform under the DSP+FPGA architecture according to claim 1, characterized in that, The DSP daughter card includes a DSP chip, a clock circuit, a reset circuit, and a JTAG emulation and debugging interface.

3. The rapid software development and verification platform under the DSP+FPGA architecture according to claim 2, characterized in that, The DSP daughter card is provided with pins for bringing out the pins of the DSP chip. The DSP daughter card slot is provided with sockets, and the pins correspond one-to-one with the sockets. Pins with the same function on different DSP chips are brought out through the same pin.

4. The rapid software development and verification platform under the DSP+FPGA architecture according to claim 1, characterized in that, The first FPGA is electrically connected to the motherboard of the PC via a PCIe cable; the communication module is electrically connected to the communication board of the PC via a communication cable.

5. The rapid software development and verification platform under the DSP+FPGA architecture according to claim 1, characterized in that, The DSP daughter card is equipped with a 3.3V power supply interface and a 1.8V power supply interface. 1.8V and 3.3V power should be supplied to the DSP daughter card through the DSP daughter card slot.

6. The rapid software development and verification platform under the DSP+FPGA architecture according to claim 1, characterized in that, Pull-up and pull-down circuits are provided around the DSP daughter card slot to enable pull-up and pull-down configuration of the DSP daughter card I / O ports.

7. The rapid software development and verification platform under the DSP+FPGA architecture according to claim 1, characterized in that, The power module converts a wide range of input DC power into the DC power required by the substrate, which includes 1.5V, 1.8V, 2.5V, 3.3V and 5V.

8. The rapid software development and verification platform under the DSP+FPGA architecture according to claim 1, characterized in that, The external device interface of the DSP daughter card is connected to the second FPGA through the DSP daughter card slot.

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