Laminated circuit structure and power module

Abstract

The utility model relates to a laminated circuit structure and a power module. The laminated circuit structure comprises a substrate, a first chip group, a second chip group and a circuit structure. The first chip set and the second chip set are arranged on one side of the substrate, the first chip set comprises a first chip, the second chip set comprises a second chip, and the circuit structure is arranged on one side, away from the substrate, of the first chip set or the second chip set and comprises a first conductive part, an insulating layer and a second conductive part which are stacked in the direction away from the substrate. Wherein the first chip, the first conductive piece, the second chip and the second conductive piece are sequentially connected in series. According to the laminated circuit structure, the parasitic inductance of the first conductive part and the parasitic inductance of the second conductive part can be counteracted due to opposite current directions when the first conductive part and the second conductive part carry current, so that the whole loop has lower inductance performance, and the parasitic inductance of the laminated circuit structure can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of power modules, and in particular, to a stacked circuit structure and a power module. Background Art

[0002] In related technologies, based on the current-carrying requirements of large currents in power modules, a single-layer large-area copper metal sheet is usually used as the main structure for electrical connection of power modules. However, this results in a relatively high parasitic inductance in the loop where the copper metal sheet is located. Summary of the Invention

[0003] Based on this, it is necessary to provide a stacked circuit structure and a power module for the problem of relatively high parasitic inductance in the loop where the single-layer large-area copper metal sheet is located.

[0004] According to a first aspect of the present application, a stacked circuit structure is provided. The stacked circuit structure includes:

[0005] A substrate;

[0006] A first chip group and a second chip group, provided on one side of the substrate; the first chip group includes a first chip, and the second chip group includes a second chip; and

[0007] A circuit structure, provided on the side of the first chip group or the second chip group facing away from the substrate, and including a first conductive member, an insulating layer, and a second conductive member stacked in a direction away from the substrate;

[0008] Wherein, the first chip, the first conductive member, the second chip, and the second conductive member are sequentially connected in series.

[0009] In one embodiment, the substrate includes a first conductive layer, and the first conductive layer includes an electrical input portion, an electrical transfer portion, and an electrical output portion that are electrically isolated from each other;

[0010] The first chip group is provided on one side of the electrical input portion, and the second chip group is provided on one side of the electrical transfer portion;

[0011] Both the first chip and the second chip include a first electrode and a second electrode. The electrical input portion is electrically connected to the first electrode of the first chip, and the second electrode of the first chip is electrically connected to the electrical transfer portion through the first conductive member; the electrical transfer portion is electrically connected to the first electrode of the second chip, and the second electrode of the second chip is electrically connected to the electrical output portion through the second conductive member.

[0012] In one embodiment, the first chip group includes a plurality of the first chips;

[0013] The first conductive member includes a first conductive body and a plurality of first conductive legs connected to the first conductive body at one end, and the other ends of the first conductive legs are electrically connected to the first chip in a one-to-one correspondence.

[0014] In one of the embodiments, the second chipset includes a plurality of the second chips;

[0015] The second conductive member includes a second conductive body and a plurality of second conductive legs connected to the second conductive body at one end, and the other ends of the second conductive legs are electrically connected to the second chip in a one-to-one correspondence.

[0016] In one embodiment, the electrical input portion and the electrical switching portion are spaced apart along a first direction;

[0017] The electrical output portion and at least a portion of the electrical input portion are spaced apart along a second direction;

[0018] The first direction and the second direction are perpendicular to each other, and are both perpendicular to the thickness direction of the substrate.

[0019] In one embodiment, the electrical input portion is provided with two first receiving grooves spaced apart along the second direction, the first conductive layer further includes two first insulating portions corresponding to the two first receiving grooves one by one, and the first insulating portions are arranged in the corresponding first receiving grooves;

[0020] Each of the first insulating parts is provided with a second receiving groove, and the electrical output part includes two sub-output parts corresponding to the two second receiving grooves one by one, and the sub-output parts are arranged in the corresponding second receiving grooves.

[0021] In one embodiment, the size of the electrical input portion along the first direction is equal to the size of the electrical switching portion along the first direction;

[0022] The dimension of the electrical input portion along the second direction is equal to the dimension of the electrical switching portion along the second direction.

[0023] In one of the embodiments, a plurality of first via holes are provided on the first conductive member;

[0024] The insulating layer is provided with a plurality of second via holes corresponding one-to-one to the plurality of first via holes;

[0025] The first via hole is connected to the corresponding second via hole;

[0026] The second conductive member includes second conductive legs corresponding to the second chips one by one. The second conductive legs pass through the corresponding second via holes and the corresponding first via holes and are electrically connected to the corresponding second chips.

[0027] In one embodiment, the thickness of the insulating layer is D0, where D0 ≥ 0.1 mm; and / or

[0028] the thickness of the first conductive member is D1, where D1 ≥ 0.1 mm; and / or

[0029] the thickness of the second conductive member is D2, where D2 ≥ 0.3 mm.

[0030] According to a second aspect of the present application, there is provided a power module including the stacked circuit structure of any one of the above embodiments.

[0031] In the technical solution of the present application, since the first conductive member and the second conductive member are stacked, in the series loop formed by the first chip, the first conductive member, the second chip, and the second conductive member, if the current flows in from the first chip, it will then flow into the first conductive member and the second chip, and then flow out from the second conductive member; if the current flows in from the second conductive member, it will then flow into the second chip and flow out through the first conductive member and the first chip; in both of the above cases, the direction of the current flowing through the first conductive member is opposite to the direction of the current flowing through the second conductive member, thereby causing the parasitic inductances of the first conductive member and the second conductive member to cancel each other out due to the opposite current directions when carrying current, and further enabling the entire loop to have a lower inductance performance, which is beneficial to reducing the parasitic inductance of the stacked circuit structure; in addition, since the insulating layer is disposed between the first conductive member and the second conductive member, the situation of short circuit in the loop where the stacked first conductive member and second conductive member are located can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Shows a schematic structural diagram of a stacked circuit structure in an embodiment of the present application.

[0033] Figure 2 Shows a top view of a stacked circuit structure in an embodiment of the present application.

[0034] Figure 3 Shows a top view of a first conductive layer in an embodiment of the present application.

[0035] Figure 4 Shows a side view of a first conductive member in an embodiment of the present application.

[0036] Figure 5 Shows a top view of a first conductive member in an embodiment of the present application.

[0037] Figure 6 Shows a top view of a substrate, a first chip group, and a second chip group in an embodiment of the present application.

[0038] Figure 7 Shows a side view of a second conductive member in an embodiment of the present application.

[0039] Figure 8 A top view of a second conductive member in an embodiment of the present application is shown.

[0040] Figure 9 A top view of an insulating layer in an embodiment of the present application is shown.

[0041] Figure numerals: 10, laminated circuit structure; 100, substrate; 110, first conductive layer; 111, electric input unit; 112, electric switching unit; 113, electric output unit; 1131, sub-output unit; 114, first insulating unit; 115, second insulating unit; 120, second conductive layer; 130, ceramic layer; 210, first chipset; 211, first chip; 220, second chipset; 221, second chip; 300, circuit structure; 310, first conductive unit Component; 311, first conductive body; 3111, first via hole; 312, first conductive foot; 313, first transfer foot; 320, second conductive component; 321, second conductive body; 322, second conductive foot; 323, second transfer foot; 330, insulating layer; 331, second via hole; C1, first receiving groove; C2, second receiving groove; 410, first silver paste layer; 420, second silver paste layer; 510, first solder layer; 520, second solder layer. DETAILED DESCRIPTION

[0042] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0043] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0044] In addition, if the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0045] In this application, unless otherwise clearly specified and defined, if terms such as "installed", "connected", "joined", "fixed", etc. appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0046] In this application, unless otherwise clearly specified and defined, if there is a description such as a first feature being "on" or "under" a second feature, the meaning can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature can be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature can be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0047] It should be noted that if an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there can also be an intermediate element. If an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. If so, the terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used in this application are only for the purpose of illustration and do not represent the only implementation manner.

[0048] Figure 1 The structural schematic diagram of the stacked circuit structure in an embodiment of this application is shown. Figure 2 The top view of the stacked circuit structure in an embodiment of this application is shown.

[0049] Please refer to Figure 1 and Figure 2, an embodiment of the present application provides a stacked circuit structure 10, including a substrate 100, a first chip group 210, a second chip group 220, and a circuit structure 300.

[0050] The first chip group 210 and the second chip group 220 are disposed on one side of the substrate 100, and the first chip group 210 includes a first chip 211, and the second chip group 220 includes a second chip 221. The circuit structure 300 is disposed on the side of the first chip group 210 or the second chip group 220 away from the substrate 100, and the circuit structure 300 includes a first conductive member 310, an insulating layer 330, and a second conductive member 320 stacked in a direction away from the substrate 100. The first chip 211, the first conductive member 310, the second chip 221, and the second conductive member 320 are sequentially connected in series.

[0051] Exemplarily, the materials of the first conductive member 310 and the second conductive member 320 are both copper.

[0052] Since the first conductive member 310 and the second conductive member 320 are stacked, in the series circuit formed by the first chip 211, the first conductive member 310, the second chip 221, and the second conductive member 320, if the current flows in from the first chip 211, it will then flow into the first conductive member 310 and the second chip 221, and then flow out from the second conductive member 320; if the current flows in from the second conductive member 320, it will then flow into the second chip 221 and flow out through the first conductive member 310 and the first chip 211; in both of the above cases, the direction of the current flowing through the first conductive member 310 is opposite to the direction of the current flowing through the second conductive member 320, thereby causing the parasitic inductances of the first conductive member 310 and the second conductive member 320 to cancel each other out due to the opposite current directions when carrying current, and further enabling the entire circuit to have a lower inductance performance, which is beneficial to reducing the parasitic inductance of the stacked circuit structure 10; in addition, since the insulating layer 330 is disposed between the first conductive member 310 and the second conductive member 320, the situation of short circuit in the circuit where the first conductive member 310 and the second conductive member 320 are stacked can be reduced.

[0053] In some embodiments, as Figure 3 shown, the substrate 100 includes a first conductive layer 110, and the first conductive layer 110 includes an electrical input portion 111, an electrical transfer portion 112, and an electrical output portion 113 that are electrically isolated from each other. The first chip group 210 is disposed on one side of the electrical input portion 111, and the second chip group 220 is disposed on one side of the electrical transfer portion 112.

[0054] Both the first chip 211 and the second chip 221 include a first electrode and a second electrode. Specifically, the first electrode is disposed on the back surface of the first chip 211 or the second chip 221, and the first electrode is a drain electrode. The second electrode is disposed on the front surface of the first chip 211 or the second chip 221, and the second electrode is a source electrode. Among them, the back surface of the first chip 211 is the side surface of the first chip 211 close to the electrical input portion 111, and the front surface of the first chip 211 is the side surface of the first chip 211 far from the electrical input portion 111; similarly, the back surface of the second chip 221 is the side surface of the first chip 211 close to the electrical transfer portion 112, and the front surface of the second chip 221 is the side surface of the first chip 211 far from the electrical transfer portion 112.

[0055] The electrical input portion 111 is electrically connected to the first electrode of the first chip 211, and the second electrode of the first chip 211 is electrically connected to the electrical transfer portion 112 through the first conductive member 310; the electrical transfer portion 112 is electrically connected to the first electrode of the second chip 221, and the second electrode of the second chip 221 is electrically connected to the electrical output portion 113 through the second conductive member 320.

[0056] Optionally, the first electrode of the first chip 211 is electrically connected to the electrical input portion 111 through the first silver paste layer 410, and the first chip 211 can be assembled on the substrate 100 through a silver sintering process.

[0057] Optionally, the first electrode of the second chip 221 is electrically connected to the electrical transfer portion 112 through the second silver paste layer 420, and the second chip 221 can be assembled on the substrate 100 through a silver sintering process.

[0058] In this way, current can flow into the first chip 211 through the electrical input portion 111, then flow to the second chip 221 through the first conductive member 310 and the electrical transfer portion 112, and finally flow out through the second conductive member 320 and the electrical output portion 113. During this process, the parasitic inductances of the first conductive member 310 and the second conductive member 320 can be offset from each other due to the opposite current directions when carrying current, which is beneficial to reducing the parasitic inductance of the stacked circuit structure 10 while also reducing the occurrence of short circuits in the loop where the first conductive member 310 and the second conductive member 320 are stacked.

[0059] In some embodiments, the first chip group 210 includes a plurality of first chips 211, such as Figure 4 and Figure 5 shown, the first conductive member 310 includes a first conductive main body portion 311 and a plurality of first conductive leg portions 312 connected to one end of the first conductive main body portion 311, and the other ends of the first conductive leg portions 312 are electrically connected to the first chips 211 one by one. Specifically, the first conductive leg portions 312 are connected to the side of the first conductive main body portion 311 close to the substrate 100.

[0060] That is to say, the first conductive leg portions 312 correspond to the first chips 211 one by one.

[0061] Specifically, the number of the first chips 211 is even, and the number of the first conductive leg portions 312 is also even. Two first chips 211 form a group of first chip subgroups, and two first conductive leg portions 312 form a group of first conductive leg groups. A group of first conductive leg groups is arranged in a figure-eight shape on the first conductive main body portion 311.

[0062] Exemplarily, as Figure 6 shown, the number of the first chips 211 is eight, as Figure 5 shown, the number of the first conductive leg portions 312 is also eight.

[0063] Optionally, the first conductive leg portions 312 are electrically connected to the second electrodes of the corresponding first chips 211 through the first solder layer 510. Of course, the present application is not limited thereto, and the second electrodes of the first chips 211 can also be electrically connected to the corresponding first conductive leg portions 312 through other welding processes such as silver sintering process or copper sintering.

[0064] In this way, it is convenient to use the first conductive member 310 to connect multiple first chips 211 in parallel between the electrical input portion 111 and the first conductive member 310.

[0065] In this embodiment, the first conductive member 310 further includes a plurality of first adapter pins 313 connected to the side of the first conductive main body portion 311 close to the substrate 100. The plurality of first adapter pins 313 are respectively electrically connected to the electrical adapter portion 112, which facilitates the electrical connection between the first conductive member 310 and the electrical adapter portion 112.

[0066] In some embodiments, the second chip group 220 includes a plurality of second chips 221, as Figure 7 and Figure 8 shown. The second conductive member 320 includes a second conductive main body portion 321 and a plurality of second conductive leg portions 322 connected to one end of the second conductive main body portion 321. The other ends of the second conductive leg portions 322 are electrically connected to the second chips 221 one by one.

[0067] That is to say, the second conductive leg portions 322 correspond to the second chips 221 one by one.

[0068] Specifically, the number of the second chips 221 is even, and the number of the second conductive leg portions 322 is also even. Two second chips 221 form a group of second chip subgroups, and two second conductive leg portions 322 form a group of second conductive leg groups. A group of second conductive leg groups is arranged in a figure-eight shape on the second conductive main body portion 321.

[0069] Exemplarily, as Figure 6 shown, the number of the second chips 221 is eight, as Figure 8As shown, there are also eight second conductive legs 322 .

[0070] Optionally, the second conductive foot 322 is electrically connected to the second electrode of the corresponding second chip 221 through the second solder layer 520. Of course, the present application is not limited thereto, and the second electrode of the second chip 221 can also be electrically connected to the corresponding second conductive foot 322 through other welding processes such as silver sintering process or copper sintering process.

[0071] In this way, the second conductive member 320 can be conveniently used to arrange the plurality of second chips 221 in parallel between the electrical transfer portion 112 and the second conductive member 320 .

[0072] In this embodiment, the second conductive member 320 further includes a plurality of second transfer pins 323 connected to the second conductive body portion 321 close to the substrate 100 . The plurality of second transfer pins 323 are respectively electrically connected to the electrical output portion 113 , thereby facilitating electrical connection between the second conductive member 320 and the electrical output portion 113 .

[0073] In some embodiments, Figure 3 As shown, the electric input portion 111 and the electric switching portion 112 are arranged along a first direction F 1 It can be understood that the first chipset 210 and the second chipset 220 are also arranged along the first direction F 1 At least a portion of the electrical output portion 113 and the electrical input portion 111 is arranged along the second direction F 2 Interval setting, first direction F 1 With the second direction F 2 They are perpendicular to each other and perpendicular to the thickness direction of the substrate 100 .

[0074] It can be that the first direction F 1 The second direction F is parallel to the length direction of the substrate 100. 2 Parallel to the width direction of the substrate 100; or, the first direction F 1 The second direction F is parallel to the width direction of the substrate 100. 2 is parallel to the length direction of the substrate 100. In this embodiment, the first direction F 1 The second direction F is parallel to the width direction of the substrate 100. 2 Parallel to the length direction of the substrate 100 .

[0075] Since the electric input portion 111 and the electric switching portion 112 are arranged along the first direction F 1 The electric input portion 111 and the electric output portion 113 are arranged in a spaced relationship along the second direction F 2 Interval setting, first direction F 1 With the second direction F 2 They are perpendicular to each other, so that it is convenient for current to be input or output through the stacked circuit structure 10 .

[0076] In some embodiments, the electrical input portion 111 is provided with a 2 There are two first receiving grooves C1 arranged at intervals, and the first conductive layer 110 also includes two first insulating parts 114 corresponding to the two first receiving grooves C1 one by one. The first insulating parts 114 are arranged in the corresponding first receiving grooves C1. Each first insulating part 114 is provided with a second receiving groove C2. The electrical output part 113 includes two sub-output parts 1131 corresponding to the two second receiving grooves C2 one by one, and the sub-output parts 1131 are arranged in the corresponding second receiving grooves C2.

[0077] In this way, the sub-output part 1131 can be accommodated in the second receiving groove C2 on the corresponding first insulating part 114, and the first insulating part 114 can be accommodated in the first receiving groove C1 on the electrical input part 111, which is beneficial to reducing the overall occupied size of the electrical output part 113 and the electrical input part 111, and further beneficial to reducing the size of the first conductive layer 110, and also beneficial to reducing the volume of the stacked circuit structure 10.

[0078] In some embodiments, the first conductive layer 110 further includes a second insulating portion 115 between the power input portion 111 and the power transfer portion 112 , which can reduce the possibility of a short circuit between the power input portion 111 and the power transfer portion 112 .

[0079] In some embodiments, the electrical input portion 111 is arranged along the first direction F 1 The size of the electrical transfer portion 112 along the first direction F 1 The electrical input portion 111 is arranged along the second direction F 2 The size of the electrical transfer portion 112 along the second direction F 2 size.

[0080] In this way, the overall structure of the first conductive layer 110 can be roughly rectangular, which is also beneficial for roughly evenly distributing the first conductive layer 110 between the electrical input part 111 and the electrical switching part 112, thereby facilitating the arrangement of the same number of first chips 211 and second chips 221 on the substrate 100.

[0081] In some embodiments, the substrate 100 further includes a second conductive layer 120 disposed on a side of the first conductive layer 110 away from the first chipset 210 or the second chipset 220 , and a ceramic layer 130 disposed between the first conductive layer 110 and the second conductive layer 120 .

[0082] For example, the first conductive layer 110 and the second conductive layer 120 are both made of copper.

[0083] In some embodiments, Figure 5 As shown, the first conductive member 310 is provided with a plurality of first via holes 3111.Figure 9 As shown, a plurality of second vias 331 corresponding to the plurality of first vias 3111 are provided on the insulating layer 330, and the first vias 3111 communicate with the corresponding second vias 331.

[0084] The second conductive member 320 includes second conductive feet 322 corresponding to the second chips 221 one by one. The second conductive feet 322 pass through the corresponding second vias 331 and the corresponding first vias 3111 and are electrically connected to the corresponding second chips 221.

[0085] Specifically, the first vias 3111 are provided on the first conductive main body 311.

[0086] In this way, while using the insulating layer 330 to reduce the short - circuit situation in the loop where the first conductive member 310 and the second conductive member 320 are stacked, the second conductive feet 322 of the second conductive member 320 can pass through the second vias 331 and the corresponding first vias 3111 and be electrically connected to the corresponding second chips 221, realizing the serial connection of the first chip 211, the first conductive member 310, the second chip 221, and the second conductive member 320 in sequence, and also reducing the parasitic inductance of the stacked circuit structure 10.

[0087] In some embodiments, the thickness of the insulating layer 330 is D0, and D0≥0.1 mm.

[0088] The thickness of the insulating layer 330 is thick enough. In this way, the electrical isolation and stacked arrangement between the first conductive member 310 and the second conductive member 320 can be better realized, and further, the short - circuit situation in the loop where the first conductive member 310 and the second conductive member 320 are stacked can be better reduced.

[0089] In some embodiments, the thickness of the first conductive member 310 is D1, and D1≥0.1 mm.

[0090] Optionally, the first conductive member 310 is a rigid sheet metal part. Exemplarily, the material of the first conductive member 310 is copper.

[0091] The thickness of the first conductive member 310 is thick enough. In this way, the first conductive member 310 can provide a relatively reliable electrical connection for the first chip group 210 in the loop.

[0092] The thickness of the second conductive member 320 is D2, and D2≥0.3 mm.

[0093] Optionally, the second conductive member 320 is a rigid sheet metal part. Exemplarily, the material of the second conductive member 320 is copper.

[0094] The thickness of the second conductive member 320 is thick enough. In this way, the second conductive member 320 can provide a relatively reliable electrical connection for the second chip group 220 in the loop.

[0095] An embodiment of the present application provides a power module, including the stacked circuit structure 10 of any one of the above embodiments.

[0096] The stacked circuit structure 10 can be utilized to reduce the parasitic inductance of the power module.

[0097] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0098] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A laminated circuit structure, characterized in that: The stacked circuit structure comprises: substrate; A first chipset and a second chipset are disposed on one side of the substrate; the first chipset includes a first chip, and the second chipset includes a second chip; and A circuit structure, provided on a side of the first chipset or the second chipset away from the substrate, and comprising a first conductive member, an insulating layer, and a second conductive member stacked in a direction away from the substrate; The first chip, the first conductive element, the second chip and the second conductive element are sequentially connected in series.

2. The laminated circuit structure according to claim 1, characterized in that: The substrate comprises a first conductive layer, wherein the first conductive layer comprises an electric input portion, an electric switching portion and an electric output portion which are electrically isolated from each other; The first chipset is disposed on one side of the electrical input portion, and the second chipset is disposed on one side of the electrical switching portion; The first chip and the second chip each include a first electrode and a second electrode, the electrical input portion is electrically connected to the first electrode of the first chip, and the second electrode of the first chip is electrically connected to the electrical switching portion through the first conductive member; the electrical switching portion is electrically connected to the first electrode of the second chip, and the second electrode of the second chip is electrically connected to the electrical output portion through the second conductive member.

3. The laminated circuit structure according to claim 2, characterized in that: The first chipset includes a plurality of the first chips; The first conductive member includes a first conductive body and a plurality of first conductive legs connected to the first conductive body at one end, and the other ends of the first conductive legs are electrically connected to the first chip in a one-to-one correspondence.

4. The laminated circuit structure according to claim 2, characterized in that: The second chipset includes a plurality of the second chips; The second conductive member includes a second conductive body and a plurality of second conductive legs connected to the second conductive body at one end, and the other ends of the second conductive legs are electrically connected to the second chip in a one-to-one correspondence.

5. The laminated circuit structure according to claim 2, characterized in that: The electric input portion and the electric switching portion are arranged at intervals along a first direction; The electrical output portion and at least a portion of the electrical input portion are spaced apart along a second direction; The first direction and the second direction are perpendicular to each other, and are both perpendicular to the thickness direction of the substrate.

6. The laminated circuit structure according to claim 5, characterized in that: The electrical input portion is provided with two first receiving grooves spaced apart along the second direction, the first conductive layer further comprises two first insulating portions corresponding to the two first receiving grooves one by one, and the first insulating portions are arranged in the corresponding first receiving grooves; Each of the first insulating parts is provided with a second receiving groove, and the electrical output part includes two sub-output parts corresponding to the two second receiving grooves one by one, and the sub-output parts are arranged in the corresponding second receiving grooves.

7. The laminated circuit structure according to claim 6, characterized in that: The size of the electrical input portion along the first direction is equal to the size of the electrical switching portion along the first direction; The dimension of the electrical input portion along the second direction is equal to the dimension of the electrical switching portion along the second direction.

8. The laminated circuit structure according to any one of claims 1 to 7, characterized in that: The first conductive member is provided with a plurality of first via holes; The insulating layer is provided with a plurality of second via holes corresponding one-to-one to the plurality of first via holes; The first via hole is connected to the corresponding second via hole; The second conductive member includes second conductive legs corresponding to the second chips one by one. The second conductive legs pass through the corresponding second via holes and the corresponding first via holes and are electrically connected to the corresponding second chips.

9. The laminated circuit structure according to any one of claims 1 to 7, characterized in that: The thickness of the insulating layer is D0, D0 ≥ 0.1 mm; and / or The thickness of the first conductive member is D1, D1 ≥ 0.1 mm; and / or The thickness of the second conductive member is D2, where D2≥0.3 mm.

10. A power module, characterized in that: It comprises a laminated circuit structure as claimed in any one of claims 1 to 9.

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