Structure for testing metal silicide residues at polycrystalline silicon side wall

Abstract

The utility model provides a test structure for metal silicide residues at a polycrystalline silicon side wall. The test structure comprises an inner test region located in a substrate and an outer test region surrounding the inner test region, the first gate structure is positioned between the inner test region and the outer test region and comprises a first gate, and an outer side wall and an inner side wall which are positioned on the surface of the side wall of the first gate; the first metal silicide layer is positioned on the surface of the inner test region and the surface of the outer test region; the second metal silicide layer is positioned on the surface of the first grid electrode; the plurality of first electric interconnection structures are positioned on the surface of the first metal silicide layer of the outer test region and are respectively distributed along the first direction and the second direction; the second electric interconnection structure is positioned on the surface of the first metal silicide layer in the inner test region; and a plurality of third electric interconnection structures, wherein each third electric interconnection structure is located on the surface of the second metal silicide layer. According to the structure, the internal side wall and the external side wall can be independently tested and do not interfere with each other, and a detection blind area does not exist.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a test structure for metal silicide residue at the sidewall of polysilicon. Background Art

[0002] In the semiconductor manufacturing process, a metal silicide process is required to reduce the contact resistance between the active region and the gate. However, during the formation of metal silicide, due to process problems, metal silicide remains on the sidewall of the polysilicon gate, resulting in bridging between the polysilicon gate and the active region. Therefore, it is necessary to detect whether there is metal silicide residue on the sidewall of the polysilicon gate through a test structure.

[0003] However, the existing test structures have detection blind spots, so that the gate sidewalls located in the detection blind spots cannot be detected.

[0004] Therefore, providing a test structure without detection blind spots has become a technical problem urgently to be solved in the industry. Summary of the Utility Model

[0005] The technical problem solved by the utility model is to provide a test structure for metal silicide residue at the sidewall of polysilicon, which solves the problem of detection blind spots existing in the existing test structures.

[0006] To solve the above technical problem, an embodiment of the utility model provides a test structure for metal silicide residue at the sidewall of polysilicon. The test structure is arranged in the dicing channel of a wafer, and the test structure includes:

[0007] An inner test area and an outer test area surrounding the inner test area, located in the substrate;

[0008] A first gate structure, the first gate structure being connected end to end, located between the inner test area and the outer test area. The first gate structure includes a first gate and an outer sidewall and an inner sidewall located on the sidewall surface of the first gate;

[0009] A first metal silicide layer, which is respectively located on the surface of the inner test area and the surface of the outer test area;

[0010] A second metal silicide layer, which is located on the surface of the first gate;

[0011] A plurality of first electrical interconnection structures, which are located on the surface of the first metal silicide layer in the outer test area and are respectively distributed along a first direction and a second direction, and the first direction and the second direction are perpendicular to each other;

[0012] A second electrical interconnection structure, which is located on the surface of the first metal silicide layer in the inner test area;

[0013] A plurality of third electrical interconnection structures, each of the third electrical interconnection structures being located on the surface of the second metal silicide layer.

[0014] Optionally, each of the first electrical interconnection structures includes:

[0015] A plurality of first contact holes, each of the first contact holes being located on the surface of the first metal silicide layer in the outer test region;

[0016] A first liner layer, the first liner layer being located on the surface of the first contact holes;

[0017] The second electrical interconnection structure includes:

[0018] A plurality of second contact holes, each of the second contact holes being located on the surface of the first metal silicide layer in the inner test region;

[0019] A second liner layer, the second liner layer being located on the surface of the second contact holes.

[0020] Optionally, each of the third electrical interconnection structures includes:

[0021] A plurality of third contact holes, each of the third contact holes being located on the surface of the second metal silicide layer

[0022] A third liner layer, the third liner layer being located on the surface of the second contact holes.

[0023] Optionally, both the inner test region and the outer test region are active regions.

[0024] Optionally, a first gate dielectric layer, the first gate dielectric layer being located between the first gate and the substrate;

[0025] And an outer wall and an inner wall located on the sidewall surface of the first gate dielectric layer.

[0026] Optionally, the outer test region further includes a plurality of mutually discrete sub-test regions; the test structure further includes: a second gate structure, the second gate structure being located between adjacent sub-test regions, and at least one end of every two of the second gate structures being connected to the first gate structure, forming a corner in the outer test region;

[0027] Each of the second gate structures extends beyond the range of the outer test region;

[0028] Each of the second gate structures includes a second gate and an outer wall and an inner wall located on the sidewall surface of the second gate.

[0029] Optionally, among the several sub-test areas, there is a first sub-test area, and the first ends of two second gate structures located on both sides of the first sub-test area are connected to form a corner; among the several sub-test areas, there is a second sub-test area, and the first ends of two second gate structures located on both sides of the second sub-test area are not connected, and the connections between the two second gate structures located on both sides of the second sub-test area and the first gate structure respectively form corners.

[0030] Optionally, the second metal silicide layer is also disposed on the surface of the second gate.

[0031] Optionally, it further includes:

[0032] A second gate dielectric layer, which is located between the second gate and the substrate,

[0033] and an outer wall and an inner wall located on the side wall surface of the second gate dielectric layer.

[0034] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0035] In the test structure for metal silicide residue at the polysilicon sidewall provided by the present invention, on the one hand, the sidewalls on the sidewall surface of the first gate are divided into an inner sidewall and an outer sidewall by the inner test area and the outer test area, so that in subsequent tests, the inner sidewall and the outer sidewall can be tested separately without interference from each other. By using the first gate structure disposed between the inner test area and the outer test area, the sidewalls can be divided into parts in the first direction and in the second direction to detect the residue direction of the metal silicide residue. On the other hand, the first gate structure covers the entire test area, so all possible metal silicide residues on the sidewalls can be detected without detection blind spots.

[0036] Further, the outer test area includes 4 first test sub-areas and 4 second test sub-areas. There is a second gate structure between adjacent test sub-areas, and the second gate structure is in contact with the first gate structure. The first test sub-area and the second gate structure form only one corner; the second test sub-area and the second gate structure and the first gate structure form two corners, and the inner test area and the first gate structure naturally form multiple corners. Thus, in subsequent tests, the relationship between the number of sidewall corners and the metal silicide residue can be judged according to the magnitudes of the currents detected in the inner test area, the first test sub-area, and the second test sub-area respectively. Through this test structure, the comparative analysis of the metal silicide residues at the corners of different numbers of gate structures can be completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0038] Figure 1 is a top view of an embodiment of a metal silicide test structure;

[0039] Figure 2 is Figure 1 a cross-sectional view of the shown embodiment along the aa' direction;

[0040] Figure 3 is a top view of a test structure for metal silicide residue at the polysilicon sidewall provided by the technical solution of the present invention Figure 1 ;

[0041] Figure 4 is Figure 3 a cross-sectional view of the shown structure along the first direction;

[0042] Figure 5 is a top view of a test structure for metal silicide residue at the polysilicon sidewall provided by the technical solution of the present invention Figure 2 ;

[0043] Figure 6 is Figure 5 a cross-sectional view of the shown structure along the first direction. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0045] In the semiconductor manufacturing process, it is necessary to reduce the contact resistance of semiconductor devices through the metal silicide process. Currently, the main steps of the metal silicide process include: first depositing a layer of metal on the polysilicon gate and the active region; then performing two rapid thermal annealing processes and one selective wet etching treatment; finally forming metal silicide on the gate surface and the active region surface.

[0046] However, as the node shrinks, the production process faces increasingly severe challenges. Under inappropriate process conditions, there may be incomplete cleaning of the metal layer on the sidewall or the formation of metal silicide, resulting in bridging between the polysilicon gate and the active region. Therefore, it is particularly important to detect whether there is residual metal silicide on the sidewall during the production process through a test structure.

[0047] As described in the background art, the existing test structure has a detection blind spot for residual metal silicide, resulting in the inability to detect the gate sidewall located in the detection blind spot. The problems existing in the prior art will be described below with reference to the accompanying drawings.

[0048] Figure 1 is a top view of an embodiment of a metal silicide test structure. Figure 2 is Figure 1 a cross-sectional view of the shown embodiment along the aa' direction.

[0049] Please refer to Figure 1 and Figure 2 , the test structure of the prior art mainly includes a substrate 1, an active region 2 formed on the surface of the substrate 1, a gate 4 formed on the surface of the active region 2, a sidewall 5 covering the sidewalls of the gate 4, and metal silicide 3 covering both the surface of the gate 4 and the surface of the active region 2. As can be seen from Figure 2 , the gate 4 divides the active region 2 into left and right regions. The first pad PAD1 is disposed on the surface of the active region 2 on the left side of the gate 4, the second pad PAD2 is disposed on the surface of the active region 2 on the right side of the gate 4, and the third pad PAD3 is disposed on the surface of the gate 4. During the test, a test voltage is applied to the third pad PAD3 and the first pad PAD1; if the measured current value is greater than 0, it indicates that there is residual metal silicide 3 on the left sidewall 5 of the gate 4; if the measured current value is equal to 0, it indicates that there is no residual metal silicide 3 on the left sidewall 5 of the gate 4. Similarly, a test voltage is applied to the third pad PAD3 and the second pad PAD2; if the measured current value is greater than 0, it indicates that there is residual metal silicide 3 on the right sidewall 5 of the gate 4; if the measured current value is equal to 0, it indicates that there is no residual metal silicide 3 on the right sidewall 5 of the gate 4. However, the problem with this solution is that this solution can only test whether there is residual metal silicide 3 on the sidewall 5 of the overlapping part between the gate 4 and the active region 2, and the sidewalls 5 on both sides beyond the active region 2 and the corners of the sidewall 5 cannot be detected; furthermore, the relationship between the corner of the sidewall 5 and the residual metal silicide 3 cannot be detected.

[0050] In view of this, the technical solution of the present utility model provides a new test structure for the residue of metal silicide at the polysilicon sidewall.

[0051] Among them, Figure 3 is a top view of the test structure for the residue of metal silicide at the polysilicon sidewall provided by the technical solution of the present utility model. Figure 4 is Figure 3 a cross-sectional view of the structure shown in the first direction.

[0052] Please refer to Figure 3 and Figure 4 , the test structure for the residue of metal silicide at the polysilicon sidewall provided by the technical solution of the present utility model, the test structure is arranged in the dicing channel of the wafer, and the test structure includes:

[0053] An inner test area 3 and an outer test area 2 surrounding the inner test area 3, located in the substrate 1;

[0054] A first gate structure 7, the first gate structure 7 is connected end to end, located between the inner test area 3 and the outer test area 2, and the first gate structure 7 includes a first gate 4 and an outer sidewall 5 and an inner sidewall 8 located on the sidewall surface of the first gate;

[0055] A first metal silicide layer 10, the first metal silicide layer 10 is respectively located on the surface of the inner test area 3 and the surface of the outer test area 2;

[0056] A second metal silicide layer 6, the second metal silicide layer 6 is located on the surface of the first gate 4;

[0057] A plurality of first electrical interconnection structures 210, the first electrical interconnection structures 210 are located on the surface of the first metal silicide layer 10 in the outer test area 2 and are respectively distributed along a first direction AA' and a second direction BB', and the first direction AA' and the second direction BB' are perpendicular to each other;

[0058] A second electrical interconnection structure 310, the second electrical interconnection structure 310 is located on the surface of the first metal silicide layer 10 in the inner test area 3;

[0059] A plurality of third electrical interconnection structures 110, each of the third electrical interconnection structures 110 is located on the surface of the second metal silicide layer 6.

[0060] By the above technical means, on the basis of realizing the detection of the residue of metal silicide on the sidewall without blind spots, the technical solution of the present utility model can also detect the residual direction of metal silicide on the outer sidewall 5. The specific principle is as follows:

[0061] The first gate structure 7 is disposed between the inner test region 3 and the outer test region 2 surrounding the inner test region 3. The second metal silicide layer 6 is disposed on the surface of the first gate structure 7. The first metal silicide layer 10 is disposed on the surfaces of the inner test region 3 and the outer test region 2. A plurality of first electrical interconnection structures 210 are respectively distributed on the surface of the first metal silicide layer 10 of the outer test region 2 along a first direction AA' and a second direction BB'. A second electrical interconnection structure 310 is disposed on the surface of the first metal silicide layer 10 of the inner test region 3. A plurality of third electrical interconnection structures 110 are disposed on the surface of the second metal silicide layer 6. By applying a detection voltage to the third electrical interconnection structure 110 and detecting whether there is a current in the first electrical interconnection structure 210, it is possible to detect whether there is metal silicide remaining on the outer sidewall 5 of the first gate 4; by applying a detection voltage to the third electrical interconnection structure 110 and detecting whether there is a current in the second electrical interconnection structure 310, it is possible to detect whether there is metal silicide remaining on the inner sidewall 8 of the first gate 4. From Figure 3 As can be seen from the structure shown, the first gate structure 7 is a rectangular ring structure. The first direction AA' passes through the parallel first side and third side of the rectangular ring structure, and the second direction BB' passes through the parallel second side and fourth side of the rectangular ring structure. And this rectangular ring structure is equivalent to dividing the entire test region into the outer test region 2 and the inner test region 3, thus completely covering the surface of the test region. Therefore, there is no detection blind area for both the outer sidewall 5 and the inner sidewall 8 of the first gate 4. At the same time, the outer sidewall 5 and the inner sidewall 8 of the first gate 4 are separated by the first gate structure 7. Therefore, the detection of metal silicide residue on the outer sidewall 5 and the detection of metal silicide residue on the inner sidewall 8 do not interfere with each other.

[0062] Since the first electrical interconnection structures 210 are distributed along the first direction AA' and the second direction BB', and the first direction AA' and the second direction BB' are perpendicular to each other. After applying a voltage to the third electrical interconnection structure 110, if there is metal silicide residue on the outer sidewall 5, then the first electrical interconnection structures 210 disposed in the first direction AA' and the first electrical interconnection structures 210 disposed in the second direction BB' can both detect a current. At this time, the first current detected from the first electrical interconnection structure 210 in the first direction AA' and the second current detected from the first electrical interconnection structure 210 in the second direction BB' can be compared. If the first current is greater than the second current, it can be determined that there is metal silicide remaining on the outer sidewall 5 along the first direction AA'; if the first current is less than the second current, it can be determined that there is metal silicide remaining on the outer sidewall 5 along the second direction BB'.

[0063] To make the above objects, features, and beneficial effects of the present utility model more obvious and understandable, the following provides a detailed description of specific embodiments of the present utility model with reference to the accompanying drawings.

[0064] Please refer to Figure 4 , as a specific embodiment, both the inner test region 3 and the outer test region 2 are active regions 12 and are disposed on the substrate 1. Shallow trench isolation structures 11 are disposed on both sides of the entire active region 12 to isolate the active region 12 from other devices. Among them, the shallow trench isolation structure 11 is specifically formed by an isolation structure of oxide, nitride, or a combination of oxide and nitride. The material of the substrate 1 may include silicon, germanium, or silicon on insulator (SOI, etc.), and the specific material of the substrate 1 can be selected according to requirements and is not limited herein.

[0065] Please refer to 4. As a specific embodiment, each of the first electrical interconnection structures 210 includes:

[0066] A plurality of first contact holes 2102, each of the first contact holes 2102 being located on the surface of the first metal silicide layer 10 of the outer test region 2;

[0067] A first liner layer 2101, the first liner layer 2101 being located on the surface of the first contact hole 2102;

[0068] The second electrical interconnection structure 310 includes:

[0069] A plurality of second contact holes 3102, each of the second contact holes 3102 being located on the surface of the first metal silicide layer 10 of the inner test region 3;

[0070] A second liner layer 3101, the second liner layer 3101 being located on the surface of the second contact hole 3102.

[0071] Each of the third electrical interconnection structures 110 includes:

[0072] A plurality of third contact holes 1101, each of the third contact holes 1101 being located on the surface of the second metal silicide layer 6;

[0073] A third liner layer 1102, the third liner layer 1102 being located on the surface of the second contact hole 3102.

[0074] The first electrical interconnection structure 210 can be correspondingly arranged with the third electrical interconnection structure 110. It can be understood that one first electrical interconnection structure 210 is arranged on the surface of the first metal silicide in the first direction AA`, and a corresponding third electrical interconnection structure 110 is arranged on the surface of the third metal silicide in the first direction AA`. The same applies to the second direction BB`, which will not be elaborated here. Therefore, the number of the first electrical interconnection structures 210 can be the same as the number of the third electrical interconnection structures 110. Of course, the arrangement of the third electrical interconnection structures 110 may not correspond to that of the first electrical interconnection structures 210. For example, 3 third electrical interconnection structures 110 can be arranged and 5 first electrical interconnection structures 210 can be arranged. At the same time, the number of the first electrical interconnection structures 210 arranged along the first direction AA` can be the same as the number of the first electrical interconnection structures 210 arranged along the second direction BB`, or of course different, which can be specifically set according to requirements and is not limited here.

[0075] It should be noted that the setting specification of the first contact hole 2102 in the first electrical interconnection structure 210 can be set to 2*2, or can be set to 2*3 or 3*2, etc., which can be specifically set according to requirements and is not limited here. The settings of the second contact hole 3102 and the third contact hole 1101 are similar to the setting of the first contact hole 2102, which will not be elaborated here.

[0076] As a specific implementation manner, the outer sidewall 5 and the inner sidewall 8 of the first gate 4 are both obtained by depositing one or more layers of oxides or nitrides or a combination of the two. Preferably, the outer sidewall 5 and the outer sidewall 8 can be an ONO (silicon oxide - silicon nitride - silicon oxide) structure.

[0077] Please refer to Figure 4 , as a specific implementation manner, the test structure further includes:

[0078] A first gate dielectric layer 9, which is located between the first gate 4 and the substrate 1;

[0079] And a sidewall structure located on the sidewall surface of the first gate dielectric layer 9.

[0080] The following takes Figure 3 the structure shown as an example to illustrate the test process of the test structure for metal silicide residue at the polysilicon sidewall provided by the embodiment of the present invention:

[0081] Please refer to Figure 4, four of the first electrical interconnection structures 210 are provided, and four of the third electrical interconnection structures 110 are provided. The first direction AA' passes through the first side and the third side of the first gate structure 7. The second direction BB' passes through the second side and the fourth side of the first gate structure 7. The four first electrical interconnection structures 210 are respectively provided on the four sides of the first gate structure 7, and the four third electrical interconnection structures 110 respectively correspond to the four first electrical interconnection structures 210 one by one.

[0082] A test voltage is applied to each of the third electrical interconnection structures 110, and the current on each of the first electrical interconnection structures 210 is detected;

[0083] If the current measured on each of the first electrical interconnection structures 210 is zero, there is no metal silicide residue on the outer sidewall 5 of the first gate 4. If a current is measured on each of the first electrical interconnection structures 210 and the current measured at the first side is the largest, there is metal silicide residue on the outer sidewall 5 of the first gate 4 and it is located on the first side of the outer sidewall 5. If a current is measured on each of the first electrical interconnection structures 210 and the current measured at the second side is the largest, there is metal silicide residue on the outer sidewall 5 of the first gate 4 and it is located on the second side of the outer sidewall 5. If a current is measured on each of the first electrical interconnection structures 210 and the current measured at the third side is the largest, there is metal silicide residue on the outer sidewall 5 of the first gate 4 and it is located on the third side of the outer sidewall 5. If a current is measured on each of the first electrical interconnection structures 210 and the current measured at the fourth side is the largest, there is metal silicide residue on the outer sidewall 5 of the first gate 4 and it is located on the fourth side of the outer sidewall 5.

[0084] A test voltage is applied to one of the third electrical interconnection structures 110, and the current on the second electrical interconnection structure 310 is detected;

[0085] If no current is measured on the second electrical interconnection structure 310, there is no metal silicide residue on the inner sidewall 8 of the first gate 4. If a current is measured on the second electrical interconnection structure 310, there is metal silicide residue on the inner sidewall 8 of the first gate 4.

[0086] It should be noted that due to the presence of the first metal silicide layer 10, only when there is metal silicide residue on the outer sidewall 5, the first electrical interconnection structures 210 provided in the external test area 2 can all detect current, but the distance between the residual metal silicide and the first electrical interconnection structures 210 will affect the magnitude of the detected current. Specifically: the farther the distance, the smaller the current; the closer the distance, the larger the current.

[0087] As described above, in actual production, metal silicide may remain on the sidewall due to improper treatment of the wet etching step or changes in the sidewall topography. The most likely place for metal silicide to remain on the sidewall is the sidewall at the gate corner. Since it is difficult to control the formation of the sidewall at the gate corner, it is also difficult for the cleaning solution to clean the sidewall at the gate corner, which makes it easier for metal silicide to remain on the sidewall at the gate corner, resulting in bridging between the active region 12 and the gate of the device and the device unable to work properly.

[0088] Figure 5 The top view of the test structure for the residual metal silicide at the polysilicon sidewall provided by the technical solution of the present invention Figure 2 。 Figure 6 is Figure 5 the cross-sectional view of the structure shown along the AA' direction.

[0089] Please refer to Figure 5 and Figure 6 As a specific embodiment, the outer test area 2 further includes a plurality of discrete sub-test areas; the test structure further includes: a second gate structure 13, the second gate structure 13 is located between adjacent sub-test areas, and at least one end of every two of the second gate structures 13 is connected to the first gate structure 7 to form a corner in the outer test area 2;

[0090] Each of the second gate structures 13 extends beyond the range of the outer test area 2;

[0091] Each of the second gate structures 13 includes a second gate and a sidewall structure located on the sidewall surface of the second gate.

[0092] Among the plurality of sub-test areas, there is a first sub-test area 201, and the first ends of the two second gate structures 13 located on both sides of the first sub-test area 201 are connected to form a corner; among the plurality of sub-test areas, there is a second sub-test area 202, and the first ends of the two second gate structures 13 located on both sides of the second sub-test area 202 are not connected, and the connections of the two second gate structures 13 located on both sides of the second sub-test area 202 to the first gate structure 7 respectively form corners.

[0093] Each of the first sub-test areas 201 and each of the second sub-test areas 202 are provided with the first electrical interconnection structure 210.

[0094] From Figure 5As can be seen from the structure shown, combining the first gate structure 7 and the second gate structure 13 forms a cross shape. Since the cross shape has one corner, two corners, and four corners respectively, the gate structure in the shape of a cross naturally divides the test area into a first sub-test area 201 with one corner, a second sub-test area 202 with two corners, and an inner test area 3 with four corners. The first electrical interconnection structure 210 is provided in each sub-test area, and a test voltage is applied to the three electrical interconnection structures. Since the gate structure in the shape of a cross physically isolates each of the first sub-test area 201, each of the second sub-test area 202, and the inner test area 3, and each of the second gate structures 13 extends beyond the outer test area 2, there is no interference between each test area when detecting whether there is residual metal silicide on the outer sidewall 5. At the same time, by detecting the current at the first electrical interconnection structure 210, the relationship between the number of corners of the outer sidewall 5 and the amount of residual metal silicide can be detected.

[0095] It should be noted that through Figure 5 As can be seen from the structure shown, there are four first sub-test areas 201 and four second sub-test areas 202. Setting the first electrical interconnection structure 210 in each of the first sub-test areas 201 and each of the second sub-test areas 202 can improve the accuracy of detecting the relationship between the number of corners of the outer sidewall 5 and the amount of residual metal silicide. Of course, the first electrical interconnection structure 210 can also be set only in one or two or three of the first sub-test areas 201, which is not limited here. The strategy of setting the first electrical interconnection structure 210 in the second sub-test area 202 is the same as that in the first sub-test area 201, and will not be elaborated here.

[0096] As a specific implementation manner, the second metal silicide layer 6 is also provided on the surface of the second gate. The test structure further includes:

[0097] A second gate dielectric layer, which is located between the second gate and the substrate 1,

[0098] and a sidewall structure located on the sidewall surface of the second gate dielectric layer.

[0099] The following takes Figure 5 the structure shown as an example to illustrate the test process of the test structure for detecting residual metal silicide at the polysilicon sidewall provided by the embodiment of the present invention:

[0100] Please refer to Figure 5 , and the first electrical interconnection structure 210 is provided in each of the first sub-test areas 201 and each of the second sub-test areas 202.

[0101] A test voltage is applied to each of the third electrical interconnection structures 110, and the current on each of the first electrical interconnection structures 210 and the current on the second electrical interconnection structures 310 are detected;

[0102] The currents measured on the first electrical interconnection structures 210 within each of the first sub-test regions 201 are added together and divided by 4 to obtain a third current. The currents measured on the first electrical interconnection structures 210 within each of the second sub-test regions 202 are added together and divided by 4 to obtain a fourth current. A fifth current is measured through the second electrical interconnection structures 310. If the third current, the fourth current, and the fifth current are all equal to zero, it indicates that there is no metal silicide residue on either the outer wall 5 or the inner wall 8 at the corner of the gate structure. If the fifth current is greater than the fourth current which is greater than the third current, it indicates that the more corners the gate structure has, the more metal silicide remains on the side walls, and the greater the risk of bridging between the gate structure and the active region 12. If the third current, the fourth current, and the fifth current are equal and greater than zero, it indicates that there is metal silicide residue on the side walls at the corner of the gate structure, but there is no direct relationship between the amount of metal silicide residue and the number of corners.

[0103] In summary, for the test structure of metal silicide residue at the polysilicon side wall provided by the embodiments of the present invention, the side walls on the side wall surface of the first gate are divided into an inner side wall and an outer side wall through the inner test region and the outer test region, so that during subsequent tests, the inner side wall and the outer side wall can be tested separately without interference from each other. By using the first gate structure disposed between the inner test region and the outer test region, the side walls can be divided into those in the first direction and those in the second direction to detect the residual direction of the metal silicide residue. In addition, since the first gate structure covers the entire test region, any possible metal silicide residue on the side walls can be detected, and there is no detection blind spot.

[0104] Furthermore, the outer test region further includes a plurality of mutually discrete sub-test regions. The second gate structures are disposed between adjacent sub-test regions, and at least one end of every two of the second gate structures is connected to the first gate structure to form a grid-shaped gate structure, thereby testing the relationship between the number of corners of the gate structure and the metal silicide residue on the side walls.

[0105] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A test structure for metal silicide residues at a polysilicon sidewall, the test structure being arranged in a cutting path of a wafer, characterized in that: The test structure includes: An inner test area and an outer test area surrounding the inner test area are located in the substrate; A first gate structure, the first gate structure is connected end to end and is located between the inner test area and the outer test area, the first gate structure includes a first gate and an outer sidewall and an inner sidewall located on a sidewall surface of the first gate; a first metal silicide layer, wherein the first metal silicide layer is respectively located on the surface of the inner test area and the surface of the outer test area; a second metal silicide layer, wherein the second metal silicide layer is located on a surface of the first gate; A plurality of first electrical interconnect structures, wherein the first electrical interconnect structures are located on the surface of the first metal silicide layer of the outer test region and are respectively distributed along a first direction and along a second direction, wherein the first direction and the second direction are perpendicular to each other; a second electrical interconnect structure, the second electrical interconnect structure being located on a surface of the first metal silicide layer in the inner test region; A plurality of third electrical interconnect structures, each of the third electrical interconnect structures is located on the surface of the second metal silicide layer.

2. The test structure of metal silicide residue at the polysilicon sidewall according to claim 1, characterized in that: Each of the first electrical interconnect structures comprises: A plurality of first contact holes, each of which is located on the surface of the first metal silicide layer in the outer test area; A first liner layer, wherein the first liner layer is located on a surface of the first contact hole; The second electrical interconnect structure comprises: A plurality of second contact holes, each of which is located on the surface of the first metal silicide layer in the inner test area; A second liner layer is located on a surface of the second contact hole.

3. The test structure of metal silicide residue at the polysilicon sidewall according to claim 1, characterized in that: Each of the third electrical interconnect structures comprises: A plurality of third contact holes, each of which is located on the surface of the second metal silicide layer A third liner layer is located on a surface of the third contact hole.

4. The test structure of metal silicide residue at polysilicon sidewalls according to claim 1, characterized in that: The inner test area and the outer test area are both active areas.

5. The test structure of metal silicide residue at polysilicon sidewalls according to claim 1, characterized in that: Also includes: a first gate dielectric layer, wherein the first gate dielectric layer is located between the first gate and the substrate; and an outer sidewall and an inner sidewall located on the sidewall surface of the first gate dielectric layer.

6. The test structure of metal silicide residue at polysilicon sidewalls according to claim 1, characterized in that: The outer test area also includes a plurality of mutually separated sub-test areas; the test structure also includes: a second gate structure, the second gate structure is located between adjacent sub-test areas, and at least one end of every two second gate structures is connected to the first gate structure to form a corner in the outer test area; Each of the second gate structures exceeds the range of the outer test region; Each of the second gate structures includes a second gate and an outer sidewall and an inner sidewall located on a sidewall surface of the second gate.

7. The test structure of metal silicide residue at polysilicon sidewalls according to claim 6, characterized in that: The several sub-test areas include a first sub-test area, and the first ends of two second gate structures located on both sides of the first sub-test area are connected and form a corner; the several sub-test areas include a second sub-test area, and the first ends of two second gate structures located on both sides of the second sub-test area are not connected, and the connections between the two second gate structures located on both sides of the second sub-test area and the first gate structure respectively form corners.

8. The test structure for metal silicide residues at polysilicon sidewalls according to claim 6, characterized in that: The second metal silicide layer is also disposed on the surface of the second gate.

9. The test structure for metal silicide residues at polysilicon sidewalls according to claim 6, characterized in that: Also includes: a second gate dielectric layer, the second gate dielectric layer being located between the second gate and the substrate, and an outer sidewall and an inner sidewall located on the sidewall surface of the second gate dielectric layer.

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