Light sensing chip and electronic equipment
By designing a stacked light blocking structure on the photosensitive chip, including alternately arranged light blocking conductive layers and insulating layers, and grounding all light blocking conductive layers, the interference problem of external light on the photosensitive chip is solved, and the effect of reducing noise and improving chip performance is achieved.
Patent Information
- Application Number
- CN202421976825.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-14
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-08-14
AI Technical Summary
When existing photosensitive chips are exposed to external light, abnormal phenomena such as increased leakage current and increased noise are prone to affecting the normal operation of the chip.
A photosensitive chip is designed, adopting a stacked light blocking structure, including a light blocking conductive layer and an insulating layer. The light blocking conductive layer and the insulating layer are arranged alternately above and below, and all light blocking conductive layers are grounded to form an effective shielding layer to directly shield the light interference from the outside world.
The light blocking structure effectively shields external light, reduces the impact of light effect on circuit performance, reduces noise, improves chip performance, and prevents the impact of digital interference on other devices.
Smart Images
Figure CN222966143U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of optoelectronic communication. More specifically, the utility model relates to a photosensitive chip and an electronic device. Background Art
[0002] In general optical applications, when an AFE (analog front end) chip is irradiated by external light, abnormal phenomena such as increased leakage current and increased noise may occur. The external light interferes with the internal components of the AFE chip, affecting the normal operation of the chip. Summary of the Utility Model
[0003] Aiming at the deficiencies of the prior art, the utility model innovatively provides a photosensitive chip and an electronic device, which realize light shielding, avoid external light from irradiating the sensitive area inside the AFE chip, and reduce the influence of the photoelectric effect on the circuit performance; all light-blocking conductive layers are grounded to form an effective and complete shielding layer, directly shielding external interference and preventing the influence of digital interference inside the AFE chip on other components; at the same time, grounding all light-blocking conductive layers eliminates floating metals, effectively avoiding the interference of floating metal coupling on the highly sensitive photosensitive circuit and the performance degradation caused by the parasitic parameters of the floating structure, reducing noise and improving the chip performance.
[0004] To achieve the above technical purpose, the first aspect of the utility model discloses a photosensitive chip, which includes an analog front-end chip and a layered light-blocking structure.
[0005] The light-blocking structure is arranged above the analog front-end chip. The light-blocking structure includes at least one light-blocking conductive layer and at least one insulating layer. The light-blocking conductive layer and the insulating layer are arranged alternately up and down. The bottom layer of the light-blocking structure is an insulating layer, and all the light-blocking conductive layers are grounded.
[0006] Further, the light-blocking conductive layer is a metal layer.
[0007] Further, when the number of the light-blocking conductive layers is two or more, the light-blocking conductive layer is provided with a hollow hole, and all the light-blocking conductive layers are stacked to be light-impermeable.
[0008] Further, the light-blocking conductive layer is a metal layer, and the total volume of the hollow holes on each light-blocking conductive layer is not less than 45% of the volume of the light-blocking conductive layer.
[0009] Further, the light-blocking conductive layer is a redistribution layer.
[0010] Further, a signal trace is arranged in one of the light-blocking conductive layers of the light-blocking structure.
[0011] Further, when the number of layers of the light-shielding conductive layer is three or more, the signal trace is disposed in one of the light-shielding conductive layers that is neither the topmost layer nor the bottommost layer among all the light-shielding conductive layers.
[0012] Further, some or all of the light-shielding conductive layers are connected to the ground pin of the analog front-end chip.
[0013] Further, the light-shielding conductive layer and the insulating layer are adhesively fixed.
[0014] To achieve the above technical objectives, a second aspect of the present invention discloses an electronic device, including the photosensing chip described in the first aspect.
[0015] The beneficial effects of the present invention are as follows:
[0016] The photosensing chip of the present invention realizes light shielding, avoids external light from irradiating the sensitive area inside the AFE chip, and reduces the influence of the photoelectric effect on the circuit performance; all the light-shielding conductive layers are grounded to form an effective and complete shielding layer, directly shielding external interference and also preventing the digital interference inside the AFE chip from affecting other devices; at the same time, grounding all the light-shielding conductive layers eliminates the floating metal, effectively avoiding the interference of the floating metal coupling on the highly sensitive photosensing circuit and the performance degradation caused by the parasitic parameters of the floating structure, reducing noise, and improving the chip performance. Description of the Drawings
[0017] Figure 1 is a schematic structural diagram of a photosensing chip in the prior art.
[0018] Figure 2 is a side view of the photosensing chip according to the first embodiment of the present invention.
[0019] Figure 3 is a side view of the photosensing chip according to the second embodiment of the present invention.
[0020] Figure 4 is a side view of the photosensing chip according to the third embodiment of the present invention.
[0021] Figure 5 is a side view of the photosensing chip according to the fourth embodiment of the present invention.
[0022] Figure 6 is a top view of the photosensing chip according to the fourth embodiment of the present invention.
[0023] Figure 7 is a side view of the photosensing chip according to the fifth embodiment of the present invention.
[0024] In the figure,
[0025] 1. Analog front-end chip; 2. Double-low film; 21. Black film; 22. Metal layer; 3. Light-blocking structure; 31. Light-blocking conductive layer; 310. Hollow hole; 3101. First hollow hole; 3102. Second hollow hole; 3103. Third hollow hole; 311. First light-blocking conductive layer; 312. Second light-blocking conductive layer; 313. Third light-blocking conductive layer; 32. Insulating layer; 321. First insulating layer; 322. Second insulating layer; 323. Third insulating layer; 324. Fourth insulating layer; 4. Signal trace. Detailed implementation mode
[0026] The light sensor chip and electronic device provided by the present utility model will be explained and described in detail below in conjunction with the accompanying drawings of the specification.
[0027] In the prior art, a double-low film 2 is usually disposed above the analog front-end chip 1 to block external light. As Figure 1 shown, the double-low film 2 is formed by stacking two layers of black films 21 and a metal layer 22 between the two layers of black films 21. The black film 21 includes alternately stacked upper and lower silicon dioxide thin layers and titanium dioxide thin layers. The metal layer 22 includes alternately stacked upper and lower metal thin layers, silicon dioxide thin layers and titanium dioxide thin layers. Due to process limitations, the metal thin layer in the metal layer 22 cannot be grounded and is in a floating state. However, in actual light sensor applications, the floating metal will be coupled to relatively large external interferences, such as screen interference and digital interference, etc., and the noise is relatively large, which has a greater impact on the performance of the AFE chip.
[0028] This embodiment specifically discloses a light sensor chip. As Figures 2 - 7 shown, it includes an analog front-end chip 1 and a laminated light-blocking structure 3. The light-blocking structure 3 is disposed above the analog front-end chip 1. The light-blocking structure 3 includes at least one light-blocking conductive layer 31 and at least one insulating layer 32. The light-blocking conductive layer 31 and the insulating layer 32 are alternately arranged up and down. The bottom layer of the light-blocking structure 3 is the insulating layer 32, and the insulating layer 32 at the bottom layer of the light-blocking structure 3 is fixed on the upper surface of the analog front-end chip 1. The top layer of the light-blocking structure 3 can be the insulating layer 32 or the light-blocking conductive layer 31, which is specifically set according to actual application needs, that is, the number of layers of the insulating layer 32 can be the same as the number of layers of the light-blocking conductive layer 31 or one more layer than the number of layers of the light-blocking conductive layer 31. As Figure 2 shown, the number of layers of the insulating layer 32 and the light-blocking conductive layer 31 in the light-blocking structure 3 is the same, and the top layer of the light-blocking structure 3 is the light-blocking conductive layer 31. As Figure 3As shown, in the light-shielding structure 3, the number of layers of the insulating layer 32 is one more than that of the light-shielding conductive layer 31, and the topmost layer of the light-shielding structure 3 is the insulating layer 32. The total number of layers of the light-shielding structure 3 is set according to actual needs. The light-shielding conductive layer 31 can shield most of the light, and the insulating layer 32 can also absorb the remaining light. By alternately stacking the light-shielding conductive layer 31 and the insulating layer 32, the shielding of light with different wavelengths is achieved, preventing external light from penetrating into the analog front-end chip 1.
[0029] Optionally, the light-shielding conductive layer 31 is a metal layer, such as a metal layer made of copper, aluminum, etc., which has a low transmittance, good shielding effect and is easy to process.
[0030] The material of the insulating layer 32 can be set according to the wavelength of the light to be absorbed. Preferably, the insulating layer 32 is benzocyclobutene (BCB), polyimide (PI) or polybenzoxazole (PBO), and more preferably polyimide (PI).
[0031] Optionally, the light-shielding conductive layer 31 and the insulating layer 32 are bonded and fixed. The adhesive can be selected as glue, and the light-shielding conductive layer 31 and the insulating layer 32 can be stacked by bonding with glue. The bottommost insulating layer 32 is also bonded and fixed to the analog front-end chip 1. By controlling the thickness and uniformity of the light-shielding conductive layer 31 and the insulating layer 32, good adhesion at the layer interface can be ensured, avoiding delamination or fracture caused by thermal expansion and contraction. The insulating layer 32 plays a buffering role, reducing the mechanical stress caused by the mismatch of thermal expansion coefficients, thereby improving the overall reliability of the photosensing chip.
[0032] As Figure 5 and 7 shown, setting the insulating layer 32 between adjacent light-shielding conductive layers 31 not only plays a buffering role, but also can prevent electrical short circuits between adjacent light-shielding conductive layers 31. Moreover, through the setting of the insulating layer 32, multi-layer structure interconnection can be realized, making the light-shielding structure 3 in a stacked shape, effectively utilizing the vertical space, and improving the integration degree and function density.
[0033] As Figures 2 - 7 shown, all the light-shielding conductive layers 31 are grounded to form an effective and complete shielding layer, directly shielding external interference. For example, when the photosensing chip is applied under the screen, the analog front-end chip 1 will be affected by the display drive interference of the screen, resulting in large fluctuations in the signal and affecting the final performance. However, the present application effectively shields the display drive interference of the screen; all the light-shielding conductive layers 31 being grounded can also prevent the influence of digital interference inside the analog front-end chip 1 on other devices; at the same time, grounding all the light-shielding conductive layers 31 eliminates the floating metal, reduces the floating effect, effectively avoids the influence of the interference coupled by the floating metal on the highly sensitive photosensing circuit and the performance degradation caused by the parasitic parameters of the floating structure, reduces noise, and improves the chip performance.
[0034] Optionally, part or all of the light-blocking conductive layer 31 is connected to the ground pin of the analog front-end chip 1. That is, part of the light-blocking conductive layer 31 can be grounded to the ground wire GND, part of the light-blocking conductive layer 31 is connected to the ground pin of the analog front-end chip 1, and the ground pin of the analog front-end chip 1 is grounded to the ground wire GND; alternatively, all of the light-blocking conductive layers 31 can be connected to the ground pin of the analog front-end chip 1, and the ground pin of the analog front-end chip 1 is grounded to the ground wire GND. Connecting the light-blocking conductive layer 31 to the ground pin of the analog front-end chip 1 and then connecting the ground pin to the ground wire GND simplifies the wiring in the circuit. Preferably, all of the light-blocking conductive layers 31 are connected to the ground pin of the analog front-end chip 1 (as shown in Figure 3 , 4 and 7).
[0035] Optionally, as shown in Figures 5 - 7 , when the number of layers of the light-blocking conductive layer 31 is two or more, the light-blocking conductive layer 31 is provided with hollow holes 310, and all the light-blocking conductive layers 31 are stacked to be light-impermeable. When the light-blocking conductive layer 31 is made of a material with a relatively large stress, if the volume ratio of this material in this layer is relatively large, it will cause delamination of the light-blocking conductive layer 31. Therefore, it is necessary to set the hollow holes 310 to reduce the volume occupied by the material and improve the reliability. The size and number of the hollow holes 310 are determined according to the material of the light-blocking conductive layer 31, and no specific limitation is made in this application. The number, size, and setting area of the hollow holes 310 on each layer of the light-blocking conductive layer 31 can be the same or different.
[0036] The hollow holes 310 on each layer are arranged as follows, that is, when all the light-blocking conductive layers 31 are stacked, there is no situation where the vertical projections of the hollow holes 310 from the top layer to the bottom layer all overlap, so that all the light-blocking conductive layers 31 are stacked to be light-impermeable.
[0037] When the number of layers of the light-blocking conductive layer 31 is two, the two layers of hollow holes 310 are staggered, and the hollow holes 310 are closed by the rest outside the hollow holes 310 to avoid light leakage. As shown in Figure 5 and 6 , the light-blocking structure 3 includes two layers of light-blocking conductive layers 31 and two layers of insulating layers 32. From bottom to top, they are the first insulating layer 321, the first light-blocking conductive layer 311, the second insulating layer 322, and the second light-blocking conductive layer 312. The first light-blocking conductive layer 311 is provided with a plurality of first hollow holes 3101, the second light-blocking conductive layer 312 is provided with a plurality of second hollow holes 3102, and the first hollow holes 3101 and the second hollow holes 3102 are staggered in the vertical direction, so that the first light-blocking conductive layer 311 and the second light-blocking conductive layer 312 are stacked to be light-impermeable.
[0038] When the number of layers of the light-blocking conductive layer 31 is two or more, the hollow holes 310 of some layers may completely overlap or partially overlap, and the hollow holes 310 of some layers are staggered. As long as it is ensured that the light-blocking conductive layers 31 do not transmit light after being stacked. For example, Figure 7 As shown, the light-blocking structure 3 includes three light-blocking conductive layers 31 and three insulating layers 32. From bottom to top, they are the first insulating layer 321, the first light-blocking conductive layer 311, the second insulating layer 322, the second light-blocking conductive layer 312, the third insulating layer 323, and the third light-blocking conductive layer 313. A plurality of first hollow holes 3101 are formed in the first light-blocking conductive layer 311, a plurality of second hollow holes 3102 are formed in the second light-blocking conductive layer 312, and a plurality of third hollow holes 3103 are formed in the third light-blocking conductive layer 313. The first hollow holes 3101 and the second hollow holes 3102 are staggered in the vertical direction, the second hollow holes 3102 and the third hollow holes 3103 are staggered in the vertical direction, but the first hollow holes 3101 and the third hollow holes 3103 overlap in the vertical direction, so that the first light-blocking conductive layer 311, the second conductive layer, and the third light-blocking conductive layer 313 still do not transmit light after being stacked.
[0039] For example, Figures 2 - 4 As shown, when the light-blocking structure 3 includes only one light-blocking conductive layer 31, no hollow holes 310 are provided on the light-blocking conductive layer 31 to ensure the light shielding effect.
[0040] Preferably, the light-blocking conductive layer 31 is a metal layer, and the total volume of the hollow holes 310 on each light-blocking conductive layer 31 is not less than 45% of the volume of the light-blocking conductive layer 31. When the light-blocking conductive layer 31 is a metal layer, if the volume ratio of the metal is greater than 55%, the light-blocking conductive layer 31 will be delaminated due to excessive stress. Therefore, the total volume of all the hollow holes 310 in the metal layer accounts for no less than 45% of the volume of the metal layer where it is located, ensuring that the photosensitive chip can be mass-produced.
[0041] More preferably, the light-blocking conductive layer 31 is a redistribution layer (RDL), which is convenient for processing and layout. Figure 5 And 7 As shown in the embodiment, the first light-blocking conductive layer 311 is a redistribution layer, which redistributes the IO pins on the analog front-end chip 1, improves the flexibility for complex wiring requirements, avoids digital interference inside the analog front-end chip 1 through reasonable wiring layout, and evaluates the interlayer spacing to ensure that the introduction of the first light-blocking conductive layer 311 will not excessively increase the parasitic capacitance.
[0042] In some embodiments, a signal trace 4 is provided in one of the light-shielding conductive layers 31 of the light-shielding structure 3. By disposing the signal trace 4 in the light-shielding conductive layer 31, the layout of the signal trace 4 is optimized, parasitic parameters are reduced, and interference coupling between traces can be reduced, ensuring high-quality signals. During actual processing, the signal trace 4 is insulated from the light-shielding conductive material in the light-shielding conductive layer 31 where it is located to avoid electrical short circuits. As Figure 4 shown, when the number of layers of the light-shielding conductive layer 31 in the light-shielding structure 3 is one layer, the signal trace 4 is disposed in this layer of the light-shielding conductive layer 31; as Figure 5 and 6 shown, when the number of layers of the light-shielding conductive layer 31 in the light-shielding structure 3 is two layers, the signal trace 4 is disposed in any one of the light-shielding conductive layers 31, that is, any one of the light-shielding conductive layers 31 can be used as a trace layer.
[0043] Hollow holes 310 can be provided in the area between adjacent signal traces 4. The vertical projection of the area where two or more layers of hollow holes 310 are staggeredly arranged falls within the area between adjacent signal traces 4, or it can also be outside the area where the signal trace 4 is located, as long as the signal trace 4 is not truncated. The present application does not make specific limitations. As Figure 6 shown, the vertical projection of the staggered arrangement of the first hollow hole 3101 and the second hollow hole 3102 is outside the area where the signal trace 4 is located.
[0044] When the number of layers of the light-shielding conductive layer 31 is three or more layers, the signal trace 4 can also be disposed in any one of the light-shielding conductive layers 31, that is, any one of the light-shielding conductive layers 31 can be used as a trace layer. Preferably, when the number of layers of the light-shielding conductive layer 31 is three or more layers, the signal trace 4 is disposed in one of the light-shielding conductive layers 31 that is neither the topmost layer nor the bottommost layer among all the light-shielding conductive layers 31, that is, there are light-shielding conductive layers 31 above and below the trace layer, which can not only shield external interference but also shield digital interference inside the analog front-end chip 1. As Figure 7 shown, the signal trace 4 is disposed in the second light-shielding conductive layer 312.
[0045] In the present application, all the light-shielding conductive layers 31 are grounded to form an effective shielding layer, effectively preventing external interference to the signal trace 4.
[0046] The present application effectively prevents external light from interfering with the internal devices of the AFE chip, ensuring the normal operation of the AFE chip.
[0047] The present application also discloses an electronic device, including the photosensing chip described in the above embodiments. The electronic device is a device using the photosensing chip, and can be a laptop computer, a mobile phone, a tablet computer, a projector, a desktop computer, a gaming device, a vehicle-mounted electronic device, a wearable intelligent device, etc.
[0048] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present utility model.
[0049] In the present utility model, unless otherwise clearly defined and limited, terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. It can be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0050] In the description of this specification, the description with reference to terms such as "this embodiment", "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any at least one embodiment or example. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0051] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present utility model, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0052] The above is only the preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent replacements, and simple improvements made to the substantial content of the present utility model shall be included in the protection scope of the present utility model.
Claims
1. A light sensing chip, characterized in that: It comprises an analog front-end chip (1) and a stacked light-blocking structure (3). The light-blocking structure (3) is arranged above the analog front-end chip (1), and comprises at least one light-blocking conductive layer (31) and at least one insulating layer (32), the light-blocking conductive layers (31) and the insulating layers (32) being arranged alternately up and down, the bottom layer of the light-blocking structure (3) being the insulating layer (32), and all the light-blocking conductive layers (31) being grounded.
2. The light sensing chip according to claim 1, characterized in that: The light-blocking conductive layer (31) is a metal layer.
3. The light sensing chip according to claim 1, characterized in that: When the number of the light-blocking conductive layers (31) is two or more, hollow holes (310) are provided on the light-blocking conductive layers (31), and all the light-blocking conductive layers (31) are opaque when stacked.
4. The light sensing chip according to claim 3, characterized in that: The light-blocking conductive layer (31) is a metal layer, and the total volume of the hollow holes (310) on each layer of the light-blocking conductive layer (31) is not less than 45% of the volume of the light-blocking conductive layer (31).
5. The light sensing chip according to claim 3 or 4, characterized in that: The light-blocking conductive layer (31) is a redistribution layer.
6. The light sensing chip according to claim 1, characterized in that: A signal wiring (4) is provided in one of the light-blocking conductive layers (31) of the light-blocking structure (3).
7. The light sensing chip according to claim 6, characterized in that: When the number of the light-blocking conductive layers (31) is three or more, the signal wiring (4) is arranged in one of the light-blocking conductive layers (31) that is not the topmost layer or the bottommost layer among all the light-blocking conductive layers (31).
8. The light sensing chip according to claim 1, characterized in that: Part or all of the light-blocking conductive layer (31) is connected to a ground pin of the analog front-end chip (1).
9. The light sensing chip according to claim 1, characterized in that: The light-blocking conductive layer (31) and the insulating layer (32) are bonded and fixed.
10. An electronic device, characterized in that: A photosensitive chip comprising any one of claims 1 to 9.