Shield gate groove type transistor
By setting stress balance ring trench on the wafer substrate of the shielded gate trench type transistor and filling the passivation glass, the serious warping problem in transistor manufacturing is solved, and the stress balance of the wafer and the reduction of production costs are achieved.
Patent Information
- Application Number
- CN202421729011.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-19
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-07-19
AI Technical Summary
During the manufacturing process, shielded gate trench transistors have severe warping due to stress mismatch, which increases the risk of wafer debris and process difficulty, reduces production efficiency and increases production costs.
A stress balance ring trench surrounding the cut-off ring trench outside the cut-off ring trench is provided in the scribed channel area of the wafer substrate, and passivation glass is filled therein to ensure that the opening directions of the stress balance ring trench, the shield gate trench and the cut-off ring trench are the same to offset the compressive stresses of the original cell area and the cut-off ring area.
By stress balanced by the tensile stress generated by the passivated glass in the ring trench, the compressive stress in the wafer cell and cut-off ring areas is offset, ensuring the stress balance of the wafer, improving warping problems, and reducing fragmentation risks and production costs.
Smart Images
Figure CN222967301U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly, to a shield gate trench transistor. Background Art
[0002] Shield Gate Trench (SGT) transistors are more conducive to the flexible application of semiconductor integrated circuits compared to traditional transistors due to their lower gate-drain capacitance, lower on-resistance, and higher breakdown voltage performance.
[0003] During the fabrication process of conventional trench transistors, after trench etching and filling, stress mismatch problems occur, resulting in warping. And due to the increase in trench width and depth, the warping after filling is more obvious in shield gate trench transistors. Therefore, compared with conventional trench transistors, the shield gate trench transistors have a greater degree of warping, which greatly increases the risk of wafer fragmentation and process difficulty during wafer operation. This significantly reduces production efficiency and increases production costs.
[0004] Therefore, how to improve the warping degree of the wafer and reduce the risk of wafer fragmentation is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Utility Model
[0005] The purpose of this application is to provide a shield gate trench transistor to improve the warping degree of the wafer and reduce the risk of wafer fragmentation.
[0006] To achieve the above purpose, the technical solution adopted in this application is as follows:
[0007] This application provides a shield gate trench transistor, which includes a wafer substrate. The wafer substrate includes a cell region, a cutoff ring region, and a dicing street region; the cutoff ring region surrounds the cell region, and the dicing street region surrounds the cutoff ring region;
[0008] The cell region is provided with shield gate trenches, the cutoff ring region is provided with cutoff ring trenches, the dicing street region is provided with stress balance ring trenches, and the stress balance ring trenches are filled with passivation glass; wherein, the opening directions of the shield gate trenches, the cutoff ring trenches, and the stress balance ring trenches are the same.
[0009] Further, the surface of the passivation glass is flush with the opening surface of the stress balance ring trenches.
[0010] Further, the distance between the stress balance ring trenches and the cutoff ring trenches is 1um - 3um.
[0011] Further, the distance between the stress balance ring trenches and the cutoff ring trenches is 2um.
[0012] Furthermore, the ratio of the depth of the shielding gate trench to the depth of the stress balance ring trench is 1:1 to 1.05.
[0013] Furthermore, the depth of the stress balance ring trench is the same as the depth of the shielding gate trench.
[0014] Furthermore, the ratio of the width of the shielding gate trench to the width of the stress balance ring trench is 1:1 to 1.05.
[0015] Furthermore, the width of the stress balance ring trench is the same as the width of the shielding gate trench.
[0016] Furthermore, the shielding gate trench type transistor further includes an isolation layer, the isolation layer is disposed on a side of the wafer substrate close to the stress balance ring trench, and the isolation layer exposes the stress balance ring trench.
[0017] Furthermore, the isolation layer includes a plasma enhanced silicon oxide layer and a borophosphosilicate glass layer, the plasma enhanced silicon oxide layer is disposed on a side of the wafer substrate close to the stress balance ring trench, and the borophosphosilicate glass layer is disposed on a side of the plasma enhanced silicon oxide layer away from the wafer substrate.
[0018] Compared with the prior art, the present application has the following beneficial effects:
[0019] The present application provides a shielding gate trench type transistor, which includes a wafer substrate, and the wafer substrate includes a cell region, a cutoff ring region and a dicing street region. Among them, the cutoff ring region surrounds the cell region, and the dicing street region surrounds the cutoff ring region. The cell region is provided with a shielding gate trench, the cutoff ring region is provided with a cutoff ring trench, the dicing street region is provided with a stress balance ring trench, and the stress balance ring trench is filled with a passivation glass. And, the opening directions of the shielding gate trench, the cutoff ring trench and the stress balance ring trench are the same.
[0020] Since the thick oxide layer and polysilicon in the shielding gate trench in the cell region and the cutoff ring trench in the cutoff ring region will bring outward stress (compressive stress), resulting in warping of the wafer substrate. The present application provides a stress balance ring trench surrounding the cutoff ring trench in the dicing street region of the wafer substrate, and the stress balance ring trench has the same opening direction as the shielding gate trench and the cutoff ring trench, that is, it is ensured that the stress balance ring trench, the shielding gate trench and the cutoff ring trench are all located on the same side of the wafer substrate. By filling the stress balance ring trench with a passivation glass, since the expansion coefficient of the passivation glass is much larger than that of silicon, therefore, the passivation glass in the stress balance ring trench will generate inward stress (tensile stress), thereby offsetting the compressive stress in the wafer cell region and the cutoff ring region, ensuring the stress balance of the wafer, improving the warping of the wafer, and further reducing the risk of fragments in wafer manufacturing, greatly reducing the production cost.
[0021] To make the above objects, features, and advantages of the present application more obvious and understandable, the following provides preferred embodiments in conjunction with the accompanying drawings and describes them in detail as follows. Description of the Drawings
[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application to be protected, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.
[0023] Figure 1 It is a cross-sectional schematic diagram of a shielded gate trench transistor in the prior art;
[0024] Figure 2 It is a cross-sectional schematic diagram of a shielded gate trench transistor provided by the present application;
[0025] Figure 3 It is a cross-sectional schematic diagram corresponding to step S10 provided by the present application;
[0026] Figure 4 It is a cross-sectional schematic diagram corresponding to step S20 provided by the present application;
[0027] Figure 5 It is a cross-sectional schematic diagram corresponding to step S30 provided by the present application;
[0028] Figure 6 It is a cross-sectional schematic diagram corresponding to step S40 provided by the present application.
[0029] Reference numerals: 10 - shielded gate trench transistor; 100 - wafer substrate; 110 - cell region; 111 - shielded gate trench; 120 - cutoff ring region; 121 - cutoff ring trench; 130 - dicing street region; 131 - stress balance ring trench; 132 - passivation glass; 200 - isolation layer; 210 - plasma enhanced silicon oxide layer; 220 - borophosphosilicate glass layer; 20 - shielded gate trench structure; 30 - oxide layer; 40 - polysilicon. Detailed Embodiments
[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents the selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.
[0031] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0032] In the description of the present application, it should be noted that relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. The term "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium.
[0033] The following will make a detailed description of some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0034] Please refer to Figure 1 , as described in the background art, when the shield gate trench structure 20 is provided on the front side of the wafer, since internal compressive stress (outward stress) is easily formed when the oxide layer 30 and polysilicon 40 are grown and deposited in the shield gate trench structure 20, the wafer bends downward and warping occurs.
[0035] Wafer warping will cause difficulties in subsequent chip processing. The reasons are as follows: warping makes it impossible to smoothly expose the entire wafer in the lithography process. Warping makes it difficult for a large number of semiconductor devices such as lithography machines to automatically handle the wafer. The wafer cannot be vacuum adsorbed by the tray, is easy to slide off and turn over from the tray, and cannot be positioned in the equipment chamber by vacuum adsorption.
[0036] In semiconductor wafer processing, the deep trench process will break the stress balance of the wafer epitaxial wafer itself. Excessive stress will cause serious wafer warping, greatly increasing the risk of wafer fragmentation, and the fragmentation rate is as high as 5%-10%. This not only delays time, reduces production efficiency, but also greatly increases the cost of semiconductor wafer processing.
[0037] Therefore, how to improve the warpage of the wafer and reduce the risk of wafer fragmentation is a technical problem that needs to be urgently solved by those skilled in the art.
[0038] To solve the above technical problems, please refer to Figure 2 , an embodiment of the present application provides a shielded gate trench transistor 10. The shielded gate trench transistor 10 includes a wafer substrate 100, and the wafer substrate 100 includes a cell region 110, a cut-off ring region 120, and a dicing street region 130. Among them, the cut-off ring region 120 surrounds the cell region 110, and the dicing street region 130 surrounds the cut-off ring region 120.
[0039] The cell region 110 is provided with shielded gate trenches 111, the cut-off ring region 120 is provided with cut-off ring trenches 121, the dicing street region 130 is provided with stress balance ring trenches 131, and the stress balance ring trenches 131 are filled with passivation glass 132. That is, the cut-off ring trenches 121 surround the shielded gate trenches 111, the stress balance ring trenches 131 surround the cut-off ring trenches 121, and there is a certain distance between the stress balance ring trenches 131 and the cut-off ring trenches 121. And, the opening directions of the shielded gate trenches 111, the cut-off ring trenches 121, and the stress balance ring trenches 131 are the same.
[0040] Based on the above design, since the thick oxide layer and polysilicon in the shielded gate trenches 111 in the cell region 110 and the cut-off ring trenches 121 in the cut-off ring region 120 will bring outward stress (compressive stress), resulting in warpage of the wafer substrate 100. In the embodiment of the present application, a stress balance ring trench 131 surrounding the cut-off ring trenches 121 is provided in the dicing street region 130 of the wafer substrate 100, and the stress balance ring trench 131 has the same opening direction as the shielded gate trenches 111 and the cut-off ring trenches 121, that is, it is ensured that the stress balance ring trench 131, the shielded gate trenches 111, and the cut-off ring trenches 121 are all located on the same side of the wafer substrate 100.
[0041] By filling the stress balance ring trenches 131 with passivation glass 132, since the expansion coefficient of the passivation glass 132 is much larger than that of silicon, therefore, the passivation glass 132 in the stress balance ring trenches 131 will generate inward stress (tensile stress), thereby offsetting the compressive stress in the cell region 110 and the cut-off ring region 120 of the wafer, ensuring the stress balance of the wafer, improving the warpage of the wafer, and further reducing the risk of fragmentation in wafer manufacturing, greatly reducing the production cost.
[0042] In the embodiment of the present application, the stress balance ring trenches 131 surround the cut-off ring trenches 121, and there is a certain distance between the stress balance ring trenches 131 and the cut-off ring trenches 121. Optionally, the distance between the stress balance ring trenches 131 and the cut-off ring trenches 121 can be 1um to 3um.
[0043] Preferably, the distance between the stress balance ring trench 131 and the cutoff ring trench 121 is 2 μm.
[0044] In order to better balance the stress of the wafer, as an alternative embodiment, the surface of the passivation glass 132 is flush with the opening surface of the stress balance ring trench 131. That is, the inside of the stress balance ring trench 131 is filled with the passivation glass 132.
[0045] Furthermore, in order to improve the effect of the stress balance ring trench 131 in balancing the wafer stress, in the embodiment of the present application, the ratio of the depth of the shielding gate trench 111 to the depth of the stress balance ring trench 131 is 1:1 to 1.05. The ratio of the width of the shielding gate trench 111 to the width of the stress balance ring trench 131 is 1:1 to 1.05.
[0046] That is, the minimum depth of the stress balance ring trench 131 is the same as the depth of the shielding gate trench 111, and the maximum depth of the stress balance ring trench 131 is 105% of the depth of the shielding gate trench 111. Similarly, the minimum width of the stress balance ring trench 131 is the same as the width of the shielding gate trench 111, and the maximum width of the stress balance ring trench 131 is 105% of the width of the shielding gate trench 111. For example, if the depth of the shielding gate trench 111 is 6 μm and the width of the shielding gate trench 111 is 4 μm. Then the depth of the stress balance ring trench 131 is 6 μm to 6.3 μm, and the width of the stress balance ring trench 131 is 4 μm to 4.2 μm.
[0047] Preferably, in the embodiment of the present application, the depth of the stress balance ring trench 131 is the same as the depth of the shielding gate trench 111, and the width of the stress balance ring trench 131 is the same as the width of the shielding gate trench 111.
[0048] As an alternative embodiment, the shielding gate trench type transistor 10 further includes an isolation layer 200. The isolation layer 200 is disposed on one side of the wafer substrate 100 close to the stress balance ring trench 131, and the isolation layer 200 exposes the stress balance ring trench 131.
[0049] In the embodiment of the present application, the isolation layer 200 includes a plasma enhanced silicon oxide layer 210 and a borophosphosilicate glass layer 220. Among them, the plasma enhanced silicon oxide layer 210 is disposed on one side of the wafer substrate 100 close to the stress balance ring trench 131, and the borophosphosilicate glass layer 220 is disposed on the side of the plasma enhanced silicon oxide layer 210 away from the wafer substrate 100. The plasma enhanced silicon oxide layer 210 is used to isolate mobile ions, and the borophosphosilicate glass layer 220 is used to isolate transistor devices and interconnect metal layers.
[0050] Optionally, the plasma enhanced silicon oxide can be replaced by tetraethyl orthosilicate (TEOS).
[0051] In addition, an embodiment of the present application further provides a method for manufacturing a shielded gate trench transistor 10. The method includes the following steps:
[0052] Step S10: After the source injection is completed on the wafer substrate, an isolation layer deposition process is performed on the front side of the wafer substrate.
[0053] Please refer to Figure 3 , in an embodiment of the present application, after the source injection is completed on the wafer substrate 100, an isolation layer 200 deposition process is performed on the front side of the wafer substrate 100. Among them, the isolation layer 200 includes a plasma-enhanced silicon oxide layer 210 and a borophosphosilicate glass layer 220. The plasma-enhanced silicon oxide layer 210 is disposed on one side of the wafer substrate 100 close to the stress balance ring trench 131, and the borophosphosilicate glass layer 220 is disposed on the side of the plasma-enhanced silicon oxide layer 210 away from the wafer substrate 100.
[0054] Step S20: Perform photoresist coating, exposure, and development, and etch the isolation layer corresponding to the scribing lane area.
[0055] Please refer to Figure 4 , in an embodiment of the present application, the wafer substrate 100 with the isolation layer 200 is subjected to photoresist coating, exposure, and development, and the isolation layer 200 corresponding to the scribing lane area 130 is etched to the surface of the wafer substrate 100. Among them, the distance between the etching position and the cutoff ring trench 121 is 2 um.
[0056] Step S30: Etch a circle of trenches in the scribing lane area to form a stress balance ring groove.
[0057] Please refer to Figure 5 , in an embodiment of the present application, a circle of trenches is etched in the scribing lane area 130 to form a stress balance ring trench 131, that is, the stress balance ring trench 131 surrounds the cutoff ring trench 121.
[0058] Step S40: Fill the stress balance ring groove with passivation glass, perform wet etching back and then annealing to obtain a shielded gate trench transistor.
[0059] In an embodiment of the present application, the passivation glass 132 is filled into the stress balance ring trench 131, wet etching back is performed and then annealing is carried out, and finally the shielded gate trench transistor 10 as shown in Figure 6 is obtained. Among them, the wet etching solvent is HCL:H 2 O 2 :H 2 O = 1:1:10, and the cleaning time is 10 s to 20 s.
[0060] In summary, the embodiment of the present application provides a shield gate trench transistor. The shield gate trench transistor includes a wafer substrate, and the wafer substrate includes a cell region, a cutoff ring region, and a scribe line region. Among them, the cutoff ring region surrounds the cell region, and the scribe line region surrounds the cutoff ring region. The cell region is provided with shield gate trenches, the cutoff ring region is provided with cutoff ring trenches, the scribe line region is provided with stress balance ring trenches, and the stress balance ring trenches are filled with passivation glass. Moreover, the opening directions of the shield gate trenches, the cutoff ring trenches, and the stress balance ring trenches are the same.
[0061] By providing a stress balance ring trench surrounding the cutoff ring trench in the scribe line region of the wafer substrate, and the stress balance ring trench has the same opening direction as the shield gate trench and the cutoff ring trench, that is, it ensures that the stress balance ring trench, the shield gate trench, and the cutoff ring trench are all located on the same side of the wafer substrate. By filling the stress balance ring trench with passivation glass, since the coefficient of thermal expansion of the passivation glass is much larger than that of silicon, therefore, the passivation glass in the stress balance ring trench will generate an inward stress (tensile stress), thereby offsetting the compressive stress in the wafer cell region and the cutoff ring region, ensuring the stress balance of the wafer, improving the warping of the wafer, and further reducing the risk of fragments in wafer manufacturing, greatly reducing the production cost.
[0062] The foregoing is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
[0063] For those skilled in the art, it is obvious that the present application is not limited to the details of the above-described exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, it is intended to include all changes falling within the meaning and scope of the equivalent elements of the claims in the present application. Any reference signs in the claims should not be regarded as limiting the claimed rights.
Claims
1. A shielded gate trench transistor, characterized in that: The shielded gate trench transistor comprises a wafer substrate, wherein the wafer substrate comprises a primary cell region, a cut-off ring region and a scribe lane region; the cut-off ring region surrounds the primary cell region, and the scribe lane region surrounds the cut-off ring region; The original cell region is provided with a shielding gate groove, the cut-off ring region is provided with a cut-off ring groove, the scribe line region is provided with a stress balance ring groove, and the stress balance ring groove is filled with passivation glass; wherein the opening directions of the shielding gate groove, the cut-off ring groove and the stress balance ring groove are all the same.
2. The shielded gate trench transistor according to claim 1, wherein: The surface of the passivation glass is flush with the opening surface of the stress balance ring groove.
3. The shielded gate trench transistor according to claim 1, wherein: The distance between the stress balance ring groove and the cut-off ring groove is 1 um to 3 um.
4. The shielded gate trench transistor according to claim 3, characterized in that: The distance between the stress balance ring groove and the cut-off ring groove is 2 um.
5. The shielded gate trench transistor according to claim 1, wherein: The ratio of the depth of the shielding gate groove to the depth of the stress balance ring groove is 1:1 to 1.
05.
6. The shielded gate trench transistor according to claim 5, characterized in that: The depth of the stress balance ring groove is the same as the depth of the shielding gate groove.
7. The shielded gate trench transistor according to claim 1, wherein: The ratio of the width of the shielding gate groove to the width of the stress balance ring groove is 1:1 to 1.
05.
8. The shielded gate trench transistor according to claim 7, wherein: The width of the stress balance ring groove is the same as the width of the shielding gate groove.
9. The shielded gate trench transistor according to claim 1, wherein: The shielded gate trench transistor further includes an isolation layer, which is disposed on a side of the wafer substrate close to the stress balance ring trench, and the isolation layer exposes the stress balance ring trench.
10. The shielded gate trench transistor according to claim 9, characterized in that: The isolation layer includes a plasma enhanced silicon oxide layer and a borophosphosilicate glass layer. The plasma enhanced silicon oxide layer is arranged on a side of the wafer substrate close to the stress balance ring groove, and the borophosphosilicate glass layer is arranged on a side of the plasma enhanced silicon oxide layer away from the wafer substrate.