SiCVDMOS device capable of improving electric field concentration in P-well region

Abstract

The utility model relates to a SiCVDMOS device capable of improving electric field concentration in a P-well region. Relates to the technical field of semiconductors. Comprising a drain metal layer, an N + substrate layer, an N-type buffer layer and an N-drift layer which are sequentially arranged from bottom to top; the N-drift layer is provided with a P-Well region which extends downwards from the top surface of the N-drift layer, and the side, close to the middle part, of the P-Well region is an inclined surface; the N + region extends downwards from the top surface of the P-Well region; the P + region extends downwards from the top surface of the P-Well region and is connected with the N + region; the gate oxide layer is arranged on the top surface of the N-drift layer, and the bottom surface of the gate oxide layer is respectively connected with the N + region, the P-Well region and the N-drift layer; the Poly layer is formed on the top surface of the gate oxide layer; the dielectric layer wraps the gate oxide layer and the Poly layer and is connected with the N + region; the source ohmic contact alloy layer is formed on the top surfaces of the P + region and the N + region, and the side part of the source ohmic contact alloy layer is connected with the dielectric layer; and the source electrode metal layer is formed on the top surfaces of the source electrode ohmic contact alloy layer and the dielectric layer. According to the utility model, the over-current capability of the chip is enhanced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiCVDMOS device with improved electric field concentration in the P-well region. Background Art

[0002] Power electronic conversion has gradually entered the high-voltage and ultra-high-voltage fields. High-voltage power devices are the decisive factors restricting the volume / power consumption and efficiency of converters. Higher requirements are imposed on high-voltage power devices in fields such as ultra-high-voltage AC / DC power transmission, new energy grid connection, and electric vehicles. Currently, silicon (Si) material devices are developed maturely, widely used, and have reliable performance. However, their properties such as small bandgap width, breakdown electric field, and thermal conductivity greatly restrict their applications at high power, high voltage, and high frequency. As one of the wide-bandgap semiconductors, SiC breaks the limit of Si materials with its excellent properties such as higher bandgap width, breakdown field strength, and thermal conductivity than Si materials, and shows superior performance such as lower power loss and higher switching frequency in high-voltage level and high-power electric energy conversion applications, having great potential.

[0003] In the blocking state of the devices in the prior art, the edge curvature of the ion implantation region is small, and the phenomenon of electric field concentration is likely to occur, resulting in serious degradation of the blocking performance of the devices and a significant reduction in the breakdown voltage. Especially for 4H-SiC materials, its diffusion coefficient is smaller than that of Si. For shallow junction devices such as MOSFETs and IGBTs, the curvature effect is more serious. Therefore, electric field concentration is likely to occur at the edge of the P-Well region of high-voltage SiCMOSFETs. How to improve the electric field concentration phenomenon of SiCVDMOS devices is an urgent problem to be solved. Summary of the Utility Model

[0004] The utility model provides a SiCVDMOS device with improved electric field concentration in the P-well region, which reduces the electric field concentration effect and optimizes the blocking performance of the device.

[0005] The technical solution of the utility model is as follows:

[0006] A SiCVDMOS device with improved electric field concentration in the P-well region includes a drain metal layer, an N + substrate layer, an N-type buffer layer, and an N - drift layer, which are arranged in sequence from bottom to top;

[0007] On the N - drift layer, there are provided:

[0008] A P-Well region extends downward from the top surface of the N - drift layer, and one side close to the middle is in the shape of an inclined plane;

[0009] N+ region, extending downward from the top surface of the P-Well region;

[0010] P + region, extending downward from the top surface of the P-Well region and connected to the N + region;

[0011] gate oxide layer, disposed on the top surface of the N - drift layer, the bottom surface of which is respectively connected to the N + region, P-Well region and N - drift layer;

[0012] Poly layer, formed on the top surface of the gate oxide layer;

[0013] dielectric layer, wrapping the gate oxide layer and the Poly layer and connected to the N + region;

[0014] source ohmic contact alloy layer, formed on the top surfaces of the P + region and N + region, the side portion of which is connected to the dielectric layer;

[0015] source metal layer, formed on the top surfaces of the source ohmic contact alloy layer and the dielectric layer.

[0016] Specifically, the growth thickness of the gate oxide layer is 40 - 60 nm.

[0017] Specifically, the thickness of the source ohmic contact alloy layer is 0.5 - 0.8 um.

[0018] Specifically, the thickness of the N + substrate layer is 360 - 400 um.

[0019] Specifically, the thickness of the N-type buffer layer is 0.8 - 1.2 um.

[0020] Specifically, the thickness of the N-drift layer is 5 - 15 um.

[0021] The present utility model improves the bottom corner of the P-Well region inside the SiCVDMOS device, reducing the curvature of the corner. In this way, when the device is in the blocking state, due to the reduction of the curvature of the bottom corner of the P-Well region of the device, the electric field concentration effect is reduced, and the blocking performance of the device is optimized; similarly, the shape of the P-Well region that is wider at the top and narrower at the bottom also results in a reduction of the JFET resistance in this part, enhancing the over-current capacity of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic cross-sectional structure diagram of the device of the present utility model;

[0023] Figure 2 is the structural schematic diagram of step S100 of the present utility model;

[0024] Figure 3 is the structural schematic diagram of step S200 of the present utility model;

[0025] Figure 4 is the structural schematic diagram of step S300 of the present utility model;

[0026] Figure 5 is the structural schematic diagram of step S400 of the present utility model;

[0027] Figure 6 is the structural schematic diagram of step S500 of the present utility model;

[0028] Figure 7 is the structural schematic diagram of step S600 of the present utility model;

[0029] Figure 8 is the structural schematic diagram of step S700 of the present utility model;

[0030] Figure 9 is the structural schematic diagram of step S800 of the present utility model;

[0031] Figure 10 is the structural schematic diagram of step S900 of the present utility model;

[0032] Figure 11 is the structural schematic diagram of step S1000 of the present utility model;

[0033] Figure 12 is the structural schematic diagram of step S1100 of the present utility model;

[0034] In the figure, 1 is the drain metal layer, 2 is the N + substrate layer, 3 is the N-type buffer layer, 4 is the N - drift layer, 5 is the P-Well region, 6 is the P + region, 7 is the source ohmic contact alloy layer, 8 is the N + region, 9 is the gate oxide layer, 10 is the Poly layer, 11 is the dielectric layer, 12 is the source metal layer, 13 is the photoresist, 14 is the photomask. Detailed implementation manners

[0035] The present utility model will be described in detail below in combination with specific actual cases. Examples of the embodiments are shown in the accompanying drawings. The illustrative embodiments and descriptions of the present utility model are only used to explain the present utility model and do not serve as a limitation to the present utility model.

[0036] Preparation method of SiCVDMOS device with improved electric field concentration in P-well region, comprising the following steps:

[0037] S100, referring to Figure 2 as shown, form an N-type buffer layer 3 on the heavily doped N + substrate layer 2;

[0038] The N + substrate layer 2 in step S100 is doped with N ions, with a thickness of 360 - 400 um and a doping concentration of 1e 19 cm -2 ±10%. The N-type buffer layer 3 is also doped with N ions, with a thickness of 0.8 - 1.2 um and a doping concentration of 1e 18 cm -2 ±10%.

[0039] S200, referring to Figure 3 as shown, epitaxially grow a lightly doped N-drift layer 4 on the N-type buffer layer 3;

[0040] The N-drift layer 4 in step S200 is doped with N ions, with a thickness of 5 - 15 um and a doping concentration of 5e 15 -2e 16 cm -2 .

[0041] S300, referring to Figure 4 as shown, dispose a photoresist 13 on the N-drift layer 4, and through a photomask 14, perform photolithography and development on the photoresist 13 to form a gentle slope angle region;

[0042] The photoresist 13 in step S300 utilizes the diffraction effect of light passing through a photomask 14 with slits, so that the light passing through the slit region diffracts outward. Thus, after the photolithography and development process, a gentle slope angle region is formed at the edge of the photoresist 13.

[0043] S400, referring to Figure 5 as shown, form a lightly doped P-Well region 5 on the N-drift layer 4 by ion implantation;

[0044] The P-Well region 5 in step S400 is doped with Al ions, with a doping concentration of 1e 17 -1e 18 cm -2 , and through the photoresist 13, pattern transfer is performed to form an injection region similar to an inverted right trapezoid, so that the corner curvature at the bottom end of the P-Well region 5 is reduced.

[0045] S500, referring to Figure 6 as shown, form a heavily doped N - on the drift layer 4 by ion implantation+ Region 8;

[0046] N in step S500 + In region 8, N ions are doped, and the doping concentration is 1e 18 -5e 18 cm -2 In this case, the ion implantation self-alignment process is adopted, and sidewalls are used to block to form a smaller channel width.

[0047] S600, refer to Figure 7 As shown, on the top surface of the N - drift layer 4, a heavily doped P + region 6 is formed by ion implantation, and then ion activation is carried out;

[0048] P in step S600 + In region 6, Al ions are doped, and the doping concentration is 5e 18 -1e 19 cm -2 ; In this case, a high-temperature annealing furnace is adopted. After covering the C film, annealing is carried out. The annealing temperature is 1650 - 1750 °C, and the annealing time is 10 - 30 min for ion activation; P + The depths of region 6 and N + region 8 are both less than the depth of the P-Well region 5.

[0049] S700, refer to Figure 8 As shown, on the N - drift layer 4, a gate oxide layer 9 is formed by dry oxygen thermal oxidation process, and a channel is formed at the interface with the P-Well region 5;

[0050] For the gate oxide layer 9 in step S700, the growth temperature is 1250 - 1350 °C, the growth thickness is 40 - 60 nm, and then NO annealing treatment is required. The annealing temperature is 1250 °C, and the time is 1H to improve the densification of the gate oxide layer 9 and reduce defects.

[0051] S800, refer to Figure 9 As shown, a Poly layer 10 is deposited on the gate oxide layer 9 to lead out the gate electrode;

[0052] S900, refer to Figure 10 As shown, a dielectric layer 11 is deposited on the Poly layer 10 to isolate the gate electrode and the source electrode metal;

[0053] S1000, refer to Figure 11 As shown, an ohmic contact window is opened on the gate oxide layer 9, Poly layer 10 and dielectric layer 11 by dry etching, and Ni metal is sputtered and alloyed at high temperature to form the source ohmic contact alloy layer 7;

[0054] S1100, refer toFigure 12 As shown, a source metal layer 12 is formed on the dielectric layer 11 and the source ohmic contact alloy layer 7 by Ti / AlCu metal sputtering to lead out a source electrode;

[0055] In step S1100, for the source ohmic contact alloy layer 7, an annealing temperature of 1000 °C and an annealing time of 5 min are adopted to form an alloy with a thickness of 0.5 - 0.8 um to achieve an ohmic contact effect.

[0056] S1200, referring to Figure 1 As shown, on the back of the N+ substrate layer 2, the thickness of the N+ substrate layer 2 is reduced by a back thinning process, and then a drain metal layer 1 is formed by sputtering Ni metal and evaporating Ti / Ni / Ag metal to lead out a drain electrode.

[0057] In step S1200, for the drain metal layer 1, laser annealing is required after Ni metal sputtering, and the laser energy is 2 - 4 mJ / cm 2 ; then Ti / Ni / Ag or Ni / Pb / Au is evaporated later with a thickness of 1.4 - 2 um.

[0058] A SiCVDMOS device with improved electric field concentration in the P-well region includes a drain metal layer 1, an N + substrate layer 2, an N-type buffer layer 3, and an N - drift layer 4, which are arranged successively from bottom to top;

[0059] The N - drift layer 4 is provided with:

[0060] A P-Well region 5 extends downward from the top surface of the N - drift layer 4 and has an inclined surface on one side near the middle, that is, the P-Well region 5 has a right trapezoidal structure;

[0061] An N + region 8 extends downward from the top surface of the P-Well region 5, and its bottom surface is higher than the bottom surface of the P-Well region 5;

[0062] A P + region 6 extends downward from the top surface of the P-Well region 5 and is connected to the N + region 8;

[0063] A gate oxide layer 9 is arranged on the top surface of the N - drift layer 4, and its bottom surface is respectively connected to the N + region 8, the P-Well region 5, and the N - drift layer 4;

[0064] A Poly layer 10 is formed on the top surface of the gate oxide layer 9;

[0065] The dielectric layer 11 is wrapped on the gate oxide layer 9 and the Poly layer 10 and is connected to the N + region 8;

[0066] The source ohmic contact alloy layer 7 is formed on the top surfaces of the P + region 6 and the N + region 8, and the side is connected to the dielectric layer 11;

[0067] The source metal layer 12 is formed on the top surfaces of the source ohmic contact alloy layer 7 and the dielectric layer 11.

[0068] The inner bottom feet of the P-Well region 5 are in an arc structure, that is, an arc chamfer is provided.

[0069] The cross-section of the P-Well region 5 is in a structure with a larger upper part and a smaller lower part. Figure 5 The included angle a between the inclined plane of the P-Well region 5 near the middle region and the bottom surface of the P-Well region 5 must be less than 90°, effectively improving the electric field concentration phenomenon caused by the curvature effect, thereby avoiding premature breakdown of the device at this place.

[0070] The present utility model improves the bottom corner of the P-Well region 5 inside the SiCVDMOS device, reducing the curvature of the corner. In this way, when the device is in the blocking state, due to the reduction of the curvature of the bottom corner of the P-Well region 5 of the device, the electric field concentration effect is reduced, and the blocking performance of the device is optimized.

[0071] The on-resistance of the SiCVDMOS device chip is mainly composed of four parts: channel resistance, accumulation layer resistance, JEFT resistance, and drift region resistance. The upper-wide and lower-narrow shape of the P-Well region 5 of the present utility model reduces the JEFT effect of the P-Well region 5, resulting in a reduction of the JFET resistance in this part and enhancing the over-current capacity of the chip.

Claims

1. A SiCVDMOS device with improved electric field concentration in the P-well region, characterized in that: The drain metal layer (1), N + Substrate layer (2), N-type buffer layer (3) and N - Drift layer (4); The N - The drift layer (4) is provided with: P-Well area (5), from the N - The top surface of the drift layer (4) extends downward, and a side close to the middle thereof is an inclined surface; N + A region (8) extending downward from the top surface of the P-Well region (5); P + Region (6) extends downward from the top surface of the P-Well region (5) and is connected to the N + Area (8) connection; The gate oxide layer (9) is arranged on the N - The top surface and bottom surface of the drift layer (4) are respectively connected to the N + Zone (8), P-Well Zone (5) and N - Drift layer (4) connection; A Poly layer (10) formed on the top surface of the gate oxide layer (9); The dielectric layer (11) is wrapped on the gate oxide layer (9) and the Poly layer (10) and is connected to the N + Area (8) connection; The source ohmic contact alloy layer (7) is formed on the P + Area (6) and N + The top surface and the side of the region (8) are connected to the dielectric layer (11).

2. The SiCVDMOS device with improved P-well region electric field concentration according to claim 1, characterized in that: The gate oxide layer (9) has a growth thickness of 40-60 nm.

3. The SiCVDMOS device with improved P-well region electric field concentration according to claim 1, characterized in that: The source ohmic contact alloy layer (7) has a thickness of 0.5-0.8 um.

4. The SiCVDMOS device with improved P-well region electric field concentration according to claim 1, characterized in that: The N + The thickness of the substrate layer (2) is 360-400 um.

5. The SiCVDMOS device with improved electric field concentration in the P-well region according to claim 1, characterized in that: The thickness of the N-type buffer layer (3) is 0.8-1.2 um.

6. The SiCVDMOS device with improved P-well region electric field concentration according to claim 1, characterized in that: The N - The thickness of the drift layer (4) is 5-15 um.

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