Low-temperature-drift band-gap reference circuit

Abstract

The utility model provides a low-temperature-drift band-gap reference circuit, which is characterized in that a zero-temperature-drift current and a first mirror current and a second mirror current of the zero-temperature-drift current are generated through a zero-temperature-drift current generation circuit, and a negative-temperature-coefficient current is generated through a negative-temperature-coefficient current generation circuit. Obtaining a high-temperature compensation current according to a difference value between the first mirror image current and the negative temperature coefficient current, obtaining a low-temperature compensation current according to a difference value between the negative temperature coefficient current and the second mirror image current, and obtaining a third mirror image current of the zero-temperature-drift current based on a mirror image unit of the reference output circuit; finally, the reference voltage is generated under the action of the first load unit, the second load unit and the third load unit, and the temperature coefficient and the voltage value of the reference voltage can be directly influenced by the impedance value of each load unit, so that the temperature coefficient and the voltage value of the reference voltage can be adjusted by adjusting the impedance value of each load unit. Finally, low-temperature-drift output and voltage value adjustability of the reference voltage are achieved.

Description

Technical Field

[0001] This application relates to the technical field of reference circuits, and particularly to a low-temperature-drift bandgap reference circuit. Background Art

[0002] With the continuous improvement of chip performance, higher requirements are put forward for circuit design, and the performance of reference circuits (including voltage and temperature coefficient) becomes an important performance index. Conventional reference circuit structures are as Figure 1 shown. MOS transistor PM1 forms a current mirror with MOS transistors PM2 and PM3 respectively, and MOS transistor NM1 forms a current mirror with MOS transistor NM2. Therefore, their voltages to the ground are equal. Let the voltage between the base and emitter of transistor Q1 be VBE1, the voltage between the base and emitter of transistor Q2 be VBE2, and the voltage between the base and emitter of transistor Q3 be VBE3. This reference circuit has only a first-order zero-temperature-coefficient output, and the temperature coefficient is greatly affected by the process. The output reference voltage can be expressed as VREF = (VBE2 - VBE1) / R1*R2 + VBE3. To ensure a specific temperature coefficient, the parameters of each component are not adjustable, so the value of the reference voltage VREF is also not adjustable. Summary of the Utility Model

[0003] This application provides a low-temperature-drift bandgap reference circuit with adjustable temperature coefficient and reference voltage.

[0004] A low-temperature-drift bandgap reference circuit includes:

[0005] A zero-temperature-drift current generation circuit for generating a zero-temperature-drift current and a first mirror current and a second mirror current of the zero-temperature-drift current;

[0006] A negative-temperature-coefficient current generation circuit for generating a negative-temperature-coefficient current;

[0007] A compensation temperature current generation circuit, connected to the zero-temperature-drift current generation circuit and the negative-temperature-coefficient current generation circuit respectively, for performing a difference operation on the first mirror current and the negative-temperature-coefficient current to obtain a high-temperature compensation current, and performing a difference operation on the negative-temperature-coefficient current and the second mirror current to obtain a low-temperature compensation current;

[0008] A reference output circuit includes a mirror unit, a first load unit, a second load unit, and a third load unit; the mirror unit is connected to the zero-temperature-drift current generation circuit for mirroring the zero-temperature-drift current to obtain a third mirror current; the mirror unit, the first load unit, the second load unit, the third load unit, and the ground terminal are connected in sequence, and a common connection terminal of the first load unit and the second load unit is used to receive a first compensation current, and a common connection terminal of the second load unit and the third load unit is used to receive a second compensation current, so as to generate a reference voltage at a common connection terminal of the mirror unit and the first load unit; wherein one of the first compensation current and the second compensation current is the low-temperature compensation current, and the other is the high-temperature compensation current.

[0009] In one embodiment, the zero-temperature-drift current generation circuit includes an operational amplifier, MOS transistor PM1, MOS transistor PM2, transistor Q1, transistor Q2, resistor R1, resistor R2, and resistor R3; an output terminal of the operational amplifier is respectively connected to a control terminal of the MOS transistor PM1 and a control terminal of the MOS transistor PM2; a first connection terminal of the MOS transistor PM1 and a first connection terminal of the MOS transistor PM2 are respectively used to receive a power supply voltage; a second connection terminal of the MOS transistor PM1, a first input terminal of the operational amplifier, a first end of the resistor R1, and a first end of the resistor R2 are commonly connected; a second connection terminal of the MOS transistor PM2, a second input terminal of the operational amplifier, a first end of the resistor R3, and a first connection terminal of the transistor Q2 are commonly connected; a second end of the resistor R1 is connected to a first connection terminal of the transistor Q1; a second end of the resistor R2, a second end of the resistor R3, a control terminal and a second connection terminal of the transistor Q1, and a control terminal and a second connection terminal of the transistor Q2 are commonly connected and connected to the ground terminal.

[0010] In one embodiment, the zero-temperature-drift current generation circuit further includes MOS transistor PM3 and MOS transistor PM4; a control terminal of the MOS transistor PM3 and a control terminal of the MOS transistor PM4 are respectively connected to the control terminal of the MOS transistor PM1; a first connection terminal of the MOS transistor PM3 and a first connection terminal of the MOS transistor PM4 are respectively used to receive the power supply voltage; a second connection terminal of the MOS transistor PM3 is connected to the compensation temperature current generation circuit for outputting the first mirror current; a second connection terminal of the MOS transistor PM4 is connected to the compensation temperature current generation circuit for outputting the second mirror current.

[0011] In one embodiment, the negative temperature coefficient current generating circuit includes a startup circuit, MOS transistor PM5, MOS transistor PM6, MOS transistor NM1, MOS transistor NM2, transistor Q3, and resistor R4; the first connection terminals of the MOS transistor PM5 and the MOS transistor PM6 are respectively used to receive the power supply voltage; the control terminal and the first connection terminal of the MOS transistor PM5, the control terminal of the MOS transistor PM6, the first connection terminal of the MOS transistor NM1, and the startup circuit are commonly connected; the second connection terminal of the MOS transistor NM1 is connected to the first connection terminal of the transistor Q3; the control terminal, the control terminal and the first connection terminal of the MOS transistor NM2, and the first connection terminal of the MOS transistor PM6 are commonly connected; the second connection terminal of the MOS transistor NM2 is connected to the first end of the resistor R4; the second end of the resistor R4 is connected to the ground terminal; the control terminal and the second connection terminal of the transistor Q3 are connected to the ground terminal; the startup circuit is used to pull down the control terminals of the MOS transistor PM5 and the MOS transistor PM6, so that the negative temperature coefficient current generating circuit enters the working state, and after the negative temperature coefficient current generating circuit enters the working state, the pulling-down action is stopped.

[0012] In one embodiment, the startup circuit includes MOS transistor PM7, MOS transistor NM3, MOS transistor NM4, and MOS transistor NM5; the control terminals of the MOS transistor PM7 and the MOS transistor NM3 are commonly connected to receive the gate control voltage; the first connection terminal of the MOS transistor PM7 is used to receive the power supply voltage, and the second connection terminal of the MOS transistor PM7, the first connection terminal of the MOS transistor NM3, the control terminal of the MOS transistor NM4, and the first connection terminal of the MOS transistor NM5 are commonly connected; the first connection terminal of the MOS transistor NM4 is connected to the second connection terminal of the MOS transistor PM5; the second connection terminals of the MOS transistor NM3, the MOS transistor NM4, and the MOS transistor NM5 are respectively connected to the ground terminal; the control terminal of the MOS transistor NM5 is connected to the control terminal of the MOS transistor NM2.

[0013] In one embodiment, the compensation temperature current generation circuit includes MOS transistor NM6, MOS transistor NM7, MOS transistor PM8, MOS transistor PM9, and MOS transistor PM10. The first connection end and the control end of the MOS transistor NM6, and the control end of the MOS transistor NM7 are commonly connected and are used to receive the first mirror current. The control end of the MOS transistor PM8 is connected to the control end of the MOS transistor PM6. The first connection end of the MOS transistor NM7, the first connection end of the MOS transistor PM8, the first connection end and the control end of the MOS transistor PM9, and the control end of the MOS transistor PM10 are commonly connected. The first connection end of the MOS transistor PM10 is used to output the high-temperature compensation current. The second connection end of the MOS transistor PM8, the second connection end of the MOS transistor PM9, and the second connection end of the MOS transistor PM10 are respectively used to receive the power supply voltage. The second connection end of the MOS transistor NM6 and the second connection end of the MOS transistor NM7 are connected to the ground terminal.

[0014] In one embodiment, the aspect ratio of the MOS transistor PM9 and the MOS transistor PM10 is K1, and the aspect ratio of the MOS transistor PM6 and the MOS transistor PM8 is K2, where K1 and K2 are non-zero constants.

[0015] In one embodiment, the compensation temperature current generation circuit further includes MOS transistor NM8, MOS transistor NM9, MOS transistor NM10, MOS transistor NM11, MOS transistor PM11, MOS transistor PM12, and MOS transistor PM13. The first connection end and the control end of the MOS transistor NM8, and the control end of the MOS transistor NM9 are commonly connected and are used to receive the second mirror current. The first connection end of the MOS transistor NM9, the first connection end and the control end of the MOS transistor NM10, the control end of the MOS transistor NM11, and the first connection end of the MOS transistor PM13 are commonly connected. The control end of the MOS transistor PM13 is connected to the MOS transistor PM6. The second connection end of the MOS transistor PM13, the first connection end of the MOS transistor PM11, and the first connection end of the MOS transistor PM12 are respectively used to receive the power supply voltage. The second connection end of the MOS transistor NM8, the second connection end of the MOS transistor NM9, the second connection end of the MOS transistor NM10, and the first connection end of the MOS transistor NM11 are respectively connected to the ground terminal. The second connection end of the MOS transistor NM11, the second connection end and the control end of the MOS transistor PM11, and the control end of the MOS transistor PM12 are commonly connected. The second connection end of the MOS transistor PM12 is used to output the low-temperature compensation current.

[0016] In one embodiment, the width-to-length ratio of the MOS transistor PM11 and the MOS transistor PM12 is K3, the width-to-length ratio of the MOS transistor NM8 and the MOS transistor NM9 is K4, and the width-to-length ratio of the MOS transistor NM11 and the MOS transistor NM10 is K5; K3, K4, and K5 are all non-zero constants.

[0017] In one embodiment, the low-temperature drift bandgap reference circuit further includes a chopper switch network, and the chopper switch network includes switches clk1, clk2, clk3, and clk4;

[0018] The first ends of the switch clk1 and the switch clk2 are commonly connected and connected to the second connection end of the MOS transistor PM1; the second end of the switch clk1 is connected to the first connection end of the operational amplifier, and the second end of the switch clk2 is connected to the second connection end of the operational amplifier; the first ends of the switch clk3 and the switch clk4 are commonly connected and connected to the second connection end of the MOS transistor PM2; the second end of the switch clk3 is connected to the first connection end of the operational amplifier, and the second end of the switch clk4 is connected to the second connection end of the operational amplifier.

[0019] The above low-temperature drift bandgap reference circuit generates a zero-temperature drift current, a first mirror current, and a second mirror current of the zero-temperature drift current through a zero-temperature drift current generation circuit. On the other hand, a negative temperature coefficient current is generated through a negative temperature coefficient current generation circuit. Then, a high-temperature compensation current is obtained according to the difference between the first mirror current and the negative temperature coefficient current, a low-temperature compensation current is obtained according to the difference between the negative temperature coefficient current and the second mirror current, and a third mirror current of the zero-temperature drift current is obtained based on the mirror unit of the reference output circuit. Finally, reference voltages are generated under the action of the first load unit, the second load unit, and the third load unit respectively. Since the impedance values of the respective load units can directly affect the temperature coefficient and voltage value of the reference voltage, the temperature coefficient and voltage value of the reference voltage can be adjusted by adjusting the impedance values of the respective load units, and finally the low-temperature drift output and voltage value adjustment of the reference voltage are realized. Description of the Drawings

[0020] Figure 1 It is a schematic diagram of the structure of a traditional reference circuit;

[0021] Figure 2 It is a structural diagram of the low-temperature drift bandgap reference circuit according to an embodiment of the present application;

[0022] Figure 3 It is a structural diagram of the low-temperature drift bandgap reference circuit according to another embodiment of the present application;

[0023] Figure 4Structural diagram of a low-temperature drift bandgap reference circuit according to another embodiment of the present application;

[0024] Figure 5 Structural diagram of a low-temperature drift bandgap reference circuit according to an embodiment of the present application;

[0025] Figure 6 Structural diagram of a low-temperature drift bandgap reference circuit according to an embodiment of the present application;

[0026] Figure 7 Structural diagram of a low-temperature drift bandgap reference circuit according to another embodiment of the present application;

[0027] Figure 8 Structural diagram of a low-temperature drift bandgap reference circuit according to another embodiment of the present application;

[0028] Figure 9 Waveform schematic diagrams of zero-temperature drift current, negative temperature coefficient current, high-temperature compensation current, and low-temperature compensation current according to the present application;

[0029] Figure 10 Waveform schematic diagram of the reference voltage after compensation according to the present application. Detailed implementation manners

[0030] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0031] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0032] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly. The described connection can be a direct connection or an indirect connection.

[0033] In addition, in this application, descriptions such as "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0034] An embodiment of the present utility model provides a low-temperature drift bandgap reference circuit, as Figure 2 shown. The reference circuit includes a zero-temperature drift current generation circuit 110, a negative temperature coefficient current generation circuit 120, a compensation temperature current generation circuit 130, and a reference output circuit. The zero-temperature drift current generation circuit 110 is used to generate a zero-temperature drift current and a first mirror current and a second mirror current of the zero-temperature drift current. The negative temperature coefficient current generation circuit 120 is used to generate a negative temperature coefficient current. The compensation temperature current generation circuit 130 is respectively connected to the zero-temperature drift current generation circuit 110 and the negative temperature coefficient current generation circuit 120, and is used to perform a difference operation on the first mirror current and the negative temperature coefficient current to obtain a high-temperature compensation current, and perform a difference operation on the negative temperature coefficient current and the second mirror current to obtain a low-temperature compensation current. The reference output circuit includes a mirror unit 141, a first load unit 142, a second load unit 143, and a third load unit 144. The mirror unit 141 is connected to the zero-temperature drift current generation circuit 110 and is used to mirror the zero-temperature drift current to obtain a third mirror current. The mirror unit 141, the first load unit 142, the second load unit 143, the third load unit 144, and the ground terminal are connected in sequence, and the common connection terminal of the first load unit 142 and the second load unit 143 is used to receive a first compensation current, and the common connection terminal of the second load unit 143 and the third load unit 144 is used to receive a second compensation current, so as to generate a reference voltage at the common connection terminal of the mirror unit 141 and the first load unit 142. Wherein, one of the first compensation current and the second compensation current is a low-temperature compensation current, and the other is a high-temperature compensation current.

[0035] It can be understood that the zero-temperature-drift current generation circuit 110 can generate a zero-temperature-drift current and mirror to generate a first mirror current and a second mirror current of the zero-temperature-drift current. The first mirror current and the second mirror current have the same temperature coefficient as the zero-temperature-drift current, and their current values change little with temperature. The negative temperature coefficient current has the characteristic that its current value decreases as the temperature increases. The first mirror current and the negative temperature coefficient current perform a difference operation, that is, the value of the first mirror current minus the value of the negative temperature coefficient current. The obtained difference current has the characteristic that its current value starts to be greater than 0 after exceeding a certain temperature value and the current value increases as the temperature value increases. According to this difference current, a high-temperature compensation current can be obtained; the value of the high-temperature compensation current can be in a multiple relationship with this difference current.

[0036] The negative temperature coefficient current and the second mirror current perform a difference operation, that is, the value of the negative temperature coefficient current minus the value of the second mirror current. The obtained difference current has the characteristic that its current value starts to be greater than 0 after being lower than a certain temperature value and the current value increases as the temperature value decreases. According to this difference current, a low-temperature compensation current can be obtained; the value of the low-temperature compensation current can be in a multiple relationship with this difference current.

[0037] The third mirror current obtained by the mirror unit 141 in the reference output circuit mirroring the zero-temperature-drift current has the same temperature coefficient as the zero-temperature-drift current, and its current value changes little with temperature; the first load unit 142, the second load unit 143, and the third load unit 144 are used to generate corresponding voltages based on each current, and finally obtain the desired reference voltage. Specifically, let the third mirror current be represented as I 01 , the first compensation current be I 02 , the second compensation current be I 03 , and the impedances of the first load unit 142, the second load unit 143, and the third load unit 144 be Z1, Z2, and Z3 in sequence. Then the voltage difference between position points a and b can be obtained as I 01 *Z1, the voltage difference between position points b and c is (I 01 +I 02 )*Z2, and the voltage difference between position point c and the ground terminal is (I 01 +I 02 +I 03 )*Z3. Thus, the voltage difference between position point a and the ground terminal, that is, the reference voltage VREF, can be expressed as:

[0038] I 01 *Z1+(I 01 +I 02 )*Z2+(I 01 +I 02 +I 03 )*Z3

[0039] That is

[0040] I 01 *(Z1 + Z2 + Z3) + I 02 *(Z2 + Z3) + I 03 *Z3

[0041] where I 01 is less affected by temperature, I 02 and one of I 03 can achieve high - temperature compensation, and the other can achieve low - temperature compensation. By the first load unit 142, the second load unit 143, and the third load unit 144, multiple temperature compensation points can be set. Just matching appropriate load values for the first load unit 142, the second load unit 143, and the third load unit 144 can set the magnitude of the reference voltage and the magnitude of temperature compensation. In this way, the magnitude of the reference voltage can be adjusted, and low - temperature drift of the reference voltage can be achieved through segmented temperature compensation. In some embodiments, each load unit may include at least one resistor.

[0042] The above - mentioned low - temperature - drift bandgap reference circuit generates a zero - temperature - drift current, a first mirror current, and a second mirror current of the zero - temperature - drift current through the zero - temperature - drift current generation circuit 110. On the other hand, it generates a negative - temperature - coefficient current through the negative - temperature - coefficient current generation circuit 120. Then, a high - temperature compensation current is obtained according to the difference between the first mirror current and the negative - temperature - coefficient current, a low - temperature compensation current is obtained according to the difference between the negative - temperature - coefficient current and the second mirror current, and a third mirror current of the zero - temperature - drift current is obtained based on the mirror unit 141 of the reference output circuit. Finally, reference voltages are generated under the action of the first load unit 142, the second load unit 143, and the third load unit 144 respectively. Since the impedance values of each load unit can directly affect the temperature coefficient and voltage value of the reference voltage, the temperature coefficient and voltage value of the reference voltage can be adjusted by adjusting the impedance values of each load unit, and finally, low - temperature - drift output and adjustable voltage value of the reference voltage are achieved.

[0043] In one embodiment, refer to Figure 3As shown in the figure, the zero-temperature-drift current generation circuit 110 includes an operational amplifier AMP, MOS transistors PM1, PM2, transistors Q1, Q2, resistors R1, R2, and R3; the output terminal of the operational amplifier is respectively connected to the control terminals of MOS transistors PM1 and PM2; the first connection terminals of MOS transistors PM1 and PM2 are respectively used to receive the power supply voltage VDD; the second connection terminal of MOS transistor PM1, the first input terminal of the operational amplifier, the first end of resistor R1, and the first end of resistor R2 are commonly connected; the second connection terminal of MOS transistor PM2, the second input terminal of the operational amplifier, the first end of resistor R3, and the first connection terminal of transistor Q2 are commonly connected; the second end of resistor R1 is connected to the first connection terminal of transistor Q1; the second ends of resistor R2, resistor R3, the control terminal and the second connection terminal of transistor Q1, and the control terminal and the second connection terminal of transistor Q2 are commonly connected and connected to the ground terminal.

[0044] Among them, the resistances of resistor R2 and resistor R3 are equal; the size ratio W / L of PM1 and PM2 is 1:1, so the currents flowing through PM1 and PM2 are equal; the output of the operational amplifier can drive MOS transistors PM1 and PM2 to conduct, and at this time transistors Q1 and Q2 also conduct successively. One of the first connection terminal and the second connection terminal of the operational amplifier can be the non-inverting input terminal, and the other is the inverting input terminal; the potentials at the second connection terminals of MOS transistors PM1 and PM2 are respectively biased to voltage Va and voltage Vb, and Va and Vb are equal. Therefore, voltage Vb is equal to the voltage VBE2 of transistor Q2, that is, Vb = VBE2. The voltage of Va is the sum of the voltage drop of resistor R1 and the voltage VBE1 of transistor Q1. So, Va = I1 * R1 + VBE1. Let the ratio of transistors Q1 and Q2 be m:n, then we have:

[0045] I1 = (VBE2 - VBE1) / R1 = △VBE / R1

[0046] Therefore, the zero-temperature-drift current IPTAT can be expressed as:

[0047] IPTAT = I1 + I2 = VT * ln(m / n) / R1 + VBE2 / R2

[0048] Wherein, VBE1 is the voltage between the base and emitter of transistor Q1, VBE2 is the voltage between the base and emitter of transistor Q2, VT is the thermal voltage with a positive temperature coefficient. Therefore, △VBE also has a positive temperature coefficient, and VBE2 is defined with a negative temperature coefficient. The zero-temperature-drift current IPTAT generated by the above circuit, due to the superposition of two factors with positive and negative temperature coefficients, can make the zero-temperature-drift current IPTAT a zero-temperature-drift coefficient current by reasonably setting the ratio of resistors R1 and R2. Preferably, MOS transistors PM1 and PM2 can be PMOS transistors; transistors Q1 and Q2 can be PNP bipolar transistors.

[0049] The above zero-temperature-drift current generation circuit 110 has a simple structure. Since the temperature coefficient can be achieved by adjusting the ratio of resistors R1 and R2, a zero-temperature-drift current that meets the requirements can be obtained by selecting appropriate resistors R1 and R2.

[0050] In one embodiment, referring to Figure 4 As shown, the zero-temperature-drift current generation circuit 110 further includes MOS transistors PM3 and PM4; the control terminals of MOS transistor PM3 and MOS transistor PM4 are respectively connected to the control terminal of MOS transistor PM1; the first connection terminals of MOS transistor PM3 and MOS transistor PM4 are respectively used to receive the power supply voltage VDD; the second connection terminal of MOS transistor PM3 is connected to the compensation temperature current generation circuit 130 for outputting a first mirror current; the second connection terminal of MOS transistor PM4 is connected to the compensation temperature current generation circuit 130 for outputting a second mirror current.

[0051] It can be understood that MOS transistor PM3 and MOS transistor PM1 can form a current mirror pair to mirror the zero-temperature-drift current flowing through MOS transistor PM1 to obtain the first mirror current IPTAT1; similarly, MOS transistor PM4 and MOS transistor PM1 can also form a current mirror pair to mirror and obtain the second mirror current IPTAT2. Preferably, MOS transistors PM3 and PM4 can be PMOS transistors.

[0052] In this way, by setting MOS transistors PM3 and PM4 to form current mirrors with MOS transistor PM1 respectively, the first mirror current and the second mirror current, which are also zero-temperature-drift coefficient currents, can be obtained through the mirror principle, and the circuit structure is simple.

[0053] In one embodiment, as Figure 5As shown, the negative temperature coefficient current generation circuit 120 includes a startup circuit 121, MOS transistor PM5, MOS transistor PM6, MOS transistor NM1, MOS transistor NM2, transistor Q3, and resistor R4; the first connection ends of MOS transistor PM5 and MOS transistor PM6 are respectively used to receive the power supply voltage; the control end and the first connection end of MOS transistor PM5, the control end of MOS transistor PM6, the first connection end of MOS transistor NM1, and the startup circuit 121 are commonly connected; the second connection end of MOS transistor NM1 is connected to the first connection end of transistor Q3; the control end, the control end and the first connection end of MOS transistor NM2, and the first connection end of MOS transistor PM6 are commonly connected; the second connection end of MOS transistor NM2 is connected to the first end of resistor R4; the second end of resistor R4 is connected to the ground terminal; the control end and the second connection end of transistor Q3 are connected to the ground terminal; the startup circuit 121 is used to pull down the control ends of MOS transistor PM5 and MOS transistor PM6 (denoted as VGN in the figure) to enable the negative temperature coefficient current generation circuit to enter the working state, and after the negative temperature coefficient current generation circuit enters the working state, stop the pulling-down action.

[0054] It can be understood that after the startup circuit 121 pulls down the control ends of MOS transistor PM5 and MOS transistor PM6, MOS transistor PM5 and MOS transistor PM6 are turned on, and MOS transistor NM1, MOS transistor NM2, and transistor Q3 are also successively turned on. Then the startup circuit 121 stops the pulling-down action. Based on the above structure, each MOS transistor can still remain turned on and generate current I3 and current I4 on the branches respectively. In some embodiments, both MOS transistor PM5 and MOS transistor PM6 can be PMOS transistors with a width-to-length ratio W / L of 1:1, both MOS transistor NM1 and MOS transistor NM2 can be PMOS transistors with a width-to-length ratio W / L of 1:1, and transistor Q3 can be a PNP triode. Based on the mirror principle, the magnitudes of I3 and I4 are the same. Therefore, the voltage drop of the triode is equal to the voltage drop of resistor R4, that is, VBE3 = I4 * R7. Thus, I4 = VBE3 / R7, where VBE3 is the voltage between the base and the emitter of transistor Q3, which is a negative temperature coefficient voltage. Therefore, the obtained I4 is a negative temperature coefficient current.

[0055] In one embodiment, the startup circuit 121 includes MOS transistor PM7, MOS transistor NM3, MOS transistor NM4, and MOS transistor NM5; the control terminals of MOS transistor PM7 and MOS transistor NM3 are commonly connected for receiving a gate control voltage (denoted as ENL in the figure); the first connection terminal of MOS transistor PM7 is used for receiving a power supply voltage, and the second connection terminal of MOS transistor PM7, the first connection terminal of MOS transistor NM3, the control terminal of MOS transistor NM4, and the first connection terminal of MOS transistor NM5 are commonly connected; the first connection terminal of MOS transistor NM4 is connected to the second connection terminal of MOS transistor PM5; the second connection terminals of MOS transistor NM3, MOS transistor NM4, and MOS transistor NM5 are respectively connected to the ground terminal; the control terminal of MOS transistor NM5 is connected to the control terminal of MOS transistor NM2.

[0056] It can be understood that when starting to work, the gate control voltage drives MOS transistor PM7 to conduct, thereby enabling MOS transistor NM4 to conduct. The control terminals of MOS transistor PM5 and MOS transistor PM6 are pulled down to the ground terminal, so that MOS transistor PM5 and MOS transistor PM6 conduct, and then MOS transistor NM1 and MOS transistor NM2 conduct. The gates of MOS transistor NM1 and MOS transistor NM2 are at a high level, so that MOS transistor NM5 conducts, pulling the gate of MOS transistor NM4 to the ground terminal, causing MOS transistor NM4 to cut off and stopping the pulling-down action.

[0057] Among them, MOS transistor PM7 can be a PMOS transistor; MOS transistors NM3, NM4, and NM5 can be NMOS transistors; the gate control voltage ENL can be a low level.

[0058] In this way, by using the above circuit, only a gate control voltage needs to be given at the start of work to generate a pulling-down action. When the subsequent circuit is turned on by the driving voltage, the voltage generated by the subsequent circuit is used to feedback-control the startup circuit 121 to make the startup circuit 121 stop the pulling-down action. The circuit is simple and can ensure the timeliness of the pulling-down stop, avoiding the influence on the subsequent circuit.

[0059] In one embodiment, as Figure 6As shown, the compensation temperature current generation circuit 130 includes MOS transistor NM6, MOS transistor NM7, MOS transistor PM8, MOS transistor PM9, and MOS transistor PM10; the first connection end and the control end of MOS transistor NM6 and the control end of MOS transistor NM7 are commonly connected and are used to receive a first mirror current (represented by IPTAT1 in the figure); the control end of MOS transistor PM8 is connected to the control end of MOS transistor PM6; the first connection end of MOS transistor NM7, the first connection end of MOS transistor PM8, the first connection end and the control end of MOS transistor PM9, and the control end of MOS transistor PM10 are commonly connected; the second connection ends of MOS transistor PM8, MOS transistor PM9, and MOS transistor PM10 are respectively used to receive a power supply voltage; the second connection end of MOS transistor NM6 and the second connection end of MOS transistor NM7 are connected to the ground terminal.

[0060] It can be understood that, on the one hand, MOS transistor PM8 and MOS transistor PM6 form a pair of current mirrors to copy the negative temperature coefficient current I4, and the copied current is denoted as ICAT1; on the other hand, MOS transistor NM7 and MOS transistor NM6 form a pair of current mirrors to copy the first mirror current IPTAT1. Thus, the current flowing through MOS transistor PM9 can be expressed as IPTAT1 - ICAT1. Since ICAT1 is a negative temperature coefficient, the current flowing through MOS transistor PM9 can achieve high-temperature compensation. Also, MOS transistor PM9 and MOS transistor PM10 form a pair of current mirrors, so this current can be mirror output to obtain the high-temperature compensation current IH. Refer to Figure 6 As shown, the high-temperature compensation current IH can achieve current compensation at the high-temperature end. Among them, to make MOS transistor NM7 copy the first mirror current IPTAT1, the aspect ratio of MOS transistor NM7 to MOS transistor NM6 needs to be 1:1; in some embodiments, the aspect ratio of MOS transistor NM7 to MOS transistor NM6 can also be set according to the compensation point requirements.

[0061] In one embodiment, the aspect ratio of MOS transistor PM9 to MOS transistor PM10 is K1, and the aspect ratio of MOS transistor PM6 to MOS transistor PM8 is K2, where K1 and K2 are non-zero constants.

[0062] It can be understood that the aspect ratio of MOS transistor PM6 to MOS transistor PM8 determines the magnitude of the current ICAT1, and the aspect ratio of MOS transistor PM9 to MOS transistor PM10 determines the magnitude of the current IPTAT1. K1 and K2 can be set by changing the size of the MOS transistors. By setting appropriate K1 and K2, the magnitude of the high-temperature compensation current IH can be further adjusted to achieve the adjustment of the temperature compensation point, so that the high-temperature compensation current can accurately compensate after the temperature is higher than a certain threshold.

[0063] In this case, the high-temperature compensation current IH can be expressed by the following formula:

[0064] IH = K1 * (IPTAT1 - ICAT1)

[0065] In one embodiment, the compensation temperature current generation circuit 130 further includes an NMOS transistor NM8, an NMOS transistor NM9, an NMOS transistor NM10, an NMOS transistor NM11, a PMOS transistor PM11, a PMOS transistor PM12, and a PMOS transistor PM13; the first connection end and the control end of the NMOS transistor NM8 and the control end of the NMOS transistor NM9 are commonly connected and are used to receive a second mirror current (represented by IPTAT2 in the figure); the first connection end of the NMOS transistor NM9, the first connection end and the control end of the NMOS transistor NM10, the control end of the NMOS transistor NM11, and the first connection end of the PMOS transistor PM13 are commonly connected; the control end of the PMOS transistor PM13 is connected to the PMOS transistor PM6, and the second connection end of the PMOS transistor PM13, the first connection end of the PMOS transistor PM11, and the first connection end of the PMOS transistor PM12 are respectively used to receive a power supply voltage; the second connection end of the NMOS transistor NM8, the second connection end of the NMOS transistor NM9, the second connection end of the NMOS transistor NM10, and the first connection end of the NMOS transistor NM11 are respectively connected to a ground terminal; the second connection end of the NMOS transistor NM11, the second connection end and the control end of the PMOS transistor PM11, and the control end of the PMOS transistor PM12 are commonly connected; the second connection end of the PMOS transistor PM12 is used to output a low-temperature compensation current.

[0066] It can be understood that on the one hand, the PMOS transistor PM8 and the PMOS transistor PM6 form a pair of current mirrors to copy the negative temperature coefficient current I4, and the copied current is denoted as ICAT2; on the other hand, the NMOS transistor NM8 and the NMOS transistor NM9 form a pair of current mirrors to copy the first mirror current IPTAT2. Thus, the current flowing through the PMOS transistor PM10 can be expressed as ICAT2 - IPTAT2. Since ICAT2 is a negative temperature coefficient, the current flowing through the PMOS transistor PM10 can achieve low-temperature compensation. Also, the PMOS transistor PM10 and the PMOS transistor PM11 form a pair of current mirrors, so this current can be mirror output to obtain the low-temperature compensation current IL. Referring to Figure 6 as shown, the low-temperature compensation current IL can achieve current compensation at the low-temperature end.

[0067] Among them, the aspect ratio of the NMOS transistor NM8 to the NMOS transistor NM9, the aspect ratio of the PMOS transistor PM13 to the PMOS transistor PM6, and the aspect ratio of the NMOS transistor NM11 to the NMOS transistor NM10 can all be set according to the compensation point requirements.

[0068] In one embodiment, the width-to-length ratio of MOS transistor PM11 and MOS transistor PM12 is K3, the width-to-length ratio of MOS transistor NM8 and MOS transistor NM9 is K4, and the width-to-length ratio of MOS transistor NM11 and MOS transistor NM10 is K5; K3, K4, and K5 are non-zero constants.

[0069] It can be understood that the width-to-length ratio between the two MOS transistors in each current mirror determines the magnitude of current IL. K3, K4, and K5 can be set by changing the dimensions of the MOS transistors. By setting appropriate K3, K4, and K5, the magnitude of the low-temperature compensation current IL can be further adjusted to achieve the adjustment of the temperature compensation point, so that the low-temperature compensation current can accurately compensate after the temperature is lower than a certain threshold. Let the width-to-length ratio of PM12 to PM11 be K3, the width-to-length ratio of MOS transistor NM8 and MOS transistor NM9 be K4, and the width-to-length ratio of MOS transistor NM11 and MOS transistor NM10 be K5, then IL can be expressed by the following formula:

[0070] IL = K4 * K3 * K2 * (ICAT2 - IPTAT2)

[0071] In one embodiment, as Figure 7 shown, the low-temperature drift bandgap reference circuit further includes a chopper switch network 150. The chopper switch network 150 includes switch clk1, switch clk2, switch clk3, and switch clk4; the first ends of switch clk1 and switch clk2 are commonly connected and connected to the second connection end of MOS transistor PM1; the second end of switch clk1 is connected to the first connection end of the operational amplifier, and the second end of switch clk2 is connected to the second connection end of the operational amplifier; the first ends of switch clk3 and switch clk4 are commonly connected and connected to the second connection end of MOS transistor PM2; the second end of switch clk3 is connected to the first connection end of the operational amplifier, and the second end of switch clk4 is connected to the second connection end of the operational amplifier.

[0072] It can be understood that a chopper switch network with the same structure is also provided inside the operational amplifier. By controlling each switch in the chopper switch network 150, one of MOS transistor PM1 and MOS transistor PM2 can be connected to the first input terminal of the operational amplifier, and the other can be connected to the second input terminal of the operational amplifier. Therefore, two connection modes can be formed. Similarly, the chopper switch network inside the operational amplifier also correspondingly adjusts the connection relationship. In this way, the chopper switch network 150 and the chopper switch network in the operational amplifier are used in combination to ensure that the signal output by the operational amplifier remains unchanged. Thus, by controlling the switching between the two connection modes, the influence of the mismatch introduced by the processing process of the operational amplifier on the reference output can be reduced.

[0073] In one embodiment, as Figure 8As shown, the first load unit 142 includes a resistor R5, the second load unit 143 includes a resistor R6, and the third load unit 144 includes a resistor R7; the mirror unit 141 includes a MOS transistor PM0, the control terminal of the MOS transistor PM0 is connected to the control terminal of the MOS transistor PM2, and the first connection terminal of the MOS transistor PM0 is used to receive a power supply voltage; the second connection terminal of the MOS transistor PM0 is connected to the first end of the resistor R5, the second end of the resistor R5 is connected to the first end of the resistor R6 and is used to receive a first compensation current; the second end of the resistor R6 is connected to the first end of the resistor R7 and is used to receive a second compensation current; the second end of the resistor R7 is connected to the ground terminal.

[0074] Among them, both the MOS transistor PM0 and the MOS transistor PM2 can be PMOS transistors, and they form a pair of current mirrors. The aspect ratio of the MOS transistor PM0 and the MOS transistor PM2 can be K, so that the current flowing through the MOS transistor PM0 is K * IPTAT, which is also a zero temperature drift current.

[0075] An embodiment of the present invention also provides a low temperature drift bandgap reference circuit, refer to Figure 8 As shown, the reference circuit includes a zero temperature drift current generation circuit 110, a negative temperature coefficient current generation circuit 120, a compensation temperature current generation circuit 130, a reference output circuit, and a chopper switch network 150; the zero temperature drift current generation circuit 110 includes an operational amplifier, a MOS transistor PM1, a MOS transistor PM2, a transistor Q1, a transistor Q2, a resistor R1, a resistor R2, a resistor R3, a MOS transistor PM3, and a MOS transistor PM4; the negative temperature coefficient current generation circuit 120 includes a MOS transistor PM7, a MOS transistor NM3, a MOS transistor NM4, a MOS transistor NM5, a MOS transistor PM5, a MOS transistor PM6, a MOS transistor NM1, a MOS transistor NM2, a transistor Q3, and a resistor R4; the compensation temperature current generation circuit 130 includes a MOS transistor NM6, a MOS transistor NM7, a MOS transistor PM8, a MOS transistor PM9, a MOS transistor PM10, a MOS transistor NM8, a MOS transistor NM9, a MOS transistor NM10, a MOS transistor NM11, a MOS transistor PM11, a MOS transistor PM12, a MOS transistor PM13; the chopper switch network 150 includes switches clk1, clk2, clk3, and clk4. The connection relationship and working process of each component can be referred to Figure 8 and the above embodiments.

[0076] Among them, the aspect ratio of the MOS transistor PM9 and the MOS transistor PM10 is K1, the aspect ratio of the MOS transistor PM6 and the MOS transistor PM8 is K2, the aspect ratio of the MOS transistor PM11 and the MOS transistor PM12 is K3, the aspect ratio of the MOS transistor NM8 and the MOS transistor NM9 is K4, and the aspect ratio of the MOS transistor NM11 and the MOS transistor NM10 is K5.

[0077] Based on the above structure, the reference voltage VREF generated between the MOS transistor PM0 and R5 can be expressed as:

[0078] VREF = K * IPTAT * (R5 + R6 + R7) + IL * (R6 + R7) + IH * R7

[0079] = K * [VT * ln(m / n) / R1 + VBE2 / R2] * (R5 + R6 + R7) + K4

[0080] * K3 * K2 * (ICAT2 - IPTAT2) * (R5 + R6) + K * (IPTAT1

[0081] - ICAT1) * R6

[0082] It can be seen therefrom that by setting the resistors R1, R2, and R3, the magnitudes of the negative temperature coefficient current and the positive temperature coefficient current can be set. By reasonably setting the ratio of the resistors R1 and R2, the zero-temperature-drift current IPTAT can be made the zero-temperature-drift coefficient current; by setting the sizes of the relevant current mirrors, the temperature compensation points of IL and IH can be set; by setting the sizes of the resistors R5, R6, and R7, the magnitude of the output reference voltage VREF and the temperature compensation magnitude can be set. Thus, based on the above circuit, the temperature coefficient of the output reference voltage can be made small and can be applied to high-precision circuits.

[0083] Based on the above structure, the waveform curves of the zero-temperature-drift current generated by the zero-temperature-drift current generation circuit, the waveform curves of the negative temperature coefficient current generated by the negative temperature coefficient current generation circuit, and the waveform curves of the high-temperature compensation current and the low-temperature compensation current generated by the compensation temperature current generation circuit can be referred to Figure 9 as shown; after high-temperature compensation and low-temperature compensation, the reference voltage that decreases due to temperature can start to be pulled up at the compensation point, refer to Figure 10 as shown.

[0084] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application. The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A low temperature drift bandgap reference circuit, characterized in that: include: A zero temperature drift current generating circuit, used for generating a zero temperature drift current and a first mirror current and a second mirror current of the zero temperature drift current; A negative temperature coefficient current generating circuit, used for generating a negative temperature coefficient current; a compensation temperature current generating circuit, connected to the zero temperature drift current generating circuit and the negative temperature coefficient current generating circuit respectively, for performing a difference operation on the first mirror current and the negative temperature coefficient current to obtain a high temperature compensation current, and performing a difference operation on the negative temperature coefficient current and the second mirror current to obtain a low temperature compensation current; A reference output circuit comprises a mirror unit, a first load unit, a second load unit and a third load unit; the mirror unit is connected to the zero temperature drift current generating circuit and is used to mirror the zero temperature drift current to obtain a third mirror current; the mirror unit, the first load unit, the second load unit, the third load unit and the ground are connected in sequence, and the common connection end of the first load unit and the second load unit is used to receive a first compensation current, and the common connection end of the second load unit and the third load unit is used to receive a second compensation current, so as to generate a reference voltage at the common connection end of the mirror unit and the first load unit; wherein one of the first compensation current and the second compensation current is the low temperature compensation current, and the other is the high temperature compensation current.

2. The low temperature drift bandgap reference circuit according to claim 1, characterized in that: The zero temperature drift current generating circuit comprises an operational amplifier, a MOS transistor PM1, a MOS transistor PM2, a transistor Q1, a transistor Q2, a resistor R1, a resistor R2 and a resistor R3; the output end of the operational amplifier is respectively connected to the control end of the MOS transistor PM1 and the control end of the MOS transistor PM2; the first connection end of the MOS transistor PM1 and the first connection end of the MOS transistor PM2 are respectively used to receive a power supply voltage; the second connection end of the MOS transistor PM1, the first input end of the operational amplifier, the first end of the resistor R1 and the first end of the resistor R2 are commonly connected; the second connection end of the MOS transistor PM2, the second input end of the operational amplifier, the first end of the resistor R3 and the first connection end of the transistor Q2 are commonly connected; the second end of the resistor R1 is connected to the first connection end of the transistor Q1; the second end of the resistor R2, the second end of the resistor R3, the control end and the second connection end of the transistor Q1, the control end and the second connection end of the transistor Q2 are commonly connected and connected to the ground end.

3. The low temperature drift bandgap reference circuit according to claim 2, characterized in that: The zero temperature drift current generating circuit also includes a MOS transistor PM3 and a MOS transistor PM4; the control end of the MOS transistor PM3 and the control end of the MOS transistor PM4 are respectively connected to the control end of the MOS transistor PM1; the first connection end of the MOS transistor PM3 and the first connection end of the MOS transistor PM4 are respectively used to receive the power supply voltage; the second connection end of the MOS transistor PM3 is connected to the compensation temperature current generating circuit for outputting the first mirror current; the second connection end of the MOS transistor PM4 is connected to the compensation temperature current generating circuit for outputting the second mirror current.

4. The low temperature drift bandgap reference circuit according to claim 1, characterized in that: The negative temperature coefficient current generating circuit comprises a startup circuit, a MOS transistor PM5, a MOS transistor PM6, a MOS transistor NM1, a MOS transistor NM2, a transistor Q3 and a resistor R4; the first connection end of the MOS transistor PM5 and the first connection end of the MOS transistor PM6 are respectively used to receive a power supply voltage; the control end and the first connection end of the MOS transistor PM5, the control end of the MOS transistor PM6, the first connection end of the MOS transistor NM1 and the startup circuit are commonly connected; the second connection end of the MOS transistor NM1 is connected to the first connection end of the transistor Q3; the MOS transistor NM1 The control end of the MOS tube NM2, the control end and the first connection end of the MOS tube NM2, and the first connection end of the MOS tube PM6 are connected in common; the second connection end of the MOS tube NM2 is connected to the first end of the resistor R4; the second end of the resistor R4 is connected to the ground end; the control end and the second connection end of the transistor Q3 are connected to the ground end; the start-up circuit is used for pulling down the control end of the MOS tube PM5 and the control end of the MOS tube PM6 to enable the negative temperature coefficient current generating circuit to enter the working state, and stops the pulling-down action after the negative temperature coefficient current generating circuit enters the working state.

5. The low temperature drift bandgap reference circuit according to claim 4, characterized in that: The startup circuit includes a MOS transistor PM7, a MOS transistor NM3, a MOS transistor NM4 and a MOS transistor NM5; the control end of the MOS transistor PM7 and the control end of the MOS transistor NM3 are commonly connected to receive a gate control voltage; the first connection end of the MOS transistor PM7 is used to receive the power supply voltage, and the second connection end of the MOS transistor PM7, the first connection end of the MOS transistor NM3, the control end of the MOS transistor NM4 and the first connection end of the MOS transistor NM5 are commonly connected; the first connection end of the MOS transistor NM4 is connected to the second connection end of the MOS transistor PM5; the second connection end of the MOS transistor NM3, the second connection end of the MOS transistor NM4 and the second connection end of the MOS transistor NM5 are respectively connected to the ground end; the control end of the MOS transistor NM5 is connected to the control end of the MOS transistor NM2.

6. The low temperature drift bandgap reference circuit according to claim 4, characterized in that: The compensation temperature current generating circuit includes a MOS tube NM6, a MOS tube NM7, a MOS tube PM8, a MOS tube PM9, and a MOS tube PM10; the first connection end and the control end of the MOS tube NM6 and the control end of the MOS tube NM7 are commonly connected and used to receive the first mirror current; the control end of the MOS tube PM8 is connected to the control end of the MOS tube PM6; the first connection end of the MOS tube NM7, the first connection end of the MOS tube PM8, the first connection end and the control end of the MOS tube PM9 and the control end of the MOS tube PM10 are commonly connected; the first connection end of the MOS tube PM10 is used to output the high temperature compensation current; the second connection end of the MOS tube PM8, the second connection end of the MOS tube PM9 and the second connection end of the MOS tube PM10 are respectively used to receive the power supply voltage; the second connection end of the MOS tube NM6 and the second connection end of the MOS tube NM7 are connected to the ground end.

7. The low temperature drift bandgap reference circuit according to claim 6, characterized in that: The width-to-length ratio of the MOS transistor PM9 and the MOS transistor PM10 is K1, and the width-to-length ratio of the MOS transistor PM6 and the MOS transistor PM8 is K2. K1 and K2 are constants that are not zero.

8. The low temperature drift bandgap reference circuit according to claim 7, characterized in that: The compensation temperature current generating circuit also includes MOS tube NM8, MOS tube NM9, MOS tube NM10, MOS tube NM11, MOS tube PM11, MOS tube PM12, and MOS tube PM13; the first connection end and control end of the MOS tube NM8 and the control end of the MOS tube NM9 are connected in common and are used to receive the second mirror current; the first connection end of the MOS tube NM9, the first connection end and control end of the MOS tube NM10, the control end of the MOS tube NM11, and the first connection end of the MOS tube PM13 are connected in common; the control end of the MOS tube PM13 is connected to the MOS tube PM6 The second connection end of the MOS tube PM13, the first connection end of the MOS tube PM11, and the first connection end of the MOS tube PM12 are respectively used to receive the power supply voltage; the second connection end of the MOS tube NM8, the second connection end of the MOS tube NM9, the second connection end of the MOS tube NM10, and the first connection end of the MOS tube NM11 are respectively connected to the ground end; the second connection end of the MOS tube NM11, the second connection end of the MOS tube PM11 and the control end, and the control end of the MOS tube PM12 are commonly connected; the second connection end of the MOS tube PM12 is used to output the low-temperature compensation current.

9. The low temperature drift bandgap reference circuit according to claim 8, characterized in that: The width-to-length ratio of the MOS transistor PM11 and the MOS transistor PM12 is K3, the width-to-length ratio of the MOS transistor NM8 and the MOS transistor NM9 is K4, and the width-to-length ratio of the MOS transistor NM11 and the MOS transistor NM10 is K5; K3, K4 and K5 are all constants that are not zero.

10. The low temperature drift bandgap reference circuit according to claim 2, characterized in that: The low temperature drift bandgap reference circuit further includes a chopper switch network, wherein the chopper switch network includes a switch clk1, a switch clk2, a switch clk3 and a switch clk4; The first end of the switch clk1 and the first end of the switch clk2 are connected in common and connected to the second connection end of the MOS transistor PM1; the second end of the switch clk1 is connected to the first connection end of the operational amplifier, and the second end of the switch clk2 is connected to the second connection end of the operational amplifier; the first end of the switch clk3 and the first end of the switch clk4 are connected in common and connected to the second connection end of the MOS transistor PM2; the second end of the switch clk3 is connected to the first connection end of the operational amplifier, and the second end of the switch clk4 is connected to the second connection end of the operational amplifier.

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