Semiconductor packaging structure and plastic packaging device

Abstract

The utility model discloses a semiconductor packaging structure and a plastic packaging device. The semiconductor packaging structure comprises a packaging body and an identification part. The packaging body is used for wrapping the frame and the chip and has a first color; the identification part is located on one surface of the packaging body and has a second color; wherein the frame comprises a first pin, and the identification part is located at the position close to the first pin on the frame, so that the first pin is marked by the identification part. According to the semiconductor packaging structure, the identification part is arranged on the surface of the packaging body, and the position of the first pin is marked through the identification part with the color different from that of the packaging body, so that the identification degree of the position of the first pin is higher, the identification of the first pin on the semiconductor packaging structure by a chip mounter is facilitated, and the chip mounting efficiency is improved.

Description

Technical Field

[0001] This application relates to the technical field of chip packaging, and particularly to a semiconductor packaging structure and a plastic encapsulation device. Background Art

[0002] Chips are manufactured in a packaged form. In engineering applications, it is necessary to find the pin1 point of the package to solder the package to the PCB to achieve the electrical connection between the chip and the PCB. Currently, according to the differences in packaging processes, the identification methods of the pin1 point can be roughly divided into the following two types: First, at the end of the packaging process, a thimble is used to squeeze the packaged chip to demold it, so a groove will be formed on the surface of the plastic encapsulant. Therefore, by setting the position of the chip during the packaging process, this groove is used to identify the first pin. Second, if there is no need to use a thimble to squeeze the chip to demold during the packaging process, the identification of the pin1 point is generally to burn a small hole on the plastic encapsulant through laser as the pin1 identification. However, the identifications formed by the above two methods are not obvious, resulting in low efficiency when connecting the package to the PCB through the mounter during the chip mounting process. Summary of the Utility Model

[0003] To solve the deficiencies of the prior art, the purpose of this application is to provide a semiconductor packaging structure and a plastic encapsulation device that can improve the recognition of the position of the first pin.

[0004] To achieve the above purpose, this application adopts the following technical solutions:

[0005] In the first aspect, this application provides a semiconductor packaging structure, which includes:

[0006] An encapsulation body for covering a frame and a chip, and having a first color;

[0007] An identification part, which is located on one surface of the encapsulation body and has a second color;

[0008] Wherein, the frame includes a first pin, and the identification part is located near the first pin, so that the first pin is marked by the identification part.

[0009] Further, the surface has a groove, and a coating with a second color is arranged in the groove to form the identification part.

[0010] Further, the chip is fixed on the metal base of the frame, and the pads on the chip and the pins on the frame are connected in one-to-one correspondence by wire bonding.

[0011] Further, the packaging form of the semiconductor packaging structure is plastic packaging.

[0012] Further, the packaging types of the semiconductor packaging structure include SOP packaging, SOT packaging, SOIC packaging, QFN packaging, and DFN packaging.

[0013] In a second aspect, the present application further provides a plastic encapsulation device for plastic encapsulating a chip and a frame to form a semiconductor package structure, including:

[0014] A mold having a cavity for placing the chip and the frame, and an opening mold channel communicating with the cavity, the opening mold channel being located near the first pin on the frame;

[0015] A thimble for passing through the opening mold channel during mold opening to eject the semiconductor package structure in the cavity and perform color marking on the semiconductor package structure to mark the position of the first pin.

[0016] Furthermore, the mold further includes a glue injection channel communicating with the cavity, and the encapsulant enters the cavity through the glue injection channel to encapsulate the chip and the frame to form an encapsulation body. Color marking is performed when the thimble presses the encapsulation body. Among them, the encapsulation body has a first color and the marking has a second color.

[0017] Furthermore, one end of the thimble close to the semiconductor package structure has a coloring structure, and the coloring structure oozes out a coating of the second color when the thimble presses the encapsulation body.

[0018] Furthermore, when the thimble presses the encapsulation body, a groove is formed on the surface of the encapsulation body, and the coating is applied in the groove.

[0019] Furthermore, the mold includes an upper mold and a lower mold. The upper mold and the lower mold respectively have inwardly recessed grooves, so that a cavity is formed when the upper mold and the lower mold are fitted together, and the opening mold channel is arranged on the upper mold or the lower mold.

[0020] Compared with the prior art, the semiconductor package structure in the first aspect marks the position of the first pin by providing an identification portion on the surface of the encapsulation body and using an identification portion having a different color from the encapsulation body, making the recognition of the position of the first pin higher, which is beneficial for the pick-and-place machine to identify the first pin on the semiconductor package structure, thereby improving the pick-and-place efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a cross-sectional view of the semiconductor package structure in an embodiment of the present application;

[0022] Figure 2 It is a schematic structural view of the semiconductor package structure in an embodiment of the present application;

[0023] Figure 3 It is a schematic view of the frame and the chip placed in the plastic encapsulation device in an embodiment of the present application;

[0024] Figure 4 It is a schematic view during mold opening in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the specific embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application.

[0026] The reference to "one embodiment" or "some embodiments" etc. described in this specification means that a specific feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of this application. Thus, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprise", "include", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0027] In the description of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or having more advantages than other embodiments. "A plurality of" means two or more. In addition, in order to facilitate a clear description of the technical solutions of the embodiments of this application, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words such as "first" and "second" do not limit the quantity and execution order, and the words such as "first" and "second" do not necessarily mean different.

[0028] As Figure 1 shown, an embodiment of this application provides a semiconductor package structure 100. The semiconductor package structure 100 includes a frame 11, a chip 12, and a package body 13. The chip 12 is fixed on the frame 11. The package body 13 covers the chip 12 and at least part of the frame 11, and the package body 13 has a first color.

[0029] The frame 11 includes a metal substrate 111 covered by the package body 13 and a plurality of pins 112 extending to the outside of the package body 13. The chip 12 is fixed on the metal substrate 11. The pads on the chip 12 are connected to the pins 112 in one-to-one correspondence by wire bonding. Thus, the chip 12 transmits signals to an external circuit through the plurality of pins 112.

[0030] As Figure 2As shown, among a plurality of pins 112, there is a first pin 1121, and the first pin 1121 plays a positioning role when the semiconductor package structure 100 is installed and soldered. The semiconductor package structure 100 further includes an identification portion located on a surface of the package body 13. The identification portion has a second color, and the position of the identification portion is close to the first pin 1121, so that the first pin 1121 is marked by the identification portion.

[0031] It should be noted that the first color is different from the second color. By setting identification portions with different colors on the package body 13 to indicate the position of the first pin 1121, the position recognition of the first pin 1121 can be improved. When the pick-and-place machine performs pick-and-place on the semiconductor package structure 100, its pick-and-place efficiency is improved.

[0032] As Figure 2 shown, in some embodiments, in order to simplify the identification process and improve efficiency, when the ejector pin extrudes the semiconductor package structure to demold it, at the same time, the package body 13 is marked with the second color to form an identification portion. Therefore, the surface of the package body 13 has a groove 131 formed by the extrusion of the ejector pin. The position of the groove 131 is close to the first pin 1121, and after the paint of the second color is applied in the groove 131 and dried, an identification portion is formed, so that the first pin 1121 is marked by the identification portion. It should be noted that the identification portion can be understood as the paint of the second color, or can be understood as the whole formed by the paint of the second color and the groove.

[0033] Optionally, by injecting the encapsulant into the interior of the mold 21, the package body 13 covers the chip 12 and the frame 11 to form the semiconductor package structure 100. The ejector pin 22 passes through the mold opening channel 212 of the mold 21, so that one end of the ejector pin 22 acts on the package body 13, extrudes the surface of the package body 13 and performs color marking. Therefore, while the semiconductor package structure 100 is separated from the mold 21, a groove 131 and the paint of the second color in the groove 131 are formed on the surface of the package body 13, so that the first pin 1121 is marked.

[0034] Through the above settings, the package body 13 has an identification portion with a color different from its surface. By marking the position of the first pin 1121 with the identification portion, the position recognition of the first pin 1121 is improved. When the pick-and-place machine performs pick-and-place on the semiconductor package structure 100, the first pin 1121 is made more prominent, and the pick-and-place efficiency of the pick-and-place machine is improved.

[0035] Exemplarily, the semiconductor package structure 100 provided in the embodiments of the present application is a plastic package. The plastic package indicates that the material used for packaging is plastic, and does not limit the specific size of the package. The size can be a large size or a small size, that is, the types of plastic packages include but are not limited to SOP packages, SOT packages, SOIC packages, DFN packages, and QFN packages.

[0036] The embodiments of the present application provide a plastic encapsulation device 200 as Figure 3 shown. The plastic encapsulation device 200 is used to encapsulate a chip 12 and a frame 11 to form a semiconductor package structure 100. The plastic encapsulation device 200 includes: a mold 21 having a cavity 211 for placing the chip 12 and the frame 11, an opening mold channel 212 communicating with the cavity 211, and a glue injection channel 213 communicating with the cavity 211. The encapsulant enters the cavity 211 through the glue injection channel 213, so that the encapsulation body 13 wraps the chip 12 and the frame 11 to form the semiconductor package structure 100. Among a plurality of pins, there is a first pin 1121, and the opening mold channel 212 is close to the position of the first pin 1121 of the frame 11.

[0037] As Figure 4 shown, the plastic encapsulation device 200 further includes a ejector pin 22, which is used to pass through the opening mold channel 212 during mold opening to eject the semiconductor package structure 100 in the cavity 211 and perform color marking on the semiconductor package structure 100 to mark the position of the first pin 1121.

[0038] In some embodiments, the mold 21 includes an upper mold 214 and a lower mold 215, and the upper mold 214 and the lower mold 215 each have an inwardly recessed 216. When the upper mold 214 is attached to the lower mold 215, the respective grooves 216 of the upper and lower molds are combined to form the cavity 211. Among them, the opening mold channel 212 is provided on the upper mold 214 or the lower mold 215.

[0039] In some embodiments, the ejector pin 22 presses the surface of the encapsulation body 13 and performs color marking on the surface. Since the encapsulation body 13 has a first color, in order to improve the recognition between the encapsulation body 13 and the marking, therefore, the marking has a second color.

[0040] Exemplarily, a coloring structure 23 is provided at one end of the ejector pin 22 close to the semiconductor package structure 100. When the ejector pin 22 presses the encapsulation body 13, the coloring structure 23 oozes out the paint of the second color, and after the paint dries, a mark is formed to mark the position of the first pin 1121.

[0041] In some embodiments, when the ejector pin 22 presses the encapsulation body 13, due to the acting force applied to the encapsulation body 13 by the ejector pin 22, a groove 131 is formed on the surface of the encapsulation body 13, and the coloring structure 23 applies the paint in the groove 131. Through the cooperation of the groove 131 and the marking, the recognition of the first pin 1121 is improved.

[0042] Exemplarily, the coloring structure 23 is configured to exude a coating of a second color when subjected to a reverse force exerted by the encapsulation body 13 thereon, that is, when the ejector pin 22 ejects the semiconductor encapsulation structure 100 from the cavity 211, the marking of the position of the first pin 1121 is completed.

[0043] As Figure 3 shown, in some embodiments, the semiconductor encapsulation structure 100 has a first positioning portion 15, and the first positioning portion 15 is located on the frame 11. The mold 21 has a second positioning portion 217 corresponding to the first positioning portion 15. Through the mutual cooperation of the first positioning portion 15 and the second positioning portion 217, the relative positions of the mold opening channel 212 and the first pin 1121 are calibrated. Thereby ensuring that the frame 11 is placed in the correct position and avoiding deviations in the color marking of the first pin 1121 caused by incorrect placement of the frame 11, and further ensuring the normal operation of the semiconductor encapsulation structure 100 after chip mounting.

[0044] Exemplarily, the first positioning portion 15 is located on the frame 11. The frame 11 has two end faces arranged oppositely, and the first positioning portion 15 is located on at least one end face. When the first positioning portion 15 is located on the upper end face of the frame 11, the second positioning portion 217 is arranged on the side of the upper mold 214 facing the frame 11; when the first positioning portion 15 is located on the lower end face of the frame 11, the second positioning portion 217 is arranged on the side of the lower mold 215 facing the frame 11.

[0045] Wherein, the first positioning portion 15 and the second positioning portion 217 are respectively a convex portion and a concave portion that are mutually engaged. When the upper mold 214 and the lower mold 215 are closed, through the mutual cooperation of the first positioning portion 15 and the second positioning portion 217, the relative positions of the mold opening channel 212 and the first pin 1121 are calibrated. It should be noted that the frame 11 can also be limited in the direction perpendicular to the mold opening direction through the first positioning portion 15 and the second positioning portion 217, improving the yield rate of the semiconductor encapsulation structure 100.

[0046] It should be understood that for those of ordinary skill in the art, improvements or transformations can be made according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of this application.

Claims

1. A semiconductor packaging structure, characterized in that: include: A package body, used for covering the frame and the chip, and having a first color; a marking portion, the marking portion being located on a surface of the package body and having a second color; The frame includes a first pin, and the identification portion is located close to the first pin, so that the first pin is marked by the identification portion.

2. The semiconductor package structure according to claim 1, wherein: The surface has a groove, and paint with a second color is arranged in the groove to form the marking portion.

3. The semiconductor package structure according to claim 1, wherein: The chip is fixed on the metal substrate of the frame, wherein the pads on the chip are connected to the pins on the frame in a one-to-one correspondence through wire bonding.

4. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure is packaged in a plastic package.

5. The semiconductor package structure according to claim 4, characterized in that: The packaging types of the semiconductor packaging structure include SOP packaging, SOT packaging, SOIC packaging, QFN packaging, and DFN packaging.

6. A plastic encapsulation device for encapsulating a chip and a frame to form a semiconductor packaging structure, characterized in that: include: A mold, comprising a cavity for placing the chip and the frame, and a mold opening channel communicating with the cavity, wherein the mold opening channel is close to the position of the first pin on the frame; An ejector pin is used to pass through the mold opening channel when the mold is opened to eject the semiconductor packaging structure in the cavity, and to color-mark the semiconductor packaging structure to mark the position of the first pin.

7. The plastic sealing device according to claim 6, characterized in that: The mold also includes a glue injection channel connected to the cavity, and the plastic packaging material enters the cavity through the glue injection channel to encapsulate the chip and the frame to form a package body. The ejector pin performs color marking when squeezing the package body, wherein the package body has a first color and the mark has a second color.

8. The plastic sealing device according to claim 7, characterized in that: One end of the ejector pin close to the semiconductor package structure has a coloring structure, and when the ejector pin presses the package body, the coloring structure oozes out the paint of the second color.

9. The plastic sealing device according to claim 8, characterized in that: When the ejector pin squeezes the package body, a groove is formed on the surface of the package body, and the coating is applied in the groove.

10. The plastic sealing device according to claim 6, characterized in that: The mold comprises an upper mold and a lower mold, and the upper mold and the lower mold respectively have an inwardly recessed groove body so that the cavity is formed when the upper mold and the lower mold are fitted together, and the mold opening channel is arranged on the upper mold or the lower mold.

Images