Storage circuit of video switcher

Abstract

The utility model discloses a storage circuit of a video switcher, which relates to the technical field of storage circuits, and comprises a PMOS (P-channel Metal Oxide Semiconductor) tube I and an NMOS (N-channel Metal Oxide Semiconductor) tube II, the source electrode of the PMOS tube I is electrically connected with the source electrode of the PMOS tube II, the PMOS tube I is electrically connected with power supply voltage, the grid electrode of the PMOS tube I is electrically connected with the grid electrode of the NMOS tube I, the grid electrode of the PMOS tube I is electrically connected with the drain electrode of the NMOS tube II, and the source electrode of the NMOS tube II is electrically connected with the drain electrode of the NMOS tube II. The grid electrode of the first PMOS tube is electrically connected with the grid electrode of a third NMOS tube. According to the storage circuit of the video switcher, when a write operation is carried out, if a storage point Q is at a high level, a word line WL is pulled to be at a high level, a write bit line WBL is at a low level and charges of the storage point Q are released to be 0 through a sixth NMOS tube and the write bit line WBL during a write low level 0 operation period, so that the write 0 operation is realized; and the connection path of the storage nodes is blocked, the aging influence is reduced, and the reading fault and the semi-selection fault are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of storage circuits, and specifically relates to a storage circuit of a video switcher. Background Art

[0002] A video switcher is a device that selectively outputs multiple video signals to a single display device. It usually consists of multiple input ports and one output port, and switches video signals by selecting different input ports. The storage circuit of a video switcher is a key part of the video switching system, which is responsible for storing and managing the switching states of video signals. The types of memories commonly used in the storage circuit of a video switcher include static random access memory, dynamic random access memory, synchronous dynamic random access memory, etc. The storage circuit can be used to store video frames, transition effects, preview window contents, etc., to support the processing and switching of multiple video signals.

[0003] The storage circuit is an important part of the video switcher and can store the video signal switching state of the video switcher. After long-term use, the read-write ports of the existing storage circuit of the video switcher will age, resulting in frequent read failures and half-select failures, which affect the storage of the video signal switching state of the video switcher. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a storage circuit of a video switcher to solve the problem that the existing storage circuit of the video switcher is prone to aging, resulting in read-write failures as mentioned in the above background art.

[0005] To achieve the above purpose, the utility model provides the following technical solution: A storage circuit of a video switcher, comprising: PMOS transistor one and NMOS transistor two,

[0006] The source electrode of the PMOS transistor one is electrically connected to the source electrode of the PMOS transistor two, and the PMOS transistor one is electrically connected to the power supply voltage. The gate electrode of the PMOS transistor one is electrically connected to the gate electrode of the NMOS transistor one. The gate electrode of the PMOS transistor one is electrically connected to the drain electrode of the NMOS transistor two. The gate electrode of the PMOS transistor one is electrically connected to the gate electrode of the NMOS transistor three. The gate electrode of the PMOS transistor one is electrically connected to the drain electrode of the PMOS transistor two.

[0007] Preferably, the drain electrode of the PMOS transistor one is electrically connected to the gate electrode of the NMOS transistor two, and the drain electrode of the PMOS transistor one is electrically connected to the gate electrode of the PMOS transistor two.

[0008] Preferably, the drain electrode of the PMOS transistor one is electrically connected to the drain electrode of the NMOS transistor one, the drain electrode of the PMOS transistor one is electrically connected to the source electrode of the NMOS transistor six, and the gate electrode of the NMOS transistor six is connected to a word line.

[0009] Preferably, the drain of the NMOS transistor six is connected to a write bit line, the port of the write bit line is electrically connected to a control transistor, the gate of the NMOS transistor five is connected to a word line, and the drain of the NMOS transistor five is electrically connected to the source of the NMOS transistor one.

[0010] Preferably, the drain of the NMOS transistor three is connected to a read bit line, the port of the read bit line is electrically connected to a control transistor, and the drain of the NMOS transistor four is electrically connected to the source of the NMOS transistor three.

[0011] Preferably, the source of the NMOS transistor four is connected to the source of the NMOS transistor two, and the NMOS transistor four is grounded, and the drain of the PMOS transistor one is Q.

[0012] Compared with the prior art, the beneficial effect of the storage circuit of the video switcher is that: the storage circuit is an important part of the video switcher, which can store the video signal switching state of the video switcher. When performing a write operation, if the storage point Q is at a high level, during the write low-level 0 operation, the word line WL is pulled to a high level, the write bit line WBL is at a low level, and the charge of the storage point Q is released to 0 through the NMOS transistor six and the write bit line WBL, thus realizing the write 0 operation. By adding an additional control transistor to the read-write port structure, the path connected to the storage node is blocked, the aging effect is reduced, and the occurrence of read failures and half-select failures is reduced. In this way, the storage circuit of the video switcher can be optimized through the above operations, so that the storage circuit can stably store the video signal switching state of the video switcher. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic circuit diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0015] Please refer to Figure 1 , the present invention provides a technical solution: a storage circuit of a video switcher, including: a PMOS transistor one and an NMOS transistor two,

[0016] The source electrode of the first PMOS transistor is electrically connected to the source electrode of the second PMOS transistor, and the first PMOS transistor is electrically connected to the power supply voltage. The gate electrode of the first PMOS transistor is electrically connected to the gate electrode of the first NMOS transistor. The gate electrode of the first PMOS transistor is electrically connected to the drain electrode of the second NMOS transistor, the gate electrode of the first PMOS transistor is electrically connected to the gate electrode of the third NMOS transistor, and the gate electrode of the first PMOS transistor is electrically connected to the drain electrode of the second PMOS transistor; the drain electrode of the first PMOS transistor is electrically connected to the gate electrode of the second NMOS transistor, and the drain electrode of the first PMOS transistor is electrically connected to the gate electrode of the second PMOS transistor; the drain electrode of the first PMOS transistor is electrically connected to the drain electrode of the first NMOS transistor, the drain electrode of the first PMOS transistor is electrically connected to the source electrode of the sixth NMOS transistor, and the gate electrode of the sixth NMOS transistor is connected to a word line; the drain electrode of the sixth NMOS transistor is connected to a write bit line, and the port of the write bit line is electrically connected to a control transistor. The gate electrode of the fifth NMOS transistor is connected to the word line, and the drain electrode of the fifth NMOS transistor is electrically connected to the source electrode of the first NMOS transistor; the drain electrode of the third NMOS transistor is connected to a read bit line, and the port of the read bit line is electrically connected to a control transistor. The drain electrode of the fourth NMOS transistor is electrically connected to the source electrode of the third NMOS transistor; the source electrode of the fourth NMOS transistor is connected to the source electrode of the second NMOS transistor, and the fourth NMOS transistor is grounded. The drain electrode of the first PMOS transistor is Q.

[0017] During specific implementation, the storage circuit is an important part of the video switcher and can store the video signal switching state of the video switcher. During the write operation, if the storage point Q is at a high level, during the write low-level 0 operation, the word line WL is pulled to a high level, and the write bit line WBL is at a low level. The charge of the storage point Q is released to 0 through the sixth NMOS transistor and the write bit line WBL, thereby realizing the write 0 operation. During the read operation, if the storage point Q is at a low level and the storage point QB is at a high level, then the third NMOS transistor conducts, and the charge on the read bit line RBL discharges through the third NMOS transistor and the fourth NMOS transistor, and the voltage of the read bit line RBL drops. The data 0 is read through the sense amplifier, indicating that the low level 0 is read. In order to prevent read failures and half-selection failures from occurring at the read-write ports of the storage circuit in the video switcher after long-term use, by adding an additional control transistor to the read-write port structure, the path connected to the storage node is blocked, the aging effect is reduced, and the occurrence of read failures and half-selection failures is reduced. Thus, through the above operations, the storage circuit of the video switcher can be optimized to stably store the video signal switching state of the storage circuit for the video switcher.

[0018] In summary: When using the storage circuit of the video switcher, first, the storage circuit receives and stores the switching state and configuration information of the video switcher through the read-write port, which is used to track the operation, performance, or faults of the device. This is the feature of the storage circuit of the video switcher. The content not described in detail in this specification belongs to the prior art well-known to those skilled in the art.

[0019] Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or equivalently replace some of the technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A storage circuit of a video switch, comprising: PMOS tube 1 and NMOS tube 2 are characterized by: The source of the PMOS tube 1 is electrically connected to the source of the PMOS tube 2, and the PMOS tube 1 is electrically connected to the power supply voltage, the gate of the PMOS tube 1 is electrically connected to the gate of the NMOS tube 1, the gate of the PMOS tube 1 is electrically connected to the drain of the NMOS tube 2, the gate of the PMOS tube 1 is electrically connected to the gate of the NMOS tube 3, and the gate of the PMOS tube 1 is electrically connected to the drain of the PMOS tube 2.

2. The storage circuit of a video switcher according to claim 1, characterized in that: The drain of the PMOS tube 1 is electrically connected to the gate of the NMOS tube 2, and the drain of the PMOS tube 1 is electrically connected to the gate of the PMOS tube 2.

3. The storage circuit of a video switcher according to claim 1, characterized in that: The drain of the PMOS tube 1 is electrically connected to the drain of the NMOS tube 1, the drain of the PMOS tube 1 is electrically connected to the source of the NMOS tube 6, and the gate of the NMOS tube 6 is connected to a word line.

4. The storage circuit of a video switcher according to claim 3, characterized in that: The drain of the NMOS tube six is ​​connected to a write bit line, a port of the write bit line is electrically connected to a control transistor, the gate of the NMOS tube five is connected to a word line, and the drain of the NMOS tube five is electrically connected to a source of the NMOS tube one.

5. The storage circuit of a video switcher according to claim 1, characterized in that: The drain of the NMOS tube three is connected to the read bit line, the port of the read bit line is electrically connected to the control transistor, and the drain of the NMOS tube four is electrically connected to the source of the NMOS tube three.

6. The storage circuit of a video switcher according to claim 5, characterized in that: The source of the NMOS tube 4 is connected to the source of the NMOS tube 2, and the NMOS tube 4 is grounded. The drain of the PMOS tube 1 is Q.

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