Modular IO system with high response speed

Abstract

The utility model relates to a modular IO system with a high response speed. The modular IO system comprises a control chip, an output 485 bus, a return 485 bus, a synchronous signal line and a plurality of CPLD sub-modules, the control chip is connected with an upper computer and is also connected with each CPLD sub-module through an output 485 bus, a return 485 bus and a synchronous signal line respectively; each CPLD sub-module is connected with a peripheral control circuit; after receiving a control signal sent by the upper computer, the control chip sends the control signal to each CPLD sub-module by outputting a 485 bus; sending a synchronous signal to each CPLD sub-module through a synchronous signal line; and the CPLD sub-module sends the backhaul data to the control chip through the backhaul 485 bus. According to the modular IO system with the high response speed, through the design, signal delay can be reduced, high-speed data transmission is achieved, and the response capability and the real-time performance of the system are remarkably improved.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and particularly to a modular IO system with high response speed. Background Art

[0002] Although most modular IO systems on the current market provide good flexibility and scalability, in some application environments (such as high-speed motion control, real-time data acquisition, etc.), the existing modular IO systems have a slow response speed and cannot meet the requirements of high-speed real-time control. Utility Model Content

[0003] To at least overcome to some extent the problem that the modular IO system in the related technology has a slow response speed and cannot meet the requirements of high-speed real-time control, this application provides a modular IO system with high response speed.

[0004] The solution of this application is as follows:

[0005] A modular IO system with high response speed, comprising:

[0006] A control chip, an output 485 bus, a feedback 485 bus, a synchronization signal line, and multiple CPLD (Complex Programmable Logic Device) sub-modules;

[0007] The control chip is connected to the upper computer, and is also connected to each CPLD sub-module through the output 485 bus, the feedback 485 bus, and the synchronization signal line respectively;

[0008] Each CPLD sub-module is connected to the peripheral control circuit;

[0009] After receiving the control signal sent by the upper computer, the control chip sends the control signal to each CPLD sub-module through the output 485 bus; and sends a synchronization signal to each CPLD sub-module through the synchronization signal line;

[0010] The CPLD sub-module sends the feedback data to the control chip through the feedback 485 bus.

[0011] Preferably, a terminal resistor board is configured at the terminal of the output 485 bus.

[0012] Preferably, a terminal resistor board is configured at the terminal of the feedback 485 bus.

[0013] Preferably, the system further comprises:

[0014] A static resistor;

[0015] The static resistor is used for electrostatic protection of the system circuit.

[0016] Preferably, a common-mode interference filtering circuit is configured at the interface of each line.

[0017] The technical solution provided by this application may include the following beneficial effects: The modular IO system with high response speed in this application includes: a control chip, an output 485 bus, a feedback 485 bus, a synchronization signal line, and multiple CPLD sub-modules; the control chip is connected to the host computer, and is also connected to each CPLD sub-module through the output 485 bus, the feedback 485 bus, and the synchronization signal line respectively; each CPLD sub-module is connected to the peripheral control circuit; after receiving the control signal sent by the host computer, the control chip sends the control signal to each CPLD sub-module through the output 485 bus; sends a synchronization signal to each CPLD sub-module through the synchronization signal line; the CPLD sub-module sends the feedback data to the control chip through the feedback 485 bus. The modular IO system with high response speed in this application can reduce signal delay and achieve high-speed data transmission through the above design, significantly improving the response ability and real-time performance of the system.

[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0020] Figure 1 It is a schematic circuit structure diagram of a modular IO system with high response speed provided by an embodiment of this application.

[0021] Reference numerals: control chip - 1; output 485 bus - 2; feedback 485 bus - 3; synchronization signal line - 4; CPLD sub-module - 5. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. On the contrary, they are only examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0023] Figure 1 It is a schematic circuit structure diagram of a modular IO system with high response speed provided by an embodiment of this application. Referring to Figure 1 , a modular IO system with high response speed includes:

[0024] A control chip 1, an output 485 bus 2, a feedback 485 bus 3, a synchronization signal line 4, and multiple CPLD sub-modules 5;

[0025] The control chip 1 is connected to the host computer, and is also connected to each CPLD sub-module 5 through the output 485 bus 2, the feedback 485 bus 3, and the synchronization signal line 4 respectively;

[0026] Each CPLD sub-module 5 is connected to the peripheral control circuit;

[0027] After receiving the control signal sent by the host computer, the control chip 1 sends the control signal to each CPLD sub-module 5 through the output 485 bus 2; and sends the synchronization signal to each CPLD sub-module 5 through the synchronization signal line 4;

[0028] The CPLD sub-module 5 sends the feedback data to the control chip 1 through the feedback 485 bus 3.

[0029] In specific practice, the control chip 1 selects the RX72M chip, and the RX72M chip has the following characteristics:

[0030] Supports mainstream industrial network communication protocols. Example software includes EtherCAT, PROFINET RT, Ethernet / IP Modbus TCP, and OPC UA integrated with 2-channel EtherCAT slave controller as industrial Ethernet software;

[0031] A performance with a main frequency of up to 240 MHz and a computing power of 1396 CoreMark, supporting 1MB SRAM;

[0032] Equipped with a double-precision floating-point arithmetic unit and a trigonometric function accelerator specifically for motor control, capable of performing sin, cos, inverse trigonometric functions, and square root functions;

[0033] Has rich PWM control outputs and analog signal units, supporting up to 2-axis motor drive;

[0034] Supports 6-channel Delta-sigma modulator interface, supporting current loop feedback signals;

[0035] Supports multiple packages, easily realizing miniaturized PCB design.

[0036] The CPLD sub-module 5 selects the PGC2KG module as the core processing unit to ensure the signal processing speed.

[0037] Preferably, a terminal resistor board is configured at the terminal of the output 485 bus 2.

[0038] A terminal resistor board is configured at the terminal of the feedback 485 bus 3.

[0039] A terminal resistor board is added at the end of the 485 bus to prevent signal reflection.

[0040] It should be noted that the system also includes:

[0041] A static impedance reactor;

[0042] The static impedance reactor is used for electrostatic protection of the system circuit, enhancing the reliability of the system.

[0043] Preferably, a common-mode interference filtering circuit is configured at the interface of each line.

[0044] Common-mode interference is filtered at the interface, improving the signal quality.

[0045] In this technical solution, the control chip 1RX72M sends instructions to each CPLD sub-module 5 through the output 485 bus 2, and each CPLD sub-module 5 then sends the data back to the control chip 1RX72M through the feedback 485 bus 2.

[0046] To ensure that all CPLD sub-modules 5 execute synchronously, a synchronization signal is used in this circuit to coordinate the actions of each CPLD sub-module 5.

[0047] The high-response-speed modular IO system in this embodiment can reduce signal delay and achieve high-speed data transmission through the above design, significantly improving the response ability and real-time performance of the system.

[0048] It can be understood that the same or similar parts in the above embodiments can be referred to each other, and the content not detailed in some embodiments can be referred to the same or similar content in other embodiments.

[0049] It should be noted that in the description of this application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "a plurality" refers to at least two.

[0050] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0051] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A modular IO system with high response speed, characterized in that: include: Control chip, output 485 bus, return 485 bus, synchronization signal line and multiple CPLD sub-modules; The control chip is connected to the host computer and is also connected to each CPLD submodule via an output 485 bus, a return 485 bus, and a synchronization signal line; Each CPLD submodule is connected to a peripheral control circuit; After receiving the control signal sent by the host computer, the control chip sends the control signal to each CPLD submodule through the output 485 bus; sends the synchronization signal to each CPLD submodule through the synchronization signal line; The CPLD submodule sends the feedback data to the control chip through the feedback 485 bus.

2. The system according to claim 1, characterized in that The terminal of the output 485 bus is configured with a terminal resistor board.

3. The system according to claim 1, characterized in that The terminal of the return 485 bus is configured with a terminal resistor board.

4. The system according to claim 1, characterized in that The system further comprises: Electrostatic resistor; The electrostatic resistor is used to provide electrostatic protection for the system circuit.

5. The system according to claim 1, characterized in that Common-mode interference filtering circuits are configured at the interfaces of each line.

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