In-memory computing circuit, memory and chip

Abstract

The utility model discloses an in-memory computing circuit, a memory and a chip, the in-memory computing circuit comprises: a data storage circuit comprising a plurality of storage sub-circuits distributed in a determinant manner, the data storage circuit having an output end configured to output a target current, the target current is used for representing data information of at least two storage sub-circuits in the data storage circuit; the control circuit is configured to control the at least two storage sub-circuits, the control circuit is connected with the control end of the data storage circuit, and the at least two storage sub-circuits are in the same row, the same column or crossed row and column; and the logical operation circuit is configured to perform logical operation on the storage data in the at least two storage sub-circuits based on the target current, and the input end of the logical operation circuit is connected with the output end of the data storage circuit. According to the utility model, the technical problem of low operation speed of the in-memory calculation circuit is solved.

Description

Technical Field

[0001] The utility model belongs to the technical field of chips, and in particular relates to an in-memory computing circuit, a memory and a chip. Background Art

[0002] As a basic architecture in computer science, the traditional von Neumann architecture stores instructions and data separately. Instructions are used to control the operation of the computer, while data is what is operated and processed. These instructions and data are stored in binary form and read from the memory when needed. With the gradual development of artificial intelligence technology, the amount of data calculations has increased rapidly. Frequently moving data from data storage circuits to external computing circuits will inevitably bring huge energy consumption and delays. Based on this, in-memory computing circuits have been proposed, and are expected to break the "storage wall" defect of the von Neumann architecture. The in-memory computing circuit closely combines the data storage circuit with the logic operation circuit. Data can be directly passed to the logic operation circuit for processing without being moved to the external computing circuit, which improves the computing speed to a certain extent.

[0003] However, with the continuous development of various deep neural networks, convolutional neural networks, as one of the most outstanding deep neural networks, are widely used in image recognition, computer vision, natural language processing and other fields. As the number of layers increases, the complexity of network learning continues to increase, and the amount of data calculations that follow also increases significantly, requiring a more complex network structure and increasing costs. The current in-memory computing circuits are also beginning to be unable to meet the increasingly complex data operations, so the low computing speed of in-memory computing circuits is a technical problem that needs to be solved urgently. Utility Model Content

[0004] The embodiments of the utility model provide an in-memory computing circuit, a memory and a chip, which solve the technical problem of low operation speed of the in-memory computing circuit.

[0005] In a first aspect, an embodiment of the utility model provides an in-memory computing circuit, comprising: a data storage circuit, comprising a plurality of storage sub-circuits distributed in a determinant-column manner, the data storage circuit having an output terminal configured to output a target current, the target current being used to characterize data information of at least two of the storage sub-circuits in the data storage circuit; a control circuit configured to control the at least two storage sub-circuits, the control circuit being connected to the control terminal of the data storage circuit, the at least two storage sub-circuits being in the same row, the same column, or crossing rows and columns; a logic operation circuit configured to perform logic operations on the stored data in the at least two storage sub-circuits based on the target current, the input terminal of the logic operation circuit being connected to the output terminal of the data storage circuit.

[0006] Combined with the first aspect of the present utility model, in some embodiments, the data storage circuit includes: a first data line of the row where the storage sub-circuit is located, and a second data line of the column where the storage sub-circuit is located. The input ends of the logic operation circuit are respectively connected to the first data line and the second data line; the control circuit includes: a first control line of the row where the storage sub-circuit is located, and a second control line and a third control line of the column where the storage sub-circuit is located; the storage sub-circuit includes: a storage unit, the function control end of the storage unit is connected to the third control line; a first MOS transistor, the source end of the first MOS transistor is connected to the data input / output end of the storage unit, the gate end of the first MOS transistor is connected to the second control line, and the drain end of the first MOS transistor is connected to the first data line; a second MOS transistor, the source end of the second MOS transistor is connected to the data input / output end of the storage unit, the gate end of the second MOS transistor is connected to the first control line, and the drain end of the second MOS transistor is connected to the second data line; when the third control line controls the storage unit to be in the data output mode, if the first control line is at a high level, the current of the storage unit is output to the second data line, and if the second control line is at a high level, the current of the storage unit is output to the first data line.

[0007] Combined with the first aspect of the present utility model, in some embodiments, the storage sub-circuit further includes: a third MOS transistor, the source end of the third MOS transistor is connected to the first data line, and the drain end of the third MOS transistor is connected to the second data line; the control circuit further includes: a fourth control line provided for the third MOS transistor, the fourth control line is connected to the gate end of the third MOS transistor; when the fourth control line is at a high level, the first data line and the second data line are connected, and when the fourth control line is at a low level, the first data line and the second data line are disconnected.

[0008] Combined with the first aspect of the present utility model, in some embodiments, the data storage circuit further includes: a third data line of the column where the storage sub-circuit is located; the control circuit further includes: a fifth control line of the row where the storage sub-circuit is located; the storage sub-circuit further includes: a fourth MOS transistor, the source end of the fourth MOS transistor is connected to the data input / output end of the storage unit, the gate end of the fourth MOS transistor is connected to the fifth control line, and the drain end of the fourth MOS transistor is connected to the third data line; when the third control line controls the storage unit to be in the data writing mode, if the fifth control line is at a high level, the data on the third data line is written into the storage unit.

[0009] Combined with the first aspect of the present utility model, in some embodiments, the logic operation circuit includes: an AND gate circuit.

[0010] In connection with the first aspect of the present utility model, in some embodiments, the logic operation circuit includes: an OR gate circuit.

[0011] In connection with the first aspect of the present utility model, in some embodiments, the logic operation circuit includes: an exclusive NOR circuit.

[0012] In connection with the first aspect of the present utility model, in some embodiments, the logic operation circuit includes: an exclusive OR circuit.

[0013] In a second aspect, an embodiment of the present utility model provides a memory, including the in-memory computing circuit according to any one of the first aspect.

[0014] In a third aspect, an embodiment of the present utility model provides a chip, including the memory according to the second aspect.

[0015] One or more technical solutions provided by the embodiments of the present utility model at least achieve the following technical effects or advantages:

[0016] An in-memory computing circuit provided by an embodiment of the present utility model includes: a data storage circuit including a plurality of storage sub-circuits distributed in a determinant manner, the data storage circuit having an output terminal configured to output a target current, the target current being used to represent data information of at least two storage sub-circuits in the data storage circuit; a control circuit configured to control at least two storage sub-circuits, the control circuit being connected to the control terminal of the data storage circuit, and at least two storage sub-circuits being in the same row, the same column, or the intersection of rows and columns; and a logic operation circuit configured to perform a logic operation on the stored data in at least two storage sub-circuits based on the target current, the input terminal of the logic operation circuit being connected to the output terminal of the data storage circuit. Whether at least two storage sub-circuits are at least two storage sub-circuits in the same row, at least two storage sub-circuits in the same column, or at least two storage sub-circuits at the intersection of rows and columns, data extraction and logic operation are completed in the internal circuit of the in-memory computing circuit, thereby avoiding transporting data from the data storage circuit to an external computing circuit in the above three cases, and shortening the time for each calculation. Therefore, the operation speed of the in-memory computing circuit is improved.

[0017] In addition, since there is no need to transport data from the data storage circuit to an external computing circuit, the energy consumption of data transmission is saved, and thus the chip power consumption is reduced. Description of the Drawings

[0018] To more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic diagram of the in-memory computing circuit in the embodiment of the present utility model;

[0020] Figure 2 is Figure 1 a partial schematic diagram of the data storage circuit and the control circuit in. Detailed implementation manners

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present utility model in conjunction with the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, rather than all embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present utility model.

[0022] In the present utility model, descriptions such as "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present utility model.

[0023] Figure 1 It is a schematic diagram of the in-memory computing circuit in the embodiment of the present utility model. Refer to Figure 1 As shown, an in-memory computing circuit provided by an embodiment of the present utility model includes: a data storage circuit 10, including a plurality of storage sub-circuits distributed in a determinant manner. The data storage circuit 10 has an output terminal configured to output a target current, and the target current is used to represent the data information of at least two storage sub-circuits in the data storage circuit 10; a control circuit 20 configured to control at least two storage sub-circuits, the control circuit 20 is connected to the control terminal of the data storage circuit 10, and at least two storage sub-circuits are in the same row, the same column or the intersection of rows and columns; a logic operation circuit 30 configured to perform a logic operation on the stored data in at least two storage sub-circuits based on the target current, and the input terminal of the logic operation circuit 30 is connected to the output terminal of the data storage circuit 10.

[0024] In some embodiments, the data storage circuit 10 includes: a first data line of the row where the storage sub-circuit is located, and a second data line of the column where the storage sub-circuit is located. The input ends of the logic operation circuit 30 are respectively connected to the first data line and the second data line; the control circuit 20 includes: a first control line of the row where the storage sub-circuit is located, and a second control line and a third control line of the column where the storage sub-circuit is located; the storage sub-circuit includes: a storage unit, the function control end of the storage unit is connected to the third control line; a first MOS transistor 110, the source end of the first MOS transistor 110 is connected to the data input / output end of the storage unit, the gate end of the first MOS transistor 110 is connected to the second control line, and the drain end of the first MOS transistor 110 is connected to the first data line; a second MOS transistor 120, the source end of the second MOS transistor 120 is connected to the data input / output end of the storage unit, the gate end of the second MOS transistor 120 is connected to the first control line, and the drain end of the second MOS transistor 120 is connected to the second data line; when the third control line controls the storage unit to be in the data output mode, if the first control line is at a high level, the current of the storage unit is output to the second data line, and if the second control line is at a high level, the current of the storage unit is output to the first data line.

[0025] Reference Figure 2 As shown in Figure 2 is Figure 1 a partial schematic diagram of the data storage circuit and the control circuit in. Assume that the storage sub-circuit is the storage unit MTJ 00 For the corresponding storage sub-circuit, then, the first data line is RLL0, the second data line is CLL0, the first control line is CLBL0, the second control line is RLBL0, and the third control line is BSL0.

[0026] It should be noted that if the first control line CLBL0 is at a high level, then the source and drain ends of all the second MOS transistors 120 in the row where the storage unit MTJ 00 is located are turned on. At this time, the currents of the storage unit MTJ 00 , the storage unit MTJ 01 , the storage unit MTJ 02 are all output to the second data line. Specifically, the current of the storage unit MTJ 00 is output to the second data line CLL0, the current of the storage unit MTJ 01 is output to the second data line CLL1, and the current of the storage unit MTJ 02 is output to the second data line CLL2. If the second control line RLBL0 is at a high level, then the source and drain ends of all the first MOS transistors 110 in the column where the storage unit MTJ 00 is located are turned on. At this time, the currents of the storage unit MTJ 00 , the storage unit MTJ 10, the current of the memory cell MTJ 20 is output to the first data line. Specifically, the current of the memory cell MTJ 00 is output to the first data line RLL0, the current of the memory cell MTJ 10 is output to the first data line RLL1, and the current of the memory cell MTJ 20 is output to the first data line RLL2.

[0027] In addition, it should be noted that if the first control line CLBL0 is at a low level, the sources and drains of all the second MOS transistors 120 in the row where the memory cell MTJ 00 is located are not conducting. At this time, the current of the memory cell MTJ 00 , the memory cell MTJ 01 , the memory cell MTJ 02 cannot be output to the second data line. If the second control line RLBL0 is at a low level, the sources and drains of all the first MOS transistors 110 in the column where the memory cell MTJ 00 is located are not conducting. At this time, the current of the memory cell MTJ 00 , the memory cell MTJ 10 , the memory cell MTJ 20 cannot be output to the first data line.

[0028] It should be noted that under the action of the first MOS transistor 110 and the second MOS transistor 120, at least two of the above memory sub - circuits can be at least two memory sub - circuits in the same row or at least two memory sub - circuits in the same column. For example, when the first control line CLBL0 and the first control line CLBL1 are at a high level, at least two memory sub - circuits are the memory sub - circuits corresponding to the memory cell MTJ 00 and the memory cell MTJ 10 . At this time, at least two memory sub - circuits are at least two memory sub - circuits in the same column. For another example, when the second control line RLBL0 and the second control line RLBL1 are at a high level, at least two memory sub - circuits are the memory sub - circuits corresponding to the memory cell MTJ 00 and the memory cell MTJ 01 . At this time, at least two memory sub - circuits are at least two memory sub - circuits in the same row.

[0029] In some embodiments, the memory sub - circuit further includes: a third MOS transistor, the source of the third MOS transistor is connected to the first data line, and the drain of the third MOS transistor is connected to the second data line; the control circuit 20 further includes: a fourth control line provided for the third MOS transistor, and the fourth control line is connected to the gate of the third MOS transistor; when the fourth control line is at a high level, the first data line and the second data line are connected, and when the fourth control line is at a low level, the first data line and the second data line are disconnected.

[0030] For example, referring to Figure 2 as shown, the third MOS transistor of the memory sub-circuit where the memory cell MTJ 01 is located is the third MOS transistor S01. Assume that the first control line CLBL0, the first control line CLBL1, the first control line CLBL2, the second control line RLBL0, the second control line RLBL1, the second control line RLBL2, and the fourth control line corresponding to the third MOS transistor S01 are all at high level. Then, the current of the memory cell MTJ 00 is output to the first data line RLL0, the current of the memory cell MTJ 01 is output to the first data line RLL0, the current of the memory cell MTJ 02 is output to the first data line RLL0, the current of the memory cell MTJ 01 is output to the second data line CLL1, the current of the memory cell MTJ 11 is output to the second data line CLL1, the current of the memory cell MTJ 21 is output to the second data line CLL1. Also, since the fourth control line corresponding to the third MOS transistor S01 is at high level, the source and drain of the third MOS transistor S01 are conducting, that is, the first data line RLL0 and the second data line CLL1 are connected. At this time, at least two memory sub-circuits are at least two memory sub-circuits that cross rows and columns. Specifically, the at least two memory sub-circuits include the memory sub-circuit corresponding to the memory cell MTJ 00 , the memory sub-circuit corresponding to the memory cell MTJ 01 , the memory sub-circuit corresponding to the memory cell MTJ 02 , the memory sub-circuit corresponding to the memory cell MTJ 11 , and the memory sub-circuit corresponding to the memory cell MTJ 21 .

[0031] For another example, referring to Figure 2 as shown, the third MOS transistor of the memory sub-circuit where the memory cell MTJ 00 is located is the third MOS transistor S00, the third MOS transistor of the memory sub-circuit where the memory cell MTJ 01 is located is the third MOS transistor S01, the third MOS transistor of the memory sub-circuit where the memory cell MTJ 02 is located is the third MOS transistor S02. Assume that the first control line CLBL0, the first control line CLBL1, the first control line CLBL2, the fourth control line corresponding to the third MOS transistor S00, the fourth control line corresponding to the third MOS transistor S01, and the fourth control line corresponding to the third MOS transistor S02 are all at high level. Then, the current of the memory cell MTJ 00 is output to the second data line CLL0, the current of the memory cell MTJ 10The current is output to the second data line CLL0, and the memory cell MTJ 20 The current is output to the second data line CLL0. The memory cell MTJ 01 The current is output to the second data line CLL1, and the memory cell MTJ 11 The current is output to the second data line CLL1, and the memory cell MTJ 21 The current is output to the second data line CLL1. The memory cell MTJ 02 The current is output to the second data line CLL2, and the memory cell MTJ 12 The current is output to the second data line CLL2, and the memory cell MTJ 22 The current is output to the second data line CLL2. Since the fourth control line corresponding to the third MOS transistor S00 is at a high level, the source and drain of the third MOS transistor S00 are conducting, that is, the first data line RLL0 and the second data line CLL0 are connected. Since the fourth control line corresponding to the third MOS transistor S01 is at a high level, the source and drain of the third MOS transistor S01 are conducting, that is, the first data line RLL0 and the second data line CLL1 are connected. Since the fourth control line corresponding to the third MOS transistor S02 is at a high level, the source and drain of the third MOS transistor S02 are conducting, that is, the first data line RLL0 and the second data line CLL2 are connected. At this time, the target current can be detected on the first data line RLL0. At least two memory sub-circuits are at least two memory sub-circuits that intersect in rows and columns. Specifically, at least two memory sub-circuits include the memory cell MTJ 00 The corresponding memory sub-circuit, the memory cell MTJ 10 The corresponding memory sub-circuit, the memory cell MTJ 20 The corresponding memory sub-circuit, the memory cell MTJ 01 The corresponding memory sub-circuit, the memory cell MTJ 11 The corresponding memory sub-circuit, the memory cell MTJ 21 The corresponding memory sub-circuit, the memory cell MTJ 02 The corresponding memory sub-circuit, the memory cell MTJ 12 The corresponding memory sub-circuit and the memory cell MTJ 21 The corresponding memory sub-circuit.

[0032] In some embodiments, the data storage circuit 10 may further include: a third data line of the column where the storage sub-circuit is located; the control circuit 20 may further include: a fifth control line of the row where the storage sub-circuit is located; the storage sub-circuit may further include: a fourth MOS transistor 130, the source terminal of the fourth MOS transistor 130 is connected to the data input / output terminal of the storage unit, the gate terminal of the fourth MOS transistor 130 is connected to the fifth control line, and the drain terminal of the fourth MOS transistor 130 is connected to the third data line; when the third control line controls the storage unit to be in the data writing mode, if the fifth control line is at a high level, the data on the third data line is written into the storage unit.

[0033] Reference Figure 2 As shown, assuming that the storage sub-circuit is the storage unit MTJ 00 The corresponding storage sub-circuit, then, the third data line is the third data line MBL0, and the fifth control line is the fifth control line WL0.

[0034] It should be noted that due to the setting of the fourth MOS transistor 130 and the fifth control line, the in-memory computing circuit provided by the embodiments of the present invention not only has a computing function, but also can perform storage, enriching the circuit function. In the case where the circuit has multiple functions, the number of electronic components is reduced, achieving the beneficial effect of simplifying the circuit.

[0035] In some embodiments, the logic operation circuit 30 may include: an AND gate circuit.

[0036] For example, assuming that the number of at least two storage sub-circuits is n, if the data stored in the storage unit is 1, the deviation between the current intensity of the storage unit and a is less than the first deviation threshold, and if the data stored in the storage unit is 0, the deviation between the current intensity of the storage unit and b is less than the second deviation threshold, where a is greater than b and n is an integer greater than 1. Then, if the deviation between the current intensity of the target current and n×a is less than the third deviation threshold, the logic operation circuit 30 outputs a current for representing that the logic operation result is 1; if the deviation between the current intensity of the target current and n×a is equal to or greater than the third deviation threshold, the logic operation circuit 30 outputs a current for representing that the logic operation result is 0.

[0037] It should be noted that the deviation between the current intensity of the storage unit and a being less than the first deviation threshold indicates that the current intensity of the storage unit is close to a. The deviation between the current intensity of the storage unit and b being less than the second deviation threshold indicates that the current intensity of the storage unit is close to b. The deviation between the current intensity of the target current and n×a being less than the third deviation threshold indicates that the current intensity of the storage unit in each storage sub-circuit among at least two storage sub-circuits is close to a.

[0038] In some embodiments, the logic operation circuit 30 may include: an OR gate circuit.

[0039] For example, assume that the number of at least two memory sub - circuits is n. If the data stored in the memory cell is 1, the deviation of the current intensity of the memory cell from a is less than the first deviation threshold. If the data stored in the memory cell is 0, the deviation of the current intensity of the memory cell from b is less than the second deviation threshold, where a > b and n is an integer greater than 1. If the deviation of the current intensity of the target current from n×b is greater than the third deviation threshold, the logic operation circuit 30 outputs a current for representing that the logic operation result is 1. If the deviation of the current intensity of the target current from n×b is less than or equal to the third deviation threshold, the logic operation circuit 30 outputs a current for representing that the logic operation result is 0.

[0040] It should be noted that the deviation of the current intensity of the target current from n×b being less than or equal to the third deviation threshold indicates that the current intensity of the memory cell of each memory sub - circuit among at least two memory sub - circuits is close to b.

[0041] In some embodiments, the logic operation circuit 30 may include: an exclusive - NOR circuit.

[0042] For example, assume that the number of at least two memory sub - circuits is n. If the data stored in the memory cell is 1, the deviation of the current intensity of the memory cell from a is less than the first deviation threshold. If the data stored in the memory cell is 0, the deviation of the current intensity of the memory cell from b is less than the second deviation threshold, where a > b and n is an integer greater than 1. If the deviation of the current intensity of the target current from n×a is less than the third deviation threshold, or the deviation of the current intensity of the target current from n×b is less than the fourth deviation threshold, the logic operation circuit 30 outputs a current for representing that the logic operation result is 1. Otherwise, the logic operation circuit 30 outputs a current for representing that the logic operation result is 0.

[0043] It should be noted that the deviation of the current intensity of the target current from n×a being less than the third deviation threshold indicates that the current intensity of the memory cell of each memory sub - circuit among at least two memory sub - circuits is close to a. The deviation of the current intensity of the target current from n×b being less than the fourth deviation threshold indicates that the current intensity of the memory cell of each memory sub - circuit among at least two memory sub - circuits is close to b.

[0044] In some embodiments, the logic operation circuit 30 may include: an exclusive - OR circuit.

[0045] For example, assume that the number of at least two storage sub-circuits is n. If the data stored in the storage unit is 1, the deviation of the current intensity of the storage unit from a is less than the first deviation threshold. If the data stored in the storage unit is 0, the deviation of the current intensity of the storage unit from b is less than the second deviation threshold, where a is greater than b and n is an integer greater than 1. If the deviation of the current intensity of the target current from n×a is less than the third deviation threshold, or the deviation of the current intensity of the target current from n×b is less than the fourth deviation threshold, the logic operation circuit 30 outputs a current for representing that the logic operation result is 0; otherwise, the logic operation circuit 30 outputs a current for representing that the logic operation result is 1.

[0046] It should be noted that the logic operation circuit 30 can be an OR gate circuit, an AND gate circuit, an exclusive OR circuit or an exclusive NOR circuit, which enriches the calculation function of the in-memory computing circuit, avoids the in-memory computing circuit only having a storage function, and improves the data processing efficiency.

[0047] Reference Figure 2 As shown, the BSL group lines, MBL group lines and WL group lines are data lines and control lines in the memory mode. In the memory mode, when WL is at a high level, it turns on the access transistors in each column and enables data to be read from the MTJ through the memory bit line (MBL) or written into the MTJ.

[0048] It should be noted that in the traditional MTJ computing structure, it is often only possible to perform horizontal unit calculations. If multiple rows need to be calculated together, it is necessary to cross MOS transistors, which is not only inflexible but also the additional MOS transistors have a single function. At the same time, if the number of crossed rows is too large, the long wiring may cause data transmission interference problems. Therefore, in the embodiments of the present invention, the original circuit is improved to make the original circuit more flexible and adaptable to more complex algorithms and requirements, achieving the beneficial effect of avoiding data transmission interference. By increasing the connection control between the longitudinal data path and the intersection points, the embodiments of the present invention not only realize the horizontal and vertical unit calculation functions of data, but also realize the data interaction function of multiple rows and columns, greatly improving the flexibility of the operation circuit and simplifying the design requirements of external driving and algorithms.

[0049] An in-memory computing circuit provided by an embodiment of the present utility model includes: a data storage circuit including a plurality of storage sub-circuits distributed in a determinant manner, the data storage circuit having an output terminal configured to output a target current, the target current being used to represent data information of at least two storage sub-circuits in the data storage circuit; a control circuit configured to control at least two storage sub-circuits, the control circuit being connected to a control terminal of the data storage circuit, and the at least two storage sub-circuits being in the same row, the same column, or the intersection of rows and columns; and a logic operation circuit configured to perform a logic operation on stored data in at least two storage sub-circuits based on the target current, an input terminal of the logic operation circuit being connected to the output terminal of the data storage circuit. Whether the at least two storage sub-circuits are at least two storage sub-circuits in the same row, at least two storage sub-circuits in the same column, or at least two storage sub-circuits at the intersection of rows and columns, data extraction and logical operations are completed within the internal circuit of the in-memory computing circuit, thus avoiding transporting data from the data storage circuit to an external computing circuit in the above three cases, shortening the time required for each calculation. Therefore, the operation speed of the in-memory computing circuit is improved. In addition, since there is no need to transport data from the data storage circuit to an external computing circuit, the energy consumption of data transmission is saved, and thus the chip power consumption is reduced.

[0050] Based on the same inventive concept, an embodiment of the present utility model provides a memory including the in-memory computing circuit in any of the above embodiments.

[0051] It should be understood that more implementation details of the memory in the embodiments of the present utility model are referred to the in-memory computing circuit described above. For the sake of simplicity of the specification, they are not described herein again.

[0052] Based on the same inventive concept, an embodiment of the present utility model provides a chip including the above memory.

[0053] It should be understood that more implementation details of the chip in the embodiments of the present utility model are referred to the in-memory computing circuit described above. For the sake of simplicity of the specification, they are not described herein again.

[0054] The above are only embodiments of the present utility model and are not used to limit the present utility model. For those skilled in the art, the present utility model may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the scope of the claims of the present utility model.

Claims

1. An in-memory computing circuit, characterized in that: include: A data storage circuit, comprising a plurality of storage sub-circuits arranged in a determinant-column pattern, wherein the data storage circuit has an output terminal configured to output a target current, wherein the target current is used to represent data information of at least two of the storage sub-circuits in the data storage circuit; A control circuit configured to control the at least two storage sub-circuits, the control circuit being connected to a control terminal of the data storage circuit, the at least two storage sub-circuits being in the same row, the same column, or crossing rows and columns; A logic operation circuit is configured to perform a logic operation on the storage data in the at least two storage sub-circuits based on the target current, wherein an input terminal of the logic operation circuit is connected to an output terminal of the data storage circuit.

2. The in-memory computing circuit according to claim 1, characterized in that: The data storage circuit comprises: a first data line in the row where the storage sub-circuit is located, and a second data line in the column where the storage sub-circuit is located, and the input end of the logic operation circuit is connected to the first data line and the second data line respectively; The control circuit includes: a first control line in the row where the storage sub-circuit is located, and a second control line and a third control line in the column where the storage sub-circuit is located; The storage sub-circuit comprises: A storage unit, wherein a function control terminal of the storage unit is connected to the third control line; a first MOS transistor, wherein a source end of the first MOS transistor is connected to a data input / output end of the storage unit, a gate end of the first MOS transistor is connected to the second control line, and a drain end of the first MOS transistor is connected to the first data line; a second MOS transistor, wherein a source end of the second MOS transistor is connected to a data input / output end of the storage unit, a gate end of the second MOS transistor is connected to the first control line, and a drain end of the second MOS transistor is connected to the second data line; When the third control line controls the storage unit to be in data output mode, if the first control line is at a high level, the current of the storage unit is output to the second data line; if the second control line is at a high level, the current of the storage unit is output to the first data line.

3. The in-memory computing circuit according to claim 2, characterized in that: The storage sub-circuit further includes: a third MOS transistor, a source end of the third MOS transistor being connected to the first data line, and a drain end of the third MOS transistor being connected to the second data line; The control circuit further includes: a fourth control line provided for the third MOS tube, the fourth control line being connected to the gate terminal of the third MOS tube; When the fourth control line is at a high level, the first data line and the second data line are connected, and when the fourth control line is at a low level, the first data line and the second data line are disconnected.

4. The in-memory computing circuit according to claim 3, characterized in that: The data storage circuit further includes: a third data line in the column where the storage sub-circuit is located; The control circuit further includes: a fifth control line of the row where the storage sub-circuit is located; The storage sub-circuit further includes: a fourth MOS transistor, wherein a source end of the fourth MOS transistor is connected to the data input and output end of the storage unit, a gate end of the fourth MOS transistor is connected to the fifth control line, and a drain end of the fourth MOS transistor is connected to the third data line; When the third control line controls the storage unit to be in a data writing mode, if the fifth control line is at a high level, the data of the third data line is written into the storage unit.

5. The in-memory computing circuit according to any one of claims 1 to 4, characterized in that: The logic operation circuit includes: an AND gate circuit.

6. The in-memory computing circuit according to any one of claims 1 to 4, characterized in that: The logic operation circuit includes: an OR gate circuit.

7. The in-memory computing circuit according to any one of claims 1 to 4, characterized in that: The logic operation circuit includes: an XOR circuit.

8. The in-memory computing circuit according to any one of claims 1 to 4, characterized in that: The logic operation circuit includes: an XOR circuit.

9. A memory, characterized in that: The invention comprises the in-memory computing circuit as claimed in any one of claims 1 to 8.

10. A chip, characterized in that: A memory comprising the memory as claimed in claim 9.

Images