High-efficiency image acquisition equipment

Abstract

The utility model provides high-efficiency image acquisition equipment, which comprises a camera, an FPGA (Field Programmable Gate Array), a DDR3 (Double Data Rate 3) and a CPU (Central Processing Unit), the data output end of the camera is connected with the data input end of the FPGA through a Camera Link interface; the data output end of the camera is connected with the data input end of the CPU through a USB interface and a network interface. And the data transmission end of the FPGA is respectively connected with the data transmission end of the CPU and the data transmission end of the DDR3. Due to the adoption of the technical scheme, the camera is connected with the FPGA through the Camera Link interface, so that the problems that a general processor is low in efficiency and a special image processor is poor in flexibility are solved, more efficient and more flexible image access and processing are realized, the high requirements of modern image processing on real-time performance, accuracy and flexibility are met, and the image processing efficiency is improved. And the overall performance and effect of image processing are improved.

Description

Technical Field

[0001] The utility model relates to the field of image acquisition, in particular to an image acquisition device with high efficiency. Background Art

[0002] The existing image access technology mainly relies on general-purpose processors or dedicated image processors. When processing large-scale image data, the general-purpose processor has the problem of low efficiency and is difficult to meet the high requirements of real-time performance, which may lead to slow image processing speed and affect the performance of the entire system and the user experience. Although the dedicated image processor shows good performance in some specific aspects, it has poor flexibility and cannot be flexibly adjusted and optimized according to specific application requirements, which to a certain extent limits its scope of application. Summary of the Utility Model

[0003] The utility model aims to at least solve the technical problems existing in the prior art, and particularly innovatively provides an image acquisition device with high efficiency.

[0004] To achieve the above object of the utility model, the utility model provides an image acquisition device with high efficiency, including a camera, an FPGA, a DDR3 and a CPU; the data output end of the camera is connected to the data input end of the FPGA through a Camera Link interface; the data output end of the camera is connected to the data input end of the CPU through a USB interface and a network interface; the data transmission end of the FPGA is respectively connected to the data transmission end of the CPU and the data transmission end of the DDR3.

[0005] Further, the Camera Link interface circuit has an LVDS buffer, and the Camera Link interface circuit includes:

[0006] The differential input positive terminal IN+ and the differential input negative terminal IN- of the LVDS buffer are connected to the differential signal output terminal of the connector J1;

[0007] The configuration terminal EQ0 of the LVDS buffer is connected to the first end of the first resistor and the first end of the second resistor, the second end of the first resistor and the first end of the third resistor are connected to the power supply VCC3.3V; the second end of the third resistor and the first end of the fourth resistor are connected to the configuration terminal EQ1 of the LVDS buffer; the second end of the fourth resistor and the second end of the second resistor are connected to the power ground; designing this connection at the configuration terminal of the LVDS buffer plays important roles in impedance matching, maintaining signal integrity, reducing power consumption, improving efficiency and enhancing anti-interference in the LVDS circuit.

[0008] The differential output positive terminal OUT+ and the differential output negative terminal OUT- of the LVDS buffer are connected to the data transmission end of the FPGA;

[0009] The power supply terminal of the LVDS buffer, the first terminal of the first capacitor, and the first terminal of the second capacitor are connected to the power supply VCC3.3V; the ground terminal of the LVDS buffer, the second terminal of the first capacitor, and the second terminal of the second capacitor are connected to the power supply ground.

[0010] The LVDS buffer is mainly used for the conditioning and transmission of high-speed signals. It can optimize the input high-speed signals, such as enhancing the signal strength, improving the signal edge slope, etc., to ensure the integrity and reliability of the signal during transmission.

[0011] During data transmission, the signal may be distorted due to various reasons (such as line loss, electromagnetic interference, etc.). The LVDS buffer can reshape the received signal to restore it to the original signal form, thus ensuring the accuracy of the data. In addition, the LVDS technology can transmit data at a high speed to meet the requirements of high-speed data transmission applications.

[0012] The model of the LVDS buffer is DS25BR110TSD, and the signal of the connector J1 is CAMERALINK CJ-SDR.

[0013] Furthermore, there are multiple LVDS buffers.

[0014] Furthermore, the data input terminal of the camera is connected to the data output terminal of the CPU.

[0015] Furthermore, the data transmission terminal of the camera is connected to the data transmission terminal of the CPU through a driver chip, including:

[0016] The data transmission terminal D of the driver chip is connected to the data input terminal of the CPU, the data enable terminal DE of the driver chip is connected to the first terminal of the resistor R78, and the second terminal of the resistor R78 is connected to the power supply VCC3.3V;

[0017] The row clock terminal R of the driver chip is connected to the data output terminal of the CPU, and the row enable negative logic terminal RE_N of the driver chip is connected to the power supply ground;

[0018] The output data terminal Y, data transmission indication terminal Z, address terminal A, and output data terminal B of the driver chip are all connected to the connector J1. The connector J1 is connected to the camera. The connector J1 is the connection point between the camera and the LVDS buffer;

[0019] The power supply terminal VCC1 of the driver chip, the power supply terminal VCC2 of the driver chip, the first terminal of the capacitor C14, and the first terminal of the capacitor C15 are connected to the power supply VCC3.3V; the second terminal of the capacitor C14 and the second terminal of the capacitor C15 are connected to the power supply ground;

[0020] The ground terminal GND1 of the drive chip and the ground terminal GND2 of the drive chip are connected to the power ground.

[0021] The camera is connected to the CPU through the connector J1, the LVDS buffer, and the drive chip, forming a complete data transmission and control link. This connection method allows the image data captured by the camera to be transmitted to the FPGA for preliminary processing, then further processed or converted by the drive chip, and finally sent to the CPU for final processing or analysis. At the same time, the CPU can also send control signals to the camera through the drive chip to adjust its settings or configurations.

[0022] The model of the drive chip is SN65LVDS180PW.

[0023] Furthermore, the data output terminal of the camera is connected to the data input terminal of the CPU through the USB interface, including:

[0024] The positive differential signal terminal USB2_DP of the primary side of the common-mode transformer and the negative differential signal terminal USB2_DM of the primary side of the common-mode transformer are respectively connected to the differential signal input terminal and the differential signal output terminal of the CPU; the positive differential signal terminal DUSB2_L_D+ of the secondary side of the common-mode transformer and the negative differential signal terminal DUSB2_L_D- of the secondary side of the common-mode transformer are respectively connected to the data terminal D+ of the USB connector and the data terminal D- of the USB connector;

[0025] The data output terminal of the ESD anti-static protection device is connected to the data input terminal of the USB connector, and the data input terminal of the ESD anti-static protection device is connected to the data output terminal of the USB connector;

[0026] The power supply terminal VBUS of the USB connector is connected to the first end of the bead and the first end of the third capacitor, and the second end of the third capacitor is connected to the power ground; the second end of the bead is connected to the power supply USB1_P1_PWR;

[0027] The data terminal D- of the USB connector is connected to the anode of the first TVS diode, and the data terminal D+ of the USB connector is connected to the anode of the second TVS diode; the cathodes of the first TVS diode and the second TVS diode are connected to the power ground;

[0028] The connector type identification terminal ID of the USB connector is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the power ground;

[0029] The negative end SSTX- of the USB 3.0 data transmission, the positive end SSTX+ of the USB 3.0 data transmission, the negative end SSRX- of the USB 3.0 data reception, and the positive end SSRX+ of the USB 3.0 data reception of the USB connector are all connected to the ESD anti-static protection device;

[0030] The ground terminal GND_DRAIN of the USB connector is connected to the power ground.

[0031] The FPGA is responsible for collecting and preliminarily processing images, and then transmitting the data to the CPU through the USB interface. To ensure that the data transmission process is not affected by electromagnetic interference, a common-mode transformer is added before the USB connector for filtering. The main advantage of using a common-mode transformer for filtering is its excellent high-frequency noise suppression ability, which is crucial for maintaining the signal integrity of high-speed data transmission. The common-mode transformer effectively isolates the noise between the FPGA and the CPU through electrical isolation, protecting the USB interface from the noise and transients on the power line. In addition, it helps to meet the strict electromagnetic compatibility (EMC) requirements, improve the reliability of data transmission, and reduce errors and packet loss.

[0032] Furthermore, it includes several USB circuit parts.

[0033] Furthermore, the camera connected to the FPGA through the Camera Link interface is a high-definition camera.

[0034] In summary, due to the adoption of the above technical solution, the present utility model uses the Camera Link interface to connect the camera to the FPGA, thereby overcoming the problems of low efficiency of general-purpose processors and poor flexibility of dedicated image processors, realizing more efficient and flexible image access and processing, meeting the high requirements of modern image processing for real-time, accuracy, and flexibility, and improving the overall performance and effect of image processing.

[0035] The additional aspects and advantages of the present utility model will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present utility model will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, wherein:

[0037] Figure 1 is a schematic structural diagram of the present utility model.

[0038] Figure 2 is a schematic connection diagram of the CPU and the FPGA of the present utility model.

[0039] Figure 3 It is a schematic diagram of the connection of the cameralink circuit of the present utility model.

[0040] Figure 4 It is a schematic diagram of the connection of the USB interface of the present utility model. Specific embodiments

[0041] The embodiments of the present utility model will be described in detail below. The examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present utility model and should not be construed as a limitation of the present utility model.

[0042] The present application proposes a high-efficiency image acquisition device such as Figure 1 shown, including a camera, an FPGA chip, a DDR3, and a CPU chip.

[0043] (1) The camera is used to collect image information. Currently, common cameras with USB interfaces, HDMI interfaces, Ethernet interfaces, cameralink interfaces, etc. on the market can all achieve image access through this device.

[0044] (2) The FPGA chip is used to receive and process data from the camera. At the same time, the data is parsed into frame signals, line signals, and data signals, and further parsed into image information in RGB format and sent to the DDR3.

[0045] (3) The DDR3 is used to cache image information. After storing a complete image, it is sent to the CPU through the PCIE bus. This is done to save most of the resources of the FPGA.

[0046] (4) The CPU judges the correctness of the image format sent by the FPGA, controls when the FPGA sends the image, and stores the image in the solid state.

[0047] The connection between the CPU and the FPGA is as Figure 2 shown. The chip of the CPU is LS1046, and the chip of the FPGA is XC7Z045. The CPU can also be connected to the camera through the network port and the USB interface; the high-definition camera is connected to the FPGA through the Camera Link interface. Because the FPGA is particularly suitable for processing high-speed and multi-channel signal data transmission, compared with the CPU, it has obvious advantages in parallel processing and low latency. Although the CPU can also connect to the camera through the USB or Ethernet interface, when a large amount of high-speed image data needs to be processed, the solution of the FPGA cooperating with the Camera Link interface can often provide a faster data transmission speed, so it becomes an ideal choice for processing high-definition video data.

[0048] The connection of the CameraLink circuit is as Figure 3 shown: There are multiple LVDS buffers, all of which are connected to the connector J1 and the FPGA. The circuit connection relationship of a single LVDS buffer is as follows: The positive differential input terminal IN+ and the negative differential input terminal IN- of the LVDS buffer are connected to the differential signal output terminal of the connector J1;

[0049] The configuration terminal EQ0 of the LVDS buffer is connected to the first end of the first resistor and the first end of the second resistor. The second end of the first resistor and the first end of the third resistor are connected to the power supply VCC3.3V; The second end of the third resistor and the first end of the fourth resistor are connected to the configuration terminal EQ1 of the LVDS buffer; The second end of the fourth resistor and the second end of the second resistor are connected to the power supply ground;

[0050] The positive differential output terminal OUT+ and the negative differential output terminal OUT- of the LVDS buffer are connected to the data transmission terminal of the FPGA;

[0051] The power supply terminal of the LVDS buffer, the first end of the first capacitor, and the first end of the second capacitor are connected to the power supply VCC3.3V; The grounding terminal of the LVDS buffer, the second end of the first capacitor, and the second end of the second capacitor are connected to the power supply ground.

[0052] In addition, there is also a driver chip. The data transmission terminal D of the driver chip is connected to the data input terminal of the CPU. The data enable terminal DE of the driver chip is connected to the first end of the resistor R78, and the second end of the resistor R78 is connected to the power supply VCC3.3V;

[0053] The row clock terminal R of the driver chip is connected to the data output terminal of the CPU, and the negative logic row enable terminal RE_N of the driver chip is connected to the power supply ground;

[0054] The output data terminal Y, the data transmission indication terminal Z, the address terminal A, and the output data terminal B of the driver chip are all connected to the connector J1, and the connector J1 is connected to the camera;

[0055] The power supply terminal VCC1 of the driver chip, the power supply terminal VCC2 of the driver chip, the first end of the capacitor C14, and the first end of the capacitor C15 are connected to the power supply VCC3.3V; The second end of the capacitor C14 and the second end of the capacitor C15 are connected to the power supply ground;

[0056] The grounding terminal GND1 and the grounding terminal GND2 of the driver chip are connected to the power supply ground.

[0057] The camera can also be directly connected to the CPU through the USB interface. The circuit connection is as Figure 4 shown. There are the same number of USB connectors and common-mode transformers. The connection relationship is as follows:

[0058] The positive differential signal terminal USB2_DP of the primary side of the common mode transformer and the negative differential signal terminal USB2_DM of the primary side of the common mode transformer are respectively connected to the differential signal input terminal and the differential signal output terminal of the CPU; the positive differential signal terminal DUSB2_L_D+ of the secondary side of the common mode transformer and the negative differential signal terminal DUSB2_L_D- of the secondary side of the common mode transformer are respectively connected to the data terminal D+ of the USB connector and the data terminal D- of the USB connector;

[0059] The data output terminal of the ESD anti-static protection device is connected to the data input terminal of the USB connector, and the data input terminal of the ESD anti-static protection device is connected to the data output terminal of the USB connector;

[0060] The power supply terminal VBUS of the USB connector is connected to the first end of the bead and the first end of the third capacitor, and the second end of the third capacitor is connected to the power ground; the second end of the bead is connected to the power supply USB1_P1_PWR;

[0061] The data terminal D- of the USB connector is connected to the anode of the first TVS diode, and the data terminal D+ of the USB connector is connected to the anode of the second TVS diode; the cathodes of the first TVS diode and the second TVS diode are connected to the power ground;

[0062] The connector type identification terminal ID of the USB connector is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the power ground;

[0063] The negative USB 3.0 data transmission terminal SSTX- of the USB connector, the positive USB 3.0 data transmission terminal SSTX+ of the USB connector, the negative USB 3.0 data reception terminal SSRX- of the USB connector, and the positive USB 3.0 data reception terminal SSRX+ of the USB connector are all connected to the ESD anti-static protection device;

[0064] The ground terminal GND_DRAIN of the USB connector is connected to the power ground.

[0065] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A high-efficiency image acquisition device, characterized in that: include: Camera, FPGA, DDR3 and CPU; the data output end of the camera is connected to the data input end of the FPGA through the Camera Link interface; the data output end of the camera is connected to the data input end of the CPU through the USB interface and the network interface; the data transmission end of the FPGA is respectively connected to the data transmission end of the CPU and the data transmission end of the DDR3.

2. The high-efficiency image acquisition device according to claim 1, characterized in that: The Camera Link interface circuit has an LVDS buffer, and the Camera Link interface circuit includes: The differential input positive terminal IN+ and the differential input negative terminal IN- of the LVDS buffer are connected to the differential signal output terminal of the connector J1; The configuration terminal EQ0 of the LVDS buffer is connected to the first end of the first resistor and the first end of the second resistor, the second end of the first resistor and the first end of the third resistor are connected to the power supply VCC3.3V; the second end of the third resistor and the first end of the fourth resistor are connected to the configuration terminal EQ1 of the LVDS buffer; the second end of the fourth resistor and the second end of the second resistor are connected to the power supply ground; The differential output positive terminal OUT+ of the LVDS buffer and the differential output negative terminal OUT- of the LVDS buffer are connected to the data transmission terminal of the FPGA; The power supply end of the LVDS buffer, the first end of the first capacitor, and the first end of the second capacitor are connected to the power supply VCC3.3V; the ground end of the LVDS buffer, the second end of the first capacitor, and the second end of the second capacitor are connected to the power ground.

3. The high-efficiency image acquisition device according to claim 2, characterized in that: There are multiple LVDS buffers.

4. The high-efficiency image acquisition device according to claim 1, characterized in that: The data input terminal of the camera is connected to the data output terminal of the CPU.

5. The high-efficiency image acquisition device according to claim 4, characterized in that: The data transmission end of the camera is connected to the data transmission end of the CPU through the driver chip, including: The data transmission terminal D of the driver chip is connected to the data input terminal of the CPU, the data enable terminal DE of the driver chip is connected to the first end of the resistor R78, and the second end of the resistor R78 is connected to the power supply VCC3.3V; The row clock terminal R of the driver chip is connected to the data output terminal of the CPU, and the row enable negative logic terminal RE_N of the driver chip is connected to the power ground; The output data terminal Y, data transmission indication terminal Z, address terminal A, and output data terminal B of the driver chip are all connected to the connector J1, and the connector J1 is connected to the camera; The power supply terminal VCC1 of the driving chip, the power supply terminal VCC2 of the driving chip, the first end of the capacitor C14, and the first end of the capacitor C15 are connected to the power supply VCC3.3V; the second end of the capacitor C14 and the second end of the capacitor C15 are connected to the power ground; The ground terminal GND1 of the driving chip and the ground terminal GND2 of the driving chip are connected to the power ground.

6. The high-efficiency image acquisition device according to claim 1, characterized in that: The data output end of the camera is connected to the data input end of the CPU through the USB interface, including: The primary differential positive signal terminal USB2_DP of the common mode transformer and the primary differential negative signal terminal USB2_DM of the common mode transformer are respectively connected to the differential signal input terminal and the differential signal output terminal of the CPU; the secondary differential positive signal terminal DUSB2_L_D+ of the common mode transformer and the secondary differential negative signal terminal DUSB2_L_D- of the common mode transformer are respectively connected to the data terminal D+ of the USB connector and the data terminal D- of the USB connector; The data output end of the ESD anti-static protection device is connected to the data input end of the USB connector, and the data input end of the ESD anti-static protection device is connected to the data output end of the USB connector; The power terminal VBUS of the USB connector is connected to the first end of the magnetic bead and the first end of the third capacitor, and the second end of the third capacitor is connected to the power ground; the second end of the magnetic bead is connected to the power supply USB1_P1_PWR; The data terminal D- of the USB connector is connected to the anode of the first TVS diode, and the data terminal D+ of the USB connector is connected to the anode of the second TVS diode; the cathode of the first TVS diode and the cathode of the second TVS diode are connected to the power ground; The connector type identification terminal ID of the USB connector is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the power ground; The USB 3.0 data transmission negative terminal SSTX- of the USB connector, the USB 3.0 data transmission positive terminal SSTX+ of the USB connector, the USB 3.0 data receiving negative terminal SSRX- of the USB connector, and the USB 3.0 data receiving positive terminal SSRX+ of the USB connector are all connected to the ESD anti-static protection device; The ground terminal GND_DRAIN of the USB connector is connected to the power ground.

7. The high-efficiency image acquisition device according to claim 6, characterized in that: It includes several USB circuit parts.

8. The high-efficiency image acquisition device according to claim 1, characterized in that: The camera connected to the FPGA through the Camera Link interface is a high-definition camera.

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