VDMOS device capable of reducing electromagnetic interference and noise thereof

Abstract

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device for reducing electromagnetic interference and noise thereof, which comprises a VDMOS device formed by mutually paralleling a plurality of VDMOS cells, each VDMOS cell comprises a drain electrode, a metal source electrode, a grid electrode and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and an N well layer, and the N well layer is isolated from the diffusion layer through the P well layer; wherein the drift layer is formed by injecting phosphorus elements with different concentrations into the diffusion layer, and the drift layer comprises a first drift layer, a second drift layer, a third drift layer and a fourth drift layer; the P well layer comprises a first lightly doped P well layer and a first heavily doped P well layer. According to the utility model, the drift layer is introduced into the diffusion layer, the drift layer can reduce the peak value of the grid voltage and prevent the peak voltage from puncturing the semiconductor epitaxial layer, and the concentration of the inner ring of the drift layer is similar to that of the N well layer, so that the on-resistance of a charge channel can be reduced, and the optimization of the EMI noise of the switch is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a VDMOS device for reducing electromagnetic interference and its noise. Background Technique

[0002] A VDMOS (Vertical Double-diffused MOS) device is a vertical double-diffused MOS (Metal Oxide Semiconductor) device. This device is well-known for its structural characteristics and is mainly used in power electronics applications. VDMOS devices have advantages such as low on-resistance, high breakdown voltage, and high-speed switching, and are suitable for occasions that require high-performance power switches, such as power management, electric vehicle control, frequency converters, etc.

[0003] A prior patent discloses a superjunction VDMOS device with dynamic charge balance (publication number CN102810567A), belonging to the field of power semiconductor devices. In the utility model, deep-level impurities are doped into the epitaxial region (3) of the superjunction structure of a conventional superjunction VDMOS device (for N-channel devices, donor impurities S, Se, or Te are doped; for P-channel devices, acceptor impurities In, Ti, or Zn are doped). In the technology disclosed in this patent, the switching response speed of the VDMOS device is optimized by doping particles into the diffusion layer. However, it is difficult to reduce the influence of the peak voltage of the gate voltage on the semiconductor epitaxial layer with this method of particle impurities;

[0004] Moreover, the capacitance value of the capacitor formed between the 'gate-drain' affects the switching speed and EMI (electromagnetic interference) characteristics of the device. When the capacitance value of the superjunction device is smaller, the Miller plateau of the switching curve is shorter, the switching speed is faster, and the switching loss is smaller. However, at the same time, the oscillation of the drain voltage and current increases significantly, resulting in a contradiction that the switching loss and EMI noise are difficult to adjust. Summary of the Invention

[0005] The main technical problem to be solved by the utility model is to provide a VDMOS device for reducing electromagnetic interference and its noise, solving the problems in the above background technique.

[0006] To solve the above technical problem, according to one aspect of the utility model, more specifically, a VDMOS device for reducing electromagnetic interference and its noise includes a VDMOS device composed of a plurality of VDMOS cells arranged in parallel. The VDMOS cell includes a drain, a metal source, a gate, and a semiconductor epitaxial layer;

[0007] The semiconductor epitaxial layer includes a substrate layer, a diffusion layer, a P-well layer, and an N-well layer. The N-well layer is isolated from the diffusion layer by the P-well layer;

[0008] Among them, a drift layer is formed inside the diffusion layer by injecting phosphorus elements with different concentrations. The drift layer includes a first drift layer, a second drift layer, a third drift layer, and a fourth drift layer;

[0009] The P-well layer includes a lightly doped first P-well layer and a heavily doped first P-well layer;

[0010] The N-well layer includes a heavily doped first N-well layer and a heavily doped second N-well layer. Only the heavily doped first N-well layer in the N-well layer is ohmically shorted to the metal source electrode.

[0011] Furthermore, the cross-sectional profiles of the lightly doped first P-well layer and the heavily doped first P-well layer are both in an 'L' shape, and the lightly doped first P-well layer and the heavily doped first P-well layer are in an interlocking state.

[0012] Furthermore, the heavily doped first N-well layer and the heavily doped second N-well layer have the same thickness and similar shapes in cross-sectional profiles.

[0013] Furthermore, when the gate is connected to the gate voltage, a charge channel is formed inside the lightly doped first P-well layer, and the N-well layer and the diffusion layer are conducted through the charge channel.

[0014] Furthermore, when the gate is connected to the gate voltage, a depletion region is formed inside the second drift layer.

[0015] Furthermore, the first drift layer and the third drift layer between adjacent VDMOS cells are integrated as a whole.

[0016] Furthermore, the fourth drift layer has the same thickness as the cross-sectional profile of the lightly doped first P-well layer, and the fourth drift layer is only in ohmic contact with the lightly doped first P-well layer.

[0017] Furthermore, the lightly doped first P-well layer is doped with low-concentration boron ions by ion implantation.

[0018] Furthermore, the heavily doped second N-well layer, the substrate layer, the heavily doped first N-well layer, and the fourth drift layer are doped with high-concentration phosphorus ions by ion implantation; the first drift layer, the second drift layer, and the third drift layer are doped with low-concentration phosphorus ions by ion implantation.

[0019] Furthermore, a gate oxide layer is deposited between the surface of the gate and the metal source electrode and the semiconductor epitaxial layer.

[0020] The beneficial effects of the VDMOS device of the present utility model for reducing electromagnetic interference and its noise are as follows:

[0021] 1. The utility model introduces a drift layer into the diffusion layer, which can reduce the peak value of the gate voltage and prevent the peak voltage from breaking through the semiconductor epitaxial layer. In addition, since the concentration of the inner circle of the drift layer is similar to that of the N-well layer, the on-resistance of the charge channel can be reduced, thereby optimizing the switching EMI noise.

[0022] 2. The utility model adds a drift layer between adjacent P-well layers to prevent the charge from flowing mutually in the P-wells of adjacent VDMOS cells, thereby ensuring the stability of the charge in the formed charge channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0024] Figure 1 It is a schematic diagram of the structure of the VDMOS device in the utility model;

[0025] Figure 2 It is a schematic diagram of the structure of a single VDMOS cell of the utility model;

[0026] Figure 3 This is a partial enlarged view of a single VDMOS cell of the utility model.

[0027] In the figure: 1. drain; 2. substrate layer; 3. diffusion layer; 4. metal source; 5. gate oxide layer; 6. gate; 7. heavily doped N-well layer 1; 8. heavily doped N-well layer 2; 9. lightly doped P-well layer 1; 10. heavily doped P-well layer 1; 11. drift layer 1; 12. drift layer 2; 13. drift layer 3; 14. drift layer 4. DETAILED DESCRIPTION

[0028] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0029] like Figures 1-3 As shown, according to one aspect of the utility model, a VDMOS device for reducing electromagnetic interference and its noise is provided, including a VDMOS device composed of a plurality of VDMOS cells arranged in parallel, the VDMOS cell including a drain 1, a metal source 4, a gate 6 and a semiconductor epitaxial layer; a gate oxide layer 5 is deposited between the surface of the gate 6 and the metal source 4 and the semiconductor epitaxial layer, the gate oxide layer 5 can ensure the formation of the gate electric field, and will not be directly connected to the drain 1 due to the voltage access to the gate 6. The semiconductor epitaxial layer includes a substrate layer 2, a diffusion layer 3, a P-well layer and an N-well layer, and the N-well layer and the diffusion layer 3 are isolated by the P-well layer (such as Figure 1As shown, after the gate voltage is applied to the gate 6, the charges in the P-well layer will accumulate on the surface area of the gate oxide layer 5 to form a charge channel. In this way, the N-well layer will be connected to the diffusion layer 3. Since the metal source 4 is connected to the N-well layer and the drain 1 is connected to the diffusion layer 3, the drain 1 will be connected to the metal source 4.

[0030] In this embodiment, a drift layer is formed inside the diffusion layer 3 by implanting different concentrations of phosphorus elements. The drift layer includes a first drift layer 11, a second drift layer 12, a third drift layer 13, and a fourth drift layer 14. The drift layer region is formed in the diffusion layer 3 by ion implantation. Since the concentrations of ion implantation are different, different levels of drift layers will be formed. In this way, the drift layer can reduce the peak value of the gate voltage and avoid the peak voltage from breaking down the semiconductor epitaxial layer.

[0031] The P-well layer includes a lightly doped first P-well layer 9 and a heavily doped first P-well layer 10. The N-well layer includes a heavily doped first N-well layer 7 and a heavily doped second N-well layer 8. Only the heavily doped first N-well layer 7 in the N-well layer is ohmically shorted to the metal source 4.

[0032] Among them, the doping concentration of the lightly doped first P-well layer 9 is 4 - 7×10 16 mol / cm 3 .

[0033] The above-mentioned lightly doped first P-well layer 9 and heavily doped first P-well layer 10 are both formed by doping boron element impurities.

[0034] The doping concentrations of the heavily doped second N-well layer 8 and the fourth drift layer 14 are both 3.6 - 6×10 18 mol / cm 3 ;

[0035] The doping concentrations of the substrate layer 2 and the heavily doped first N-well layer 7 are 6.8 - 9×10 18 mol / cm 3 ;

[0036] The doping concentration of the first drift layer 11 is 1.6 - 3.2×10 16 mol / cm 3 ;

[0037] The doping concentration of the second drift layer 12 is 7 - 9.5×10 16 mol / cm 3 ;

[0038] The doping concentration of the third drift layer 13 is 4 - 6×10 16 mol / cm 3 ;

[0039] The above-mentioned heavily doped N-well layer 8, drift layer 14, substrate layer 2, heavily doped N-well layer 7, drift layer 11, drift layer 12, and drift layer 13 are all formed by doping with phosphorus element impurities.

[0040] In this embodiment, the cross-sectional profiles of the lightly doped P-well layer 9 and the heavily doped P-well layer 10 are both in an 'L' shape, and the lightly doped P-well layer 9 and the heavily doped P-well layer 10 are in an interlocking state. This interlocking design can not only divide the P-well layer into two levels but also ensure that when the charge channel is formed, the charge accumulation mainly occurs inside the lightly doped P-well layer 9. The thicknesses of the cross-sectional profiles of the heavily doped N-well layer 7 and the heavily doped N-well layer 8 are the same, and the shapes are similar (as Figure 3 shown). Since the contour shapes of the heavily doped N-well layer 7 and the heavily doped N-well layer 8 are the same, this can reduce the lateral intervention of the gate electric field on the charges in the N-well layer and avoid the problem of all charges gathering at the position of the gate oxide layer 5.

[0041] In this embodiment, when the gate 6 is connected to the gate voltage, a charge channel is formed inside the lightly doped P-well layer 9, and the N-well layer and the diffusion layer 3 are conducted through the charge channel. When the gate 6 is connected to the gate voltage, a depletion region is formed inside the drift layer 12. By controlling the gate voltage, the conductivity of the JFET region can be adjusted, thereby affecting the overall performance and function of the device.

[0042] In this embodiment, the drift layer 11 and the drift layer 13 between adjacent VDMOS cells are integrated. The thickness of the cross-sectional profile of the drift layer 14 is the same as that of the lightly doped P-well layer 9, and the drift layer 14 is only in ohmic contact with the lightly doped P-well layer 9. The doping concentration of the drift layer 14 is the same as that of the doped N-well layer 8. In this way, the on-resistance of the two can be reduced to the minimum after the charge channel is formed.

[0043] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions, or substitutions made by those of ordinary skill in the art within the scope of the essence of the present invention also belong to the protection scope of the present invention.

Claims

1. A VDMOS device for reducing electromagnetic interference and noise, characterized in that: A VDMOS device comprising a plurality of VDMOS cells arranged in parallel, wherein the VDMOS cell comprises a drain (1), a metal source (4), a gate (6) and a semiconductor epitaxial layer; The semiconductor epitaxial layer comprises a substrate layer (2), a diffusion layer (3), a P-well layer and an N-well layer, wherein the N-well layer and the diffusion layer (3) are isolated from each other by the P-well layer; wherein a drift layer is formed by injecting phosphorus elements of different concentrations into the interior of the diffusion layer (3), and the drift layer comprises a drift layer 1 (11), a drift layer 2 (12), a drift layer 3 (13) and a drift layer 4 (14); The P-well layer includes a lightly doped P-well layer 1 (9) and a heavily doped P-well layer 1 (10); The N-well layer comprises a heavily doped N-well layer 1 (7) and a heavily doped N-well layer 2 (8), and among the N-well layers, only the heavily doped N-well layer 1 (7) is ohmically short-circuited with the metal source electrode (4).

2. The VDMOS device for reducing electromagnetic interference and noise according to claim 1, characterized in that: The cross-sectional profiles of the lightly doped P-well layer 1 (9) and the heavily doped P-well layer 1 (10) are both in an "L" shape, and the lightly doped P-well layer 1 (9) and the heavily doped P-well layer 1 (10) are in a mutually interlocking state.

3. The VDMOS device for reducing electromagnetic interference and noise according to claim 1, characterized in that: The cross-sectional profiles of the heavily doped N-well layer 1 (7) and the heavily doped N-well layer 2 (8) have the same thickness and similar shapes.

4. The VDMOS device for reducing electromagnetic interference and noise according to claim 1, characterized in that: When the gate (6) is connected to a gate voltage state, a charge channel is formed inside the lightly doped P-well layer (9), and the N-well layer and the diffusion layer (3) are connected through the charge channel.

5. The VDMOS device for reducing electromagnetic interference and noise according to claim 4, characterized in that: When the gate (6) is connected to a gate voltage state, a depletion region is formed in the second drift layer (12).

6. The VDMOS device for reducing electromagnetic interference and noise according to claim 1, characterized in that: The drift layer 1 (11) and the drift layer 3 (13) between the adjacent VDMOS cells are integrated as a whole.

7. The VDMOS device for reducing electromagnetic interference and noise according to claim 1, characterized in that: The drift layer four (14) has the same thickness as the cross-sectional profile of the lightly doped P-well layer one (9), and the drift layer four (14) is only in ohmic contact with the lightly doped P-well layer one (9).

8. The VDMOS device for reducing electromagnetic interference and noise according to claim 1, characterized in that: The lightly doped P-well layer 1 (9) is doped with low concentration of boron ions by ion implantation.

9. The VDMOS device for reducing electromagnetic interference and noise according to claim 1, characterized in that: The heavily doped N-well layer 2 (8), the substrate layer (2), the heavily doped N-well layer 1 (7) and the drift layer 4 (14) are doped with high concentration of phosphorus ions by ion implantation; The drift layer 1 (11), the drift layer 2 (12) and the drift layer 3 (13) are doped with low-concentration phosphorus ions by ion implantation.

10. The VDMOS device for reducing electromagnetic interference and noise according to claim 1, characterized in that: A gate oxide layer (5) is deposited between the surface of the gate (6), the metal source (4) and the semiconductor epitaxial layer.

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