Planar power metal oxide semiconductor with improved avalanche characteristic

Abstract

The utility model discloses a planar power metal oxide semiconductor with improved avalanche characteristics, which comprises a plurality of repetitive units, and any repetitive unit structurally comprises an epitaxial layer, a plurality of metal oxide semiconductor layers and a plurality of metal oxide semiconductor layers, a P well region; the oxide layer is deposited in the P-type well region; the P-type polycrystalline silicon is formed in the P-type well region; the N + well region is formed in the P-type well region; the P + well region is formed in the P-type well region; the gate oxide layer is located on the upper surface of the epitaxial layer; the gate polycrystalline silicon is located on the upper surface of the gate oxide layer; the gate electrode oxide layer and the gate electrode polycrystalline silicon are coated in the dielectric layer; and the metal layer is deposited on the upper surface of the whole device and is in contact with the P-type polycrystalline silicon through a metal contact hole. By optimizing the internal structure of the device, avalanche collapse caused by premature conduction of the built-in BJT of the device can be avoided on the premise of not influencing other static characteristics of the device, so that the avalanche characteristic of the device is improved.

Description

Technical Field

[0001] The utility model belongs to the fields of electronic components, semiconductors, and integrated circuits, and particularly relates to a planar power metal oxide semiconductor with improved avalanche characteristics. Background Art

[0002] The structure of a power metal oxide semiconductor field effect transistor (Power MOSFET) can be divided into a trench structure and a planar structure. Among them, the planar structure is generally used in high-voltage application scenarios, while the trench is more commonly used in low-voltage application scenarios. However, for MOSFET devices of any structure, the application end has strict requirements for their avalanche breakdown performance. Although the device itself has a certain avalanche resistance, how to enhance the avalanche breakdown performance of the device has been widely studied. Content of the Utility Model

[0003] In order to overcome the above deficiencies, the utility model provides a planar power metal oxide semiconductor with improved avalanche characteristics. By optimizing the internal structure of the device, it is possible to avoid avalanche breakdown caused by the premature conduction of the built-in BJT without affecting other static characteristics of the device, thereby improving the avalanche characteristics of the device.

[0004] The main technical solution adopted in the utility model is as follows:

[0005] A planar power metal oxide semiconductor with improved avalanche characteristics includes a plurality of repetitive units. The structure of any one repetitive unit includes:

[0006] An epitaxial layer, disposed on a substrate;

[0007] A P-well region, located on the inner surface of the epitaxial layer;

[0008] An oxide layer, deposited in the P-type well region;

[0009] P-type polysilicon, formed in the P-type well region and located on the upper surface of the oxide layer;

[0010] An N+-well region, formed in the P-type well region and located on both sides of the P-type polysilicon, in partial contact with the P-type polysilicon;

[0011] A P+-well region, formed in the P-type well region and located on both sides of the oxide layer and the P-type polysilicon. The P+-well region is in partial contact with the oxide layer and the P-type polysilicon respectively, and the P+-well region is located below the N+-well region;

[0012] A gate oxide layer, located on the upper surface of the epitaxial layer, and both ends of the gate oxide layer cover the upper surfaces of the P-well region and the N+-well region;

[0013] The gate polysilicon is located on the upper surface of the gate oxide layer;

[0014] The dielectric layer encapsulates both the gate oxide layer and the gate polysilicon, and a metal contact hole is provided on the dielectric layer to expose the upper surface of the P-type polysilicon;

[0015] The metal layer is deposited on the upper surface of the entire device and is in contact with the P-type polysilicon through the metal contact hole.

[0016] Preferably, the epitaxial layer is an N-epitaxial layer with a concentration ≥ 1e16 cm -3 .

[0017] Preferably, the thickness of the gate oxide layer is 0.02 - 0.1 um.

[0018] Preferably, the thickness of the gate polysilicon is 0.5 um - 1.0 um.

[0019] Preferably, the doping concentration of the P-well region is 5e12 - 5e13 cm -2 .

[0020] Preferably, the doping concentration of the N+ well region is 5e14 - 1e16 cm -2 .

[0021] Preferably, the doping concentration of the P+ well region is 1e14 - 1e15 cm -2 .

[0022] Preferably, the doping concentration of the P-type polysilicon is 1e14 - 1e15 cm -2 .

[0023] Preferably, the thickness of the dielectric layer is 0.8 um - 1.3 um.

[0024] Preferably, the upper surface of the P-type polysilicon is lower than the upper surface of the N+ well region, and the height difference between the two is ≥ 0.1 um.

[0025] Beneficial effects: The present utility model provides a planar power metal oxide semiconductor with improved avalanche characteristics. By optimizing the internal structure of the device, P-type polysilicon is used to replace the areas that cannot be achieved by the P+ well region in the existing structure, thereby increasing the concentrations of the entire P-well region and the P+ well region, further reducing the built-in Rb resistance in the device, thus avoiding avalanche breakdown caused by premature conduction of the built-in BJT in the device, while not affecting other static characteristics of the device. Description of the Drawings

[0026] Figure 1 It is a schematic structural diagram of an existing planar power metal oxide semiconductor;

[0027] Figure 2 Schematic structural diagram (substrate omitted) of the planar power metal oxide semiconductor of Example 1;

[0028] In the figure: epitaxial layer 001, P-well region 002, oxide layer 003, P-type polysilicon 004, N+-well region 005, P+-well region 006, gate oxide layer 007, gate polysilicon 008, dielectric layer 009, metal layer 010. Detailed implementation manners

[0029] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application. Example 1

[0030] A planar power metal oxide semiconductor with improved avalanche characteristics includes a plurality of repetitive units, as Figure 2 shown. The structure of any one repetitive unit includes:

[0031] An epitaxial layer 001, disposed on the substrate; in this Example 1, the epitaxial layer 001 is an N-epitaxial layer with a concentration ≥ 1e16 cm -3 , and the doping ion type is preferably phosphorus.

[0032] A P-well region 002, located on the inner surface of the epitaxial layer 001; in this Example 1, the doping concentration of the P-well region is 5e12 - 5e13 cm -2 , and the doping ion type is preferably boron.

[0033] An oxide layer 003, deposited in the P-type well region 002. In this Example 1, the purpose of setting the oxide layer 003 is to block the ion implantation of boron difluoride and avoid affecting the lower contour of the P-well region 002;

[0034] A P-type polysilicon 004, formed in the P-type well region 002 and located on the upper surface of the oxide layer 003; in this Example 1, the doping concentration of the P-type polysilicon is 1e14 - 1e15 cm -2 , and the doping ion is preferably boron ion.

[0035] An N+-well region 005, formed in the P-type well region 002 and located on both sides of the P-type polysilicon 004, in partial contact with the P-type polysilicon 004; in this Example 1, the doping concentration of the N+-well region is 5e14 - 1e16 cm -2 , and the doping ion type is preferably arsenic or phosphorus.

[0036] The P+ well region 006 is formed within the P-type well region 002 and is located on both sides of the oxide layer 003 and the P-type polysilicon 004. The P+ well region 006 is in partial contact with the oxide layer 003 and the P-type polysilicon 004 respectively. The P+ well region 006 is located below the N+ well region 005. In this Embodiment 1, the doping concentration of the P+ well region is 1e14 - 1e15 cm -2 , and the doping ion species is boron difluoride.

[0037] The gate oxide layer 007 is located on the upper surface of the epitaxial layer 001, and both ends of the gate oxide layer 007 cover the upper surfaces of the P well region 002 and the N+ well region 005. In this Embodiment 1, the thickness of the gate oxide layer can be selectively designed according to different design applications, generally 0.02 - 0.1 um,

[0038] The gate polysilicon 008 is located on the upper surface of the gate oxide layer 007. In this Embodiment 1, the thickness of the gate polysilicon 008 is 0.5 um - 1.0 um.

[0039] The dielectric layer 009 wraps both the gate oxide layer 007 and the gate polysilicon 008, and a metal contact hole is provided on the dielectric layer 009 to expose the upper surface of the P-type polysilicon 004. In this Embodiment 1, the thickness of the dielectric layer 009 is 0.8 um - 1.3 um.

[0040] The metal layer 010 is deposited on the upper surface of the entire device and is in contact with the P-type polysilicon 004 through the metal contact hole.

[0041] In this Embodiment 1, the upper surface of the P-type polysilicon is lower than the upper surface of the N+ well region, and the height difference between the two is ≥0.1 um.

[0042] The design principle of the present utility model is as follows:

[0043] As Figure 1 shown is the existing planar power metal oxide semiconductor. In this structure, if a smaller Rb resistance value is desired, the concentrations of the entire P well region and the P+ well region are required to be very high. However, generally, the P+ well region cannot be made too deep because there is a certain ratio between the longitudinal and lateral diffusion of the P+ well region. If the P+ well region is made too deep, the lateral part may possibly enclose the entire N+ well region. In the present utility model, as Figure 2 shown, the P-type polysilicon is used to replace the regions that cannot be achieved by the P+ well region, thereby increasing the concentrations of the entire P well region and the P+ well region, thereby reducing the built-in Rb resistance in the MOSFET, thereby avoiding the avalanche breakdown caused by the premature conduction of the built-in BJT, and at the same time not affecting other static characteristics of the device.

[0044] The above are only the preferred embodiments of the present utility model. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present utility model, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present utility model.

Claims

1. A planar power metal oxide semiconductor with improved avalanche characteristics, comprising a plurality of repetitive units, characterized in that: Any repeating unit structure includes: An epitaxial layer is disposed on a substrate; A P-well region, located on the inner surface of the epitaxial layer; an oxide layer, deposited in the P-type well region; P-type polysilicon is formed in the P-type well region and is located on the upper surface of the oxide layer; N+ well regions are formed in the P-type well regions and are located on both sides of the P-type polysilicon and are in contact with the P-type polysilicon portion; A P+ well region is formed in the P-type well region and is located on both sides of the oxide layer and the P-type polysilicon, the P+ well region is in contact with the oxide layer and the P-type polysilicon portion respectively, and the P+ well region is located below the N+ well region; A gate oxide layer, located on the upper surface of the epitaxial layer, and both ends of the gate oxide layer cover the upper surfaces of the P well region and the N+ well region; Gate polysilicon, located on the upper surface of the gate oxide layer; A dielectric layer, wherein the dielectric layer covers the gate oxide layer and the gate polysilicon, and a metal contact hole is provided on the dielectric layer to expose the upper surface of the P-type polysilicon; The metal layer is deposited on the upper surface of the entire device and contacts the P-type polysilicon through metal contact holes.

2. The planar power metal oxide semiconductor with improved avalanche characteristics according to claim 1, characterized in that: The epitaxial layer is an N-epitaxial layer.

3. The planar power metal oxide semiconductor with improved avalanche characteristics according to claim 1, characterized in that: The thickness of the gate oxide layer is 0.02-0.1 um.

4. The planar power metal oxide semiconductor with improved avalanche characteristics according to claim 1, characterized in that: The thickness of the gate polysilicon is 0.5um-1.0um.

5. The planar power metal oxide semiconductor with improved avalanche characteristics according to claim 1, characterized in that: The thickness of the dielectric layer is 0.8um-1.3um.

6. The planar power metal oxide semiconductor with improved avalanche characteristics according to claim 1, characterized in that: The upper surface of the P-type polysilicon is lower than the upper surface of the N+ well region, and the height difference between the two is ≥0.1 um.

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