Thermal printing circuit and chip

Abstract

According to the thermal printing circuit and chip provided by the invention, the pixel state signals corresponding to the target pixel point and the reference pixel point are processed through the logic circuit to obtain the heating state signals, and then the heating state signals are output to the subsequent working module one by one through the output module; in addition, data storage, data transmission sequence configuration and corresponding data processing mode information configuration can be completed through a storage module, a selection module and a configuration module, so that the accuracy and effectiveness of heating state signal configuration are improved, the configuration time is shortened through multiple pixel state processing modes, and the configuration efficiency is improved. Therefore, the thermal printing configuration efficiency is improved, and the configuration compatibility of thermal printing is also improved.

Description

Technical Field

[0001] This application relates to, but is not limited to, a thermal printing circuit and a chip. Background Art

[0002] On a thermal print head, there is a row of independently controllable heating points arranged at equal intervals. During printing, these heating points are in close contact with the thermal printing paper. When a specific point is heated, the color of the corresponding point on the thermal printing paper will become darker. At the same time, the thermal printing paper advances, completing the printing of one line. When printing an image, after the first line is printed, the second line is printed, and so on.

[0003] In some embodiments, usually only one preset thermal printing control algorithm is included. To replace the thermal printing algorithm, recoding is required, which is a large amount of work and the configuration efficiency is not high. Even configuration errors may occur, resulting in a waste of a large amount of time.

[0004] Therefore, a thermal printing circuit is needed to improve the configuration efficiency and compatibility of thermal printing. Summary of the Utility Model

[0005] This application provides a thermal printing circuit and a chip to improve the configuration efficiency and compatibility of thermal printing.

[0006] In a first aspect, this application provides a thermal printing circuit, which includes:

[0007] An input module, a logic module, and an output module;

[0008] Wherein, the input module is connected to the input end of the logic module, the output end of the logic module is connected to the output module; the output module is connected to the printing module;

[0009] And, the logic module is configured to perform a logic operation on the image signal input by the input module to obtain a heating state signal; the output module is configured to output the heating state signal;

[0010] The printing module is configured to heat the thermistor corresponding to the target pixel point according to the heating state signal and perform a printing operation according to each pixel point in the pixel image;

[0011] The circuit further includes a storage module, a selection module, and a configuration module;

[0012] Wherein, the storage module is connected to the input module through the selection module, and the configuration module is connected to the selection module and the logic module;

[0013] The storage module is used to store the pixel image of the original image. The pixel image includes a plurality of pixel points, and the pixel state of the pixel point is used to indicate the printing condition of the pixel point, including a printing state or a vacant state;

[0014] The input module includes a first input terminal and a second input terminal. The first input terminal is used to input a first pixel state signal corresponding to the target pixel point, and the second input terminal is one or more and is used to input a second pixel state signal of a reference pixel point corresponding to the target pixel point;

[0015] The configuration module is used to provide a configuration signal. The logic module is used to determine a logic circuit according to the configuration signal. The selection module is used to transmit the first pixel state signal and the second pixel state signal to the input module according to the configuration signal.

[0016] As an optional implementation manner, the heating state signal includes a first heating state signal and a second heating state signal;

[0017] Wherein, the first heating state signal is used to indicate the first heating degree of the thermistor corresponding to the target pixel point, and the second heating state signal is used to indicate the second heating degree of the thermistor corresponding to the target pixel point;

[0018] The first heating degree and the second heating degree are accumulative.

[0019] As an optional implementation manner, the first logic circuit in the logic module includes a first logic unit and a second logic unit. The first logic unit includes a signal holder, and the second logic unit includes a first NOT gate and a first AND gate;

[0020] Wherein, the input terminal of the signal holder is connected to the first input terminal, and the output terminal of the signal holder serves as the output terminal of the first logic unit; the input terminal of the first NOT gate is connected to the second input terminal, the input terminal of the first AND gate is connected to the output terminal of the first NOT gate and the first input terminal, and the output terminal of the first AND gate serves as the output terminal of the second logic unit;

[0021] Moreover, the first pixel state signal is used to indicate the state signal of the target pixel point, and the second pixel state signal is used to indicate the state signal of the first pixel point in the same column of the previous row of the target pixel point; the first logic unit is used to generate a first heating state signal with the same level as the first pixel state signal according to the first pixel state signal; the second logic unit is used to generate a second heating state signal according to the first pixel state signal and the second pixel state signal.

[0022] As an alternative embodiment, the second logic circuit in the logic module further includes a third logic unit, and the third logic unit includes a first OR gate, a second AND gate, a second NOT gate, and a third NOT gate;

[0023] Wherein, the second pixel status signal includes a first sub-signal, a second sub-signal, and a third sub-signal. The first sub-signal is used to indicate the status signal of the first pixel in the same column of the previous row of the target pixel. The second sub-signal is used to indicate the status signal of the second pixel adjacent to the left of the first pixel. The third sub-signal corresponds to the status signal of the third pixel adjacent to the right of the first pixel;

[0024] Wherein, the input terminals of the second NOT gate and the third NOT gate are connected to the second input terminal. The second NOT gate is used to invert the second sub-signal, and the third NOT gate is used to invert the third sub-signal. The input terminal of the first OR gate is connected to the output terminal of the second NOT gate and the output terminal of the third NOT gate. The input terminal of the second AND gate is connected to the first input terminal and the output terminal of the first OR gate. The output terminal of the second AND gate serves as the output terminal of the third logic unit;

[0025] And, the second heating status signal includes a first sub-status signal and a second sub-status signal. The output terminal of the first AND gate is used to output the first sub-status signal, and the output terminal of the second AND gate is used to output the second sub-status signal.

[0026] As an alternative embodiment, the third logic circuit in the logic module includes a first logic unit, a second logic unit, a fourth logic unit, and a fifth logic unit;

[0027] The fourth logic unit includes a fourth NOT gate, a second OR gate, and a third AND gate; the fifth logic unit includes a fifth NOT gate, a sixth NOT gate, and a fourth AND gate;

[0028] Wherein, the second pixel status signal includes a first sub-signal and a fourth sub-signal. The first sub-signal is used to indicate the status signal of the first pixel in the same column of the previous row of the target pixel. The fourth sub-signal is used to indicate the status signal of the fourth pixel in the same column of the next row of the target pixel;

[0029] The input terminal of the fourth NOT gate is connected to the second input terminal and is used to invert the first sub-signal. The input terminal of the second OR gate is connected to the second input terminal and the output terminal of the fourth NOT gate, and is used to perform an OR logic operation on the inverted signal of the first sub-signal and the fourth sub-signal. The input terminal of the third AND gate is connected to the first input terminal and the output terminal of the second OR gate. The output terminal of the third AND gate serves as the output terminal of the fourth logic unit;

[0030] The input terminal of the fifth NOT gate is connected to the first input terminal, and the input terminal of the sixth NOT gate is connected to the second input terminal. The fifth NOT gate is used to invert the first pixel status signal, and the sixth NOT gate is used to invert the first sub-signal. The input terminals of the fourth AND gate are connected to the second input terminal, the output terminal of the fifth NOT gate, and the output terminal of the sixth NOT gate, and are used to perform an AND logic operation on the fourth sub-signal, the inverted signal of the first sub-signal, and the inverted signal of the first pixel status signal. The output terminal of the fourth AND gate serves as the output terminal of the fifth logic unit;

[0031] Moreover, the first logic unit is used to generate a first heating status signal with the same level as the first pixel status signal according to the first pixel status signal; the second heating status signal includes a second sub-status signal, a third sub-status signal, and a fourth sub-status signal. The output terminal of the third AND gate is used to output the second sub-status signal, the output terminal of the first AND gate is used to output the third sub-status signal, and the output terminal of the fourth AND gate is used to output the fourth sub-status signal.

[0032] As an optional implementation manner, the fourth logic circuit in the logic module includes a first logic unit, a sixth logic unit, a seventh logic unit, and an eighth logic unit. The first logic unit includes a signal holder. The sixth logic unit includes a seventh NOT gate, an eighth NOT gate, a fifth AND gate, a sixth AND gate, a third OR gate, and a seventh AND gate. The seventh logic unit includes a ninth NOT gate, a tenth NOT gate, an eighth AND gate, a ninth AND gate, a fourth OR gate, and a tenth AND gate. The eighth logic unit includes an eleventh NOT gate, a twelfth NOT gate, a thirteenth NOT gate, a fourteenth NOT gate, a fifteenth NOT gate, a fifth OR gate, and an eleventh AND gate;

[0033] Among them, the second pixel status signal includes a first sub-signal, a second sub-signal, a third sub-signal, a fourth sub-signal, and a fifth sub-signal. The first sub-signal is used to indicate the status signal of the first pixel in the same column of the previous row of the target pixel point. The second sub-signal is used to indicate the status signal of the second pixel adjacent to the left of the first pixel point. The third sub-signal corresponds to the status signal of the third pixel adjacent to the right of the first pixel point. The fourth sub-signal is used to indicate the status signal of the fourth pixel in the same column of the next row of the target pixel point. The fifth sub-signal is used to indicate the status signal of the fifth pixel in the same column of the previous row of the first pixel point;

[0034] The input terminal of the seventh NOT gate is connected to the second input terminal, and the input terminal of the eighth NOT gate is connected to the second input terminal. The seventh NOT gate is used to invert the first sub-signal, and the eighth NOT gate is used to invert the fifth sub-signal. The input terminal of the fifth AND gate is connected to the output terminals of the seventh NOT gate and the eighth NOT gate, and is used to perform an AND logic operation on the inverted signal of the first sub-signal and the inverted signal of the fifth sub-signal. The input terminal of the sixth AND gate is connected to the output terminal of the seventh NOT gate and the second input terminal, and is used to perform an AND operation on the inverted signal of the first sub-signal and the fifth sub-signal. The input terminal of the third OR gate is connected to the output terminals of the fifth AND gate and the sixth AND gate. The input terminal of the seventh AND gate is connected to the output terminal of the third OR gate and the first input terminal. The output terminal of the seventh AND gate serves as the output terminal of the sixth logic unit;

[0035] The input terminal of the ninth NOT gate is connected to the second input terminal, and the input terminal of the tenth NOT gate is connected to the second input terminal. The ninth NOT gate is used to invert the first sub-signal, and the tenth NOT gate is used to invert the fifth sub-signal. The input terminal of the eighth AND gate is connected to the output terminals of the ninth NOT gate and the tenth NOT gate, and is used to perform an AND logic operation on the inverted signal of the first sub-signal and the inverted signal of the fifth sub-signal. The input terminal of the ninth AND gate is connected to the second input terminal and the output terminal of the tenth NOT gate, and is used to perform an AND logic operation on the first sub-signal and the inverted signal of the fifth sub-signal. The input terminal of the fourth OR gate is connected to the output terminals of the ninth AND gate and the tenth AND gate. The input terminal of the tenth AND gate is connected to the output terminal of the fourth OR gate and the first input terminal. The output terminal of the tenth AND gate serves as the output terminal of the seventh logic unit;

[0036] The input terminal of the eleventh NOT gate is connected to the first input terminal, the input terminal of the twelfth NOT gate is connected to the second input terminal, the input terminal of the thirteenth NOT gate is connected to the second input terminal, the input terminal of the fourteenth NOT gate is connected to the second input terminal, the input terminal of the fifteenth NOT gate is connected to the second input terminal. The eleventh NOT gate is used to invert the first pixel state signal, the twelfth NOT gate is used to invert the first sub-signal, the thirteenth NOT gate is used to invert the fifth sub-signal, the fourteenth NOT gate is used to invert the second sub-signal, and the fifteenth NOT gate is used to invert the third sub-signal. The input terminal of the fifth OR gate is connected to the output terminals of the fourteenth NOT gate and the fifteenth NOT gate, and is used to perform an OR logic operation on the inverted signal of the second sub-signal and the inverted signal of the third sub-signal. The input terminals of the eleventh AND gate are connected to the second input terminal, the output terminal of the eleventh NOT gate, the output terminal of the twelfth NOT gate, the output terminal of the thirteenth NOT gate, and the output terminal of the fifth OR gate, and are used to perform an AND logic operation on the fourth sub-signal, the inverted signal of the first pixel state signal, the inverted signal of the first sub-signal, the inverted signal of the fifth sub-signal, and the output signal of the fifth OR gate. The output terminal of the eleventh AND gate serves as the output terminal of the eighth logic unit;

[0037] Moreover, the first logic unit is used to generate a first heating state signal with the same level as the first pixel state signal according to the first pixel state signal; the second heating state signal includes a second sub-state signal, a third sub-state signal, and a fourth sub-state signal. The output terminal of the seventh AND gate is used to output the second sub-state signal, the output terminal of the tenth AND gate is used to output the third sub-state signal, and the output terminal of the eleventh AND gate is used to output the fourth sub-state signal.

[0038] As an optional implementation manner, the output module includes a first clock pin, four FIFO registers, and four data signal pins;

[0039] The first clock pin is connected to the clock pin of the printing module for data transfer clock synchronization;

[0040] The input terminals of the four FIFO registers input the heating state signals according to a preset time sequence, and the output terminals are respectively connected to the four data signal pins, and are used to output the heating state signals simultaneously after the input of the heating state signals is completed;

[0041] The four data signal pins are respectively connected to the four data pins of the printing module for outputting the heating state signals to the printing module.

[0042] As an optional implementation manner, the circuit further includes a paper detection circuit;

[0043] The paper detection circuit includes:

[0044] A light-emitting diode, which is connected to a first power supply and is used for emitting an optical signal;

[0045] A light-receiving tube, which is connected in series with a sampling resistor between a second power supply and a ground voltage, and is used for generating a current change according to the received light intensity;

[0046] An amplifying circuit, the input end of which is connected to the connection point of the sampling resistor and the light-receiving tube, is used for collecting the voltage across the sampling resistor, and outputting a paper detection parameter according to the voltage across the sampling resistor, and the paper detection parameter is used for indicating the printable position of the paper of the printing module.

[0047] As an optional implementation manner, the amplifying circuit includes: a first resistor, a second resistor, a third resistor, an integrated operational amplifier and an analog-to-digital converter;

[0048] The first end of the first resistor is used as the input end of the amplifying circuit and is connected to the connection point of the sampling resistor and the light-receiving tube, and the other end of the first resistor is connected to the positive-phase input end of the integrated operational amplifier;

[0049] The first end of the second resistor is connected to the inverting input end of the integrated operational amplifier, and the other end of the second resistor is connected to the output end of the integrated operational amplifier;

[0050] The first end of the third resistor is connected to the inverting input end of the integrated operational amplifier and the first end of the second resistor, and the other end of the third resistor is connected to the ground voltage;

[0051] The output end of the integrated operational amplifier is connected to the input end of the analog-to-digital converter;

[0052] The output end of the analog-to-digital converter outputs a paper detection parameter.

[0053] In a second aspect, the present application provides a chip, and the chip includes the thermal printing circuit as described in the first aspect.

[0054] The thermal printing circuit and chip provided by the present application input the pixel state signals corresponding to the target pixel points and reference pixel points through the input module, so that the logic module performs logical operation processing on the pixel state signals to obtain the heating state signals, and then outputs the heating state signals to the subsequent working modules one by one through the output module. At the same time, the storage and configuration of the data transmission sequence can be completed through the storage module, selection module and configuration module, and the selection of the logic circuit can be completed through the configuration module. Thereby, the accuracy and effectiveness of the heating state signal configuration are improved, and the time required for configuration is reduced through a variety of pixel state processing logic circuits, thereby improving the thermal printing configuration efficiency and also improving the configuration compatibility of thermal printing. Description of the Drawings

[0055] The drawings herein are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application and used together with the specification to explain the principles of the present application.

[0056] Figure 1 is a schematic structural diagram of a thermal printing circuit disclosed in an embodiment of the present application;

[0057] Figure 2 is a schematic structural diagram of another thermal printing circuit disclosed in an embodiment of the present application;

[0058] Figure 3 is a schematic structural diagram of another thermal printing circuit disclosed in an embodiment of the present application;

[0059] Figure 4 is a schematic structural diagram of another thermal printing circuit disclosed in an embodiment of the present application;

[0060] Figure 5 is a schematic structural diagram of another thermal printing circuit disclosed in an embodiment of the present application;

[0061] Figure 6 is a schematic structural diagram of another thermal printing circuit disclosed in an embodiment of the present application;

[0062] Figure 7 is a schematic structural diagram of another thermal printing circuit disclosed in an embodiment of the present application;

[0063] Figure 8 is a schematic structural diagram of another thermal printing circuit disclosed in an embodiment of the present application;

[0064] Figure 9 is a schematic structural diagram of another thermal printing circuit disclosed in an embodiment of the present application;

[0065] Figure 10 is a schematic structural diagram of another thermal printing circuit disclosed in an embodiment of the present application;

[0066] Figure 11 It is a schematic diagram of the effect of a thermal printing circuit disclosed in an embodiment of the present application;

[0067] Figure 12 It is a schematic diagram of the structure of a thermal printing circuit disclosed in an embodiment of the present application;

[0068] Figure 13 It is a schematic diagram of the structure of a microprocessing chip disclosed in an embodiment of the present application.

[0069] Reference signs:

[0070] I1 - First power supply; I2 - Second power supply; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; A1 - Integrated operational amplifier; 11 - Input module; 12 - Logic module; 13 - Output module; 14 - Storage module; 15 - Configuration module; 16 - Selection module; 17 - Printing module; 101 - First logic unit; 102 - Second logic unit; 103 - Third logic unit; 104 - Fourth logic unit; 105 - Fifth logic unit; 106 - Sixth logic unit; 107 - Seventh logic unit; 108 - Eighth logic unit; 1001 - Signal holder; 1101 - First NOT gate; 1201 - First AND gate; 1301 - First OR gate; 1202 - Second AND gate; 1102 - Second NOT gate; 1103 - Third NOT gate; 1104 - Fourth NOT gate; 1302 - Second OR gate; 1203 - Third AND gate; 1105 - Fifth NOT gate; 1106 - Sixth NOT gate; 1204 - Fourth AND gate; 1107 - Seventh NOT gate; 1108 - Eighth NOT gate; 1205 - Fifth AND gate; 1206 - Sixth AND gate; 1303 - Third OR gate; 1207 - Seventh AND gate; 1109 - Ninth NOT gate; 1110 - Tenth NOT gate; 1208 - Eighth AND gate; 1209 - Ninth AND gate; 1304 - Fourth OR gate; 1210 - Tenth AND gate; 1305 - Fifth OR gate; 1211 - Eleventh AND gate; 1401 - First FIFO register; 1402 - Second FIFO register; 1403 - Third FIFO register; 1404 - Fourth FIFO register.

[0071] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed embodiments

[0072] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0073] On a thermal print head, there is a row of independently controllable heating points arranged at equal intervals. During printing, these heating points are in close contact with the thermal printing paper. When a specific point is heated, the corresponding point on the thermal printing paper will darken. At the same time, the thermal printing paper advances, completing the printing of one line. When printing an image, after the first line is printed, the second line is printed, and so on.

[0074] In some embodiments, usually only one preset thermal printing control algorithm is included. To replace the thermal printing algorithm, recoding is required, which is a large amount of work and the configuration efficiency is not high. Even configuration errors may occur, resulting in a waste of a large amount of time.

[0075] To improve the control effect of the thermistor, the technical concept of the present application is to input the pixel state signals corresponding to the target pixel points and reference pixel points through the input module, so that the logic module performs logical operation processing on the pixel state signals to obtain the heating state signals. Then, the heating state signals are output one by one to the subsequent working modules through the output module. At the same time, data storage and configuration of the data transmission sequence can be completed through the storage module, selection module, and configuration module, and the selection of the logic circuit can be completed through the configuration module. Thereby, the accuracy and effectiveness of the heating state signal configuration are improved, and the time required for configuration is reduced through multiple pixel state processing logic circuits. Thereby, the thermal printing configuration efficiency is improved, and the configuration compatibility of thermal printing is also improved. In summary, the printing effect is improved.

[0076] Embodiment 1

[0077] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a thermal printing circuit disclosed in an embodiment of the present application. As Figure 1 shown, the present application provides a thermal printing circuit, and the circuit includes:

[0078] An input module 11, a logic module 12, and an output module 13;

[0079] Among them, the input module 11 may include a first input end and a second input end. The input module 11 is connected to the input end of the logic module 12, and the output end of the logic module 12 is connected to the output module 13;

[0080] Moreover, the first input terminal is used to input the first pixel state signal P1 corresponding to the target pixel point Q0, and the second input terminals are one or more, and are used to input the second pixel state signals P2 of the reference pixel points corresponding to the target pixel point Q0; the logic module 12 is used to perform a logic operation on the image signal input by the input module 11 to obtain a heating state signal; the output module 13 is used to output the heating state signal;

[0081] The output module is used to output the heating state signal.

[0082] As an example, let P1 represent the first pixel state signal corresponding to the target pixel point Q0 input by the first input terminal, and let P2 represent the second pixel state signal P2 of the reference pixel point input by the second input terminal. In other embodiments, the state signal of the target pixel point Q0 can be uniformly used to represent the first pixel state signal P1.

[0083] Please refer to Figure 2 , Figure 2 FIG. is a schematic structural diagram of another thermal printing circuit disclosed in the embodiments of the present application. As an optional implementation manner, the circuit further includes a storage module 14, a configuration module 15, a selection module 16, and a printing module 17;

[0084] Among them, the storage module 14 is connected to the input module 11 through the selection module 16, the printing module 17 is connected to the output module 13, and the configuration module 15 is respectively connected to the selection module 16 and the logic module 12; moreover, the storage module 14 is used to determine the original image, and according to the original image, determine the pixel image, or directly store the pixel image corresponding to the original image; wherein, the pixel image includes a plurality of target pixel points Q0, and the pixel state of the target pixel point Q0 is used to indicate the printing condition of the pixel point, including the printing state or the vacant state;

[0085] The configuration module 15 is used to send configuration signals to the selection module 16 and the logic module 12 according to the user configuration information;

[0086] The selection module 16 is used to determine the reference pixel points of each target pixel point Q0 according to the configuration signal, and send the first pixel state signal P1 and the second pixel state signal P2 to the input module 11;

[0087] The logic module 12 determines the corresponding logic circuit according to the configuration signal, performs an operation on the first pixel state signal P1 and the second pixel state signal P2 by using the logic circuit corresponding to the pixel state processing mode, obtains the heating state signal, and outputs the heating state signal through the aforementioned output module 13;

[0088] The printing module 17 is used to heat the thermistor corresponding to the target pixel point Q0 according to the received heating state signal, and perform a printing operation according to each pixel point in the pixel image;

[0089] Among them, a feasible implementation manner of the logic module 12 is to integrally set a configuration module 15 for human-computer interaction. The user can set the pixel state processing mode through the interaction interface, so as to select a pixel state processing mode among multiple printing circuits. The logic module 12 selects a logic circuit according to the pixel state processing mode.

[0090] The thermosensitive printing circuit corresponding to the current pixel state processing mode is determined by the logic module 12, so as to control the heating degree of each thermistor of the printing module through the thermosensitive printing circuit, and thus complete the printing work through the printing module 17, thereby improving the efficiency and accuracy of the working state configuration of the thermistor, and thus improving the printing effect.

[0091] The pixel state signals corresponding to the target pixel point Q0 and the reference pixel point are input through the input module 11, so that the pixel state signals are logically operated and processed by the logic module 12 to obtain the heating state signal, and then the heating state signal is output to the subsequent working module one by one through the output module 13, thereby realizing the precise configuration of the heating state signal, that is, based on the distribution of the printing pixel points and the working state of the thermistor, the heating state signal corresponding to the thermistor is determined, improving the efficiency and effectiveness of the heating state signal configuration of the thermistor, and thus improving the printing effect.

[0092] As an optional implementation manner, the heating state signal includes a first heating state signal and a second heating state signal;

[0093] Among them, the first heating state signal is used to indicate the first heating degree of the thermistor corresponding to the target pixel point Q0, and the second heating state signal is used to indicate the second heating degree of the thermistor corresponding to the target pixel point Q0.

[0094] The first heating degree can be understood as an indication signal of whether to heat the thermistor, while the second heating degree can be understood as an indication signal of the specific heating degree of the thermistor.

[0095] Correspondingly, in some embodiments, the first heating degree and the second heating degree can be accumulated to jointly indicate the heating situation of the thermistor.

[0096] In some embodiments, the heating state signal may further include a third heating state signal for indicating the preheating state, and specific reference can be made to the corresponding description.

[0097] By separately configuring the first heating state signal and the second heating state signal, the accuracy of configuring the heating state signal of the thermistor is further improved, thereby improving the printing effect.

[0098] Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of another thermal printing circuit disclosed in the embodiments of the present application. As shown in Figure 3 , as an optional implementation manner, the logic module 12 includes a first logic circuit. The first logic circuit includes a first logic unit 101 and a second logic unit 102. The first logic unit 101 includes a signal holder 1001, and the second logic unit 102 includes a first NOT gate 1101 and a first AND gate 1201;

[0099] Among them, the input end of the signal holder 1001 is connected to the first input end, and the output end of the signal holder 1001 serves as the output end of the first logic unit 101; the input end of the first NOT gate 1101 is connected to the second input end, the input end of the first AND gate 1201 is connected to the output end of the first NOT gate 1101 and the first input end, and the output end of the first AND gate 1201 serves as the output end of the second logic unit 102;

[0100] The first pixel state signal P1 is used to indicate the state signal of the target pixel point Q0, and the second pixel state signal P2 is used to indicate the state signal of the first pixel point Q1 in the same column of the previous row of the target pixel point Q0;

[0101] Moreover, the first logic unit 101 is used to generate a first heating state signal with the same level as the first pixel state signal P1 according to the first pixel state signal P1; the second logic unit 102 is used to generate a second heating state signal according to the first pixel state signal P1 and the second pixel state signal P2.

[0102] Among them, Da is used to indicate the first heating state signal, and Db is used to indicate the second heating state signal.

[0103] By processing the pixel state signals from the input module 11 through the first logic unit 101 and the second logic unit 102, the first heating state signal and the second heating state signal can be respectively obtained, improving the accuracy of configuring the heating state signal of the thermistor, thereby improving the printing effect.

[0104] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of another thermal printing circuit disclosed in the embodiments of the present application. Moreover, please refer to Figure 5 , Figure 5 which is a schematic structural diagram of another thermal printing circuit disclosed in the embodiments of the present application. Figure 4 shows the input / output signal configuration method based on this embodiment, whileFigure 5 The implementation details of the corresponding logic module 12 are shown.

[0105] Among them, Da is used to indicate the first heating state signal, and Db and Dc serve as the first sub-state signal Db and the second sub-state signal Dc, respectively, and are used to jointly indicate the second heating state signal.

[0106] As an alternative implementation, the logic module 12 further includes a second logic circuit. The second logic circuit includes a third logic unit 103, and the third logic unit 103 includes a first OR gate 1301, a second AND gate 1202, a second NOT gate 1102, and a third NOT gate 1103;

[0107] Among them, the second pixel state signal P2 includes a first sub-signal, a second sub-signal, and a third sub-signal. The first sub-signal is used to indicate the state signal of the first pixel Q1 in the same column of the previous row of the target pixel Q0. The second sub-signal is used to indicate the state signal of the second pixel Q2 on the left side of the previous row of the target pixel Q0. The third sub-signal is used to indicate the state signal of the third pixel Q3 on the right side of the previous row of the target pixel Q0;

[0108] Among them, the input ends of the second NOT gate 1102 and the third NOT gate 1103 are connected to the second input end P2. The second NOT gate 1102 is used to invert the second sub-signal, and the third NOT gate 1103 is used to invert the third sub-signal. The input end of the first OR gate 1301 is connected to the output ends of the second NOT gate 1102 and the third NOT gate 1103. The input end of the second AND gate 1202 is connected to the first input end and the output end of the first OR gate 1301. The output end of the second AND gate 1202 serves as the output end of the third logic unit 103;

[0109] In addition, the second heating state signal includes a first sub-state signal Db and a second sub-state signal Dc. The output end of the first AND gate 1201 is used to output the first sub-state signal, and the output end of the second AND gate 1202 is used to output the second sub-state signal Dc.

[0110] Through the third logic unit 103, the precise configuration of the second heating state signal is realized. The second heating state signal is divided into a first sub-state signal Db and a second sub-state signal Dc, so as to indicate the second heating state signal through a multi-bit digital quantity, increasing the possible states of the second heating state signal, thereby improving the accuracy of the configuration of the heating state signal of the thermistor, and thus improving the printing effect.

[0111] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of another thermal printing circuit disclosed in the embodiments of the present application. In addition, please refer to Figure 7 , Figure 7It is a schematic structural diagram of another thermal printing circuit disclosed in the embodiments of the present application. Figure 6 It shows the input and output signal configuration method based on this embodiment. The pixel points in the same column of the upper and lower rows are used as inputs, and Figure 7 It shows the implementation details of the corresponding logic module 12.

[0112] As an optional implementation, the heating state signal further includes a third heating state signal;

[0113] Among them, the third heating state signal is used to indicate the preheating state of the thermistor corresponding to the third pixel point Q3 in the same column of the next row of the target pixel point Q0.

[0114] By indicating the preheating state through the third heating state signal, and combining the first heating state signal and the second heating state signal to jointly describe the heating situation of the thermistor, the accuracy of the thermistor heating state signal configuration is improved, thereby improving the printing effect.

[0115] As an optional implementation, the logic module 12 further includes a third logic circuit, and the third logic circuit includes a fourth logic unit 104 and a fifth logic unit 105;

[0116] The fourth logic unit 104 includes a fourth NOT gate 1104, a second OR gate 1302, and a third AND gate 1203, and the fifth logic unit 105 includes a fifth NOT gate 1105, a sixth NOT gate 1106, and a fourth AND gate 1204;

[0117] Among them, the second pixel state signal P2 includes a first sub-signal and a fourth sub-signal. The first sub-signal is used to indicate the state signal of the first pixel point Q1 in the same column of the upper row of the target pixel point Q0, and the fourth sub-signal is used to indicate the state signal of the fourth pixel point Q4 in the same column of the next row of the target pixel point Q0;

[0118] The input end of the fourth NOT gate 1104 is connected to the second input end, and is used to invert the first sub-signal. The input ends of the second OR gate 1302 are connected to the second input end and the output end of the fourth NOT gate 1104, and are used to perform an OR logic operation on the inverted signal of the first sub-signal and the fourth sub-signal. The input ends of the third AND gate 1203 are connected to the first input end and the output end of the second OR gate 1302, and the output end of the third AND gate 1203 is used as the output end of the fourth logic unit 104;

[0119] The input terminal of the fifth NOT gate 1105 is connected to the first input terminal, the input terminal of the sixth NOT gate 1106 is connected to the second input terminal. The fifth NOT gate 1105 is used to invert the first pixel status signal P1, and the sixth NOT gate 1106 is used to invert the first sub-signal. The input terminals of the fourth AND gate 1204 are connected to the second input terminal, the output terminal of the fifth NOT gate 1105, and the output terminal of the sixth NOT gate 1106, and are used to perform an AND logic operation on the first sub-signal, the inverted signal of the fourth sub-signal, and the inverted signal of the first pixel status signal P1;

[0120] Moreover, the second heating status signal includes a first sub-status signal Db and a second sub-status signal Dc. The output terminal of the first AND gate 1201 is used to output the second sub-status signal, the output terminal of the third AND gate 1203 is used to output the first sub-status signal Db, and the output terminal of the fourth AND gate 1204 is used to output the third heating status signal.

[0121] Wherein, in this embodiment, Da is used to indicate the first heating status signal, Db and Dc are used as two sub-status signals to jointly indicate the second heating status signal, and Dd is used to indicate the third heating status signal.

[0122] Wherein, the first heating status signal Da is the main heating status signal, Db and Dc jointly constitute the second heating status signal, and provide 4 heating levels for heating adjustment as a two-bit binary number. The third heating status signal Dd is used for preheating and is enabled when preheating is required for the next line after a long-time cooling.

[0123] The accuracy and effectiveness of the status signal configuration are further improved through the fourth logic unit 104 and the fifth logic unit 105, enabling the printing circuit to achieve the heating status signal configuration in the application scenario of more reference pixel points based on the target pixel point Q0. Thereby, the accuracy of the heating status signal configuration of the thermistor is improved, and the printing effect is enhanced.

[0124] In addition, in a scenario where various embodiments are combined and applied, please refer to Figure 8 , Figure 8 which is a schematic structural diagram of another thermal printing circuit disclosed in the embodiments of the present application. Moreover, please refer to Figure 9 , Figure 9 which is a schematic structural diagram of another thermal printing circuit disclosed in the embodiments of the present application. Correspondingly, Figure 8 shows the input-output signal configuration method based on this embodiment. The pixel signals corresponding to the same-column pixel points in the upper and lower rows, the same-column pixel points in the penultimate two rows, the adjacent-column pixel points in the upper row, and the target pixel point Q0 itself are used as inputs, while Figure 9 shows the implementation details of the corresponding logic module 12.

[0125] The logic module includes a fourth logic circuit, and the fourth logic circuit includes a first logic unit 101, a sixth logic unit 106, a seventh logic unit 107, and an eighth logic unit 108. The first logic unit includes a signal holder 1001. The sixth logic unit 106 includes a seventh NOT gate 1107, an eighth NOT gate 1108, a fifth AND gate 1205, a sixth AND gate 1206, a third OR gate 1303, and a seventh AND gate 1207. The seventh logic unit includes a ninth NOT gate 1109, a tenth NOT gate 1110, an eighth AND gate 1208, a ninth AND gate 1209, a fourth OR gate 1304, and a tenth AND gate 1210. The eighth logic unit includes an eleventh NOT gate, a twelfth NOT gate, a thirteenth NOT gate, a fourteenth NOT gate, a fifteenth NOT gate, a fifth OR gate 1305, and an eleventh AND gate 1211. For convenience, the eleventh NOT gate, the twelfth NOT gate, the thirteenth NOT gate, the fourteenth NOT gate, and the fifteenth NOT gate are not shown in the figure;

[0126] Wherein, the input end of the signal holder 1001 is connected to the first input end, and the output end of the signal holder serves as the output end of the first logic unit 1001;

[0127] The second pixel state signal P2 includes a first sub-signal, a second sub-signal, a third sub-signal, a fourth sub-signal, and a fifth sub-signal. The first sub-signal is used to indicate the state signal of the first pixel Q1 in the same column of the previous row of the target pixel Q0. The second sub-signal is used to indicate the state signal of the second pixel Q2 adjacent to the left of the first pixel Q1. The third sub-signal corresponds to the state signal of the third pixel Q3 adjacent to the right of the first pixel Q1. The fourth sub-signal is used to indicate the state signal of the fourth pixel Q4 in the same column of the next row of the target pixel Q0. The fifth sub-signal is used to indicate the state signal of the fifth pixel Q5 in the same column of the previous row of the first pixel Q1;

[0128] The input terminal of the seventh NOT gate 1107 is connected to the second input terminal, and the input terminal of the eighth NOT gate 1108 is connected to the second input terminal. The seventh NOT gate 1107 is used to invert the first sub-signal, and the eighth NOT gate 1108 is used to invert the fifth sub-signal. The input terminals of the fifth AND gate 1205 are connected to the output terminal of the seventh NOT gate 1207 and the output terminal of the eighth NOT gate 1208, and are used to perform an AND logic operation on the inverted signal of the first sub-signal and the inverted signal of the fifth sub-signal. The input terminals of the sixth AND gate 1206 are connected to the output terminal of the seventh NOT gate 1107 and the second input terminal, and are used to perform an AND operation on the inverted signal of the first sub-signal and the fifth sub-signal. The input terminal of the third OR gate 1303 is connected to the output terminal of the fifth AND gate 1205 and the output terminal of the sixth AND gate 1206. The input terminal of the seventh AND gate 1207 is connected to the output terminal of the third OR gate 1303 and the first input terminal. The output terminal of the seventh AND gate 1207 serves as the output terminal of the sixth logic unit 106;

[0129] The input terminal of the ninth NOT gate 1109 is connected to the second input terminal, and the input terminal of the tenth NOT gate 1110 is connected to the second input terminal. The ninth NOT gate 1109 is used to invert the first sub-signal, and the tenth NOT gate 1110 is used to invert the fifth sub-signal. The input terminals of the eighth AND gate 1208 are connected to the output terminal of the ninth NOT gate 1109 and the output terminal of the tenth NOT gate 1110, and are used to perform an AND logic operation on the inverted signal of the first sub-signal and the inverted signal of the fifth sub-signal. The input terminals of the ninth AND gate 1209 are connected to the second input terminal and the output terminal of the tenth NOT gate 1110, and are used to perform an AND logic operation on the first sub-signal and the inverted signal of the fifth sub-signal. The input terminal of the fourth OR gate 1304 is connected to the output terminal of the eighth AND gate 1208 and the output terminal of the ninth AND gate 1209. The input terminal of the tenth AND gate 1210 is connected to the output terminal of the fourth OR gate 1304 and the first input terminal. The output terminal of the tenth AND gate 1210 serves as the output terminal of the eighth logic unit;

[0130] The input terminal of the eleventh NOT gate is connected to the first input terminal, the input terminal of the twelfth NOT gate is connected to the second input terminal, the input terminal of the thirteenth NOT gate is connected to the second input terminal, the input terminal of the fourteenth NOT gate is connected to the second input terminal, the input terminal of the fifteenth NOT gate is connected to the second input terminal. The eleventh NOT gate is used to invert the first pixel state signal P1, the twelfth NOT gate is used to invert the first sub-signal, the thirteenth NOT gate is used to invert the fifth sub-signal, the fourteenth NOT gate is used to invert the second sub-signal, and the fifteenth NOT gate is used to invert the third sub-signal. The input terminal of the fifth OR gate 1305 is connected to the output terminal of the fifteenth NOT gate and the output terminal of the sixteenth NOT gate, and is used to perform an OR logic operation on the inverted signal of the second sub-signal and the inverted signal of the third sub-signal. The input terminals of the eleventh AND gate 1211 are connected to the second input terminal, the output terminal of the eleventh NOT gate, the output terminal of the twelfth NOT gate, the output terminal of the thirteenth NOT gate, and the output terminal of the fifth OR gate 1305, and is used to perform an AND logic operation on the fourth sub-signal, the inverted signal of the first pixel state signal P1, the inverted signal of the first sub-signal, the inverted signal of the fifth sub-signal, and the output signal of the fifth OR gate. The output terminal of the eleventh AND gate 1211 serves as the output terminal of the eighth logic unit;

[0131] Moreover, the first logic unit is used to generate a first heating state signal with the same level as the first pixel state signal P1 according to the first pixel state signal P1; the second heating state signal includes a first sub-state signal Db, a second sub-state signal Dc, and an eighth sub-state signal. The output terminal of the eighth AND gate is used to output the sixth sub-state signal, and the output terminal of the eleventh AND gate is used to output the seventh sub-state signal; the output terminal of the twelfth AND gate is used to output a third heating state signal.

[0132] For specific technical effects, reference may be made to the relevant descriptions in any of the foregoing embodiments.

[0133] Please refer to Figure 10 , Figure 10 which is a schematic structural diagram of a thermal printing circuit disclosed in an embodiment of the present application, showing the circuit structure for the output module 13 to output a heating state signal to the printing module.

[0134] The output module 13 includes a first FIFO register 1401, a second FIFO register 1402, a third FIFO register 1403, and a fourth FIFO register 1404;

[0135] The output module 13 is connected to the logic module and is used to receive the heating status signal output by the logic module. The first output terminals of the first FIFO register 1401, the second FIFO register 1402, the third FIFO register 1403, and the fourth FIFO register 1404 in the output module 13 are respectively connected to the printing module 14. There is also a clock line CLK connecting the output module 13 and the printing module 14. The first FIFO register 1401, the second FIFO register 1402, the third FIFO register 1403, and the fourth FIFO register 1404 are used to send the heating status signal to the printing module, and the clock line CLK is used for synchronization between the output module 13 and the printing module.

[0136] To make the signal output by the output module 13 conform to the format of the printing module, the logic module 12 outputs the heating status signal in serial format to the output module 13. The first FIFO register 1401, the second FIFO register 1402, and the third FIFO register 1403 also have second output terminals. The input terminal of the first FIFO register 1401 is connected to the logic module, the input terminal of the second FIFO register 1402 is connected to the second output terminal of the first FIFO register 1401, the input terminal of the third FIFO register 1403 is connected to the second output terminal of the second FIFO register 1402, and the input terminal of the fourth FIFO register 1404 is connected to the second output terminal of the third FIFO register 1403. When the first FIFO register 1401, the second FIFO register 1402, the third FIFO register 1403, and the fourth FIFO register 1404 are not full, the first FIFO register 1401, the second FIFO register 1402, and the third FIFO register 1403 transmit the heating status signal to the subsequent register through the second output terminal, and the first output terminals of the first FIFO register 1401, the second FIFO register 1402, the third FIFO register 1403, and the fourth FIFO register are deactivated. When the first FIFO register 1401, the second FIFO register 1402, the third FIFO register 1403, and the fourth FIFO register 1404 are full, the first FIFO register 1401, the second FIFO register 1402, the third FIFO register 1403, and the fourth FIFO register 1404 send the heating status signal to the printing module simultaneously.

[0137] Please refer to Figure 11 , Figure 11It is a schematic diagram of the effect of another thermal printing circuit disclosed in the embodiments of the present application. The rate of transmitting data to the printing module may affect the printing speed of the printing module. Therefore, the data transmission should be as fast as possible. However, limited by the hardware performance of the printing module, the frequency of the serial line has an upper limit. The present application transmits serial data through 4 data lines simultaneously, which can improve the transmission speed, and the transmitted data format meets the requirements of the printing module data format.

[0138] Figure 11 It shows a printing effect of output transmission with four data lines. The 1280-bit heating state signals are evenly divided into four segments of data, and each segment of data includes 320 bits of continuous data for transmission, which improves the transmission efficiency and meets the format requirements of the printing module, avoiding complex format conversion.

[0139] By simultaneously outputting the heating state signals to the printing module through the first FIFO register 1401, the second FIFO register 1402, the third FIFO register 1403, and the fourth FIFO register 1404, the signal transmission efficiency can be improved. Through the connection relationship of the first FIFO register 1401, the second FIFO register 1402, the third FIFO register 1403, and the fourth FIFO register 1404, the format of the transmitted signal can meet the requirements of the printing module, simplifying the data format conversion process; when the first FIFO register 1401, the second FIFO register 1402, the third FIFO register 1403, and the fourth FIFO register 1404 are full, they simultaneously send the heating state signals to the printing module, which can improve the signal synchronization and avoid the printing module receiving signals with incorrect timings.

[0140] Please refer to Figure 12 , Figure 12 It is a schematic structural diagram of another thermal printing circuit disclosed in the embodiments of the present application. As an optional implementation manner, the circuit may further include a paper detection circuit, specifically including:

[0141] A light-emitting diode, which is connected to the first power supply I1, and the light-emitting diode is used to emit an optical signal;

[0142] A light-receiving tube, which is connected in series with a sampling resistor between the second power supply I2 and the ground voltage, and the light-receiving tube is used to generate a current change according to the received light intensity;

[0143] Collect the voltage across the sampling resistor to obtain the paper detection parameter.

[0144] As an optional implementation manner, the first power supply I1 includes a first controllable current source;

[0145] The first controllable current source is used to control the intensity of the optical signal emitted by the light-emitting diode.

[0146] As an alternative embodiment, the second power supply I2 includes a second controllable current source;

[0147] The second controllable current source is used to control the conduction current of the light-receiving tube.

[0148] The operating current ranges of the light-emitting tubes and light-detecting tubes of different printing modules or different printing papers are different. In some embodiments, adjustment is achieved by changing the series resistors, which requires a large number of IO interfaces and has a limited electrical adjustment range. In this application, the current magnitude is directly adjusted by a variable current source, simplifying the adjustment process and providing a larger adjustment range.

[0149] As an alternative embodiment, the paper detection circuit includes an amplifier circuit, which can be used to obtain paper detection parameters according to the output of the amplifier circuit;

[0150] The input end of the amplifier circuit is connected to the connection point of the sampling resistor and the light-receiving tube, and is used to collect the voltage across the sampling resistor and output paper detection parameters according to the voltage across the sampling resistor. The paper detection parameters are used to indicate the printable position of the paper for the printing module.

[0151] Wherein, the amplifier circuit includes: a first resistor R1, a second resistor R2, a third resistor R3, an integrated operational amplifier A1, and an analog-to-digital converter;

[0152] The first end of the sampling resistor connected to the light-receiving tube is connected to the non-inverting input end of the integrated operational amplifier through the first resistor R1;

[0153] The inverting input end of the integrated operational amplifier is connected to the output end of the integrated operational amplifier A1 through the second resistor R2;

[0154] The inverting input end of the integrated operational amplifier A1 is also connected to the ground voltage through the third resistor;

[0155] The output end of the integrated operational amplifier A1 is connected to the analog-to-digital converter;

[0156] Wherein, the analog-to-digital converter outputs paper detection parameters.

[0157] Through the detection and amplification of the sampling resistor by the amplifier circuit, a smaller sampling resistor can be used in the circuit, making the voltage division of the sampling resistor smaller, avoiding frequent replacement of resistors to enable the light-receiving tube to operate in the amplification region, improving the signal quality, and reducing device losses.

[0158] Embodiment 2

[0159] Please refer to Figure 13 , Figure 13 which is a schematic structural diagram of a microprocessing chip disclosed in an embodiment of the present application. As shown inFigure 13 As shown, the chip includes a thermal printing circuit as in any of the embodiments.

[0160] The circuit provided by any embodiment of the present application can be applied to a processing chip, and the chip can be a microcontroller unit (MCU), digital signal processor (DSP), microprocessor unit (MPU), micro central control chip, system-on-chip (SoC), thermal printing chip, etc. that can process digital signals, analog signals, or perform signal control functions, instruction processing, and arithmetic operations.

[0161] After considering the specification and practicing the technical solutions disclosed herein, those skilled in the art will readily conceive of other embodiments of the present application. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0162] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A thermal printing circuit, characterized in that: The circuit comprises: Input modules, logic modules and output modules; Wherein, the input module is connected to the input end of the logic module, the output end of the logic module is connected to the output module; the output module is connected to the printing module; Furthermore, the logic module is used to perform logic operations according to the image signal input by the input module to obtain a heating state signal; and the output module is used to output the heating state signal; The printing module is used to heat the thermistor corresponding to the target pixel point according to the heating state signal, and perform a printing operation according to each pixel point in the pixel image; The circuit also includes a storage module, a selection module and a configuration module; Wherein, the storage module is connected to the input module through the selection module, and the configuration module is connected to the selection module and the logic module; The storage module is used to store a pixel image of an original image, wherein the pixel image includes a plurality of pixel points, and the pixel state of the pixel point is used to indicate the printing status of the pixel point, including a printing status or an empty status; The input module includes a first input terminal and a second input terminal, the first input terminal is used to input a first pixel state signal corresponding to a target pixel point, and the second input terminal is one or more and is used to input a second pixel state signal of a reference pixel point corresponding to the target pixel point; The configuration module is used to provide a configuration signal, the logic module is used to determine a logic circuit according to the configuration signal, and the selection module is used to transmit a first pixel state signal and a second pixel state signal to an input module according to the configuration signal.

2. The circuit according to claim 1, characterized in that The heating state signal includes a first heating state signal and a second heating state signal; The first heating state signal is used to indicate a first heating degree of the thermistor corresponding to the target pixel point, and the second heating state signal is used to indicate a second heating degree of the thermistor corresponding to the target pixel point; The first heating level and the second heating level may be additive.

3. The circuit according to claim 2, characterized in that The first logic circuit in the logic module includes a first logic unit and a second logic unit, the first logic unit includes a signal holder, and the second logic unit includes a first NOT gate and a first AND gate; The input end of the signal holder is connected to the first input end, and the output end of the signal holder serves as the output end of the first logic unit; the input end of the first NOT gate is connected to the second input end, the input end of the first AND gate is connected to the output end of the first NOT gate and the first input end, and the output end of the first AND gate serves as the output end of the second logic unit; Furthermore, the first pixel status signal is used to indicate the status signal of the target pixel point, and the second pixel status signal is used to indicate the status signal of the first pixel point in the same column and row above the target pixel point; the first logic unit is used to generate a first heating status signal with the same level as the first pixel status signal according to the first pixel status signal; and the second logic unit is used to generate a second heating status signal according to the first pixel status signal and the second pixel status signal.

4. The circuit according to claim 3, characterized in that The second logic circuit in the logic module further includes a third logic unit, and the third logic unit includes a first OR gate, a second AND gate, a second NOT gate and a third NOT gate; The second pixel state signal includes a first sub-signal, a second sub-signal and a third sub-signal, wherein the first sub-signal is used to indicate a state signal of a first pixel in a row and a column above the target pixel, the second sub-signal is used to indicate a state signal of a second pixel adjacent to the left side of the first pixel, and the third sub-signal corresponds to a state signal of a third pixel adjacent to the right side of the first pixel; The input ends of the second NOT gate and the third NOT gate are connected to the second input end, the second NOT gate is used to invert the second sub-signal, the third NOT gate is used to invert the third sub-signal, the input end of the first OR gate is connected to the output end of the second NOT gate and the output end of the third NOT gate, the input end of the second AND gate is connected to the first input end and the output end of the first OR gate, and the output end of the second AND gate serves as the output end of the third logic unit; Furthermore, the second heating state signal includes a first sub-state signal and a second sub-state signal, the output end of the first AND gate is used to output the first sub-state signal, and the output end of the second AND gate is used to output the second sub-state signal.

5. The circuit according to claim 2, characterized in that The third logic circuit in the logic module includes a first logic unit, a second logic unit, a fourth logic unit and a fifth logic unit; The fourth logic unit includes a fourth NOT gate, a second OR gate and a third AND gate; the fifth logic unit includes a fifth NOT gate, a sixth NOT gate and a fourth AND gate; The second pixel status signal includes a first sub-signal and a fourth sub-signal, the first sub-signal is used to indicate the status signal of a first pixel in the same column and a row above the target pixel, and the fourth sub-signal is used to indicate the status signal of a fourth pixel in the same column and a row below the target pixel; The input end of the fourth NOT gate is connected to the second input end, and is used to invert the first sub-signal; the input end of the second OR gate is connected to the second input end and the output end of the fourth NOT gate, and is used to perform an OR logic operation on the inverted signal of the first sub-signal and the fourth sub-signal; the input end of the third AND gate is connected to the first input end and the output end of the second OR gate, and the output end of the third AND gate serves as the output end of the fourth logic unit; The input end of the fifth NOT gate is connected to the first input end, the input end of the sixth NOT gate is connected to the second input end, the fifth NOT gate is used to invert the first pixel state signal, the sixth NOT gate is used to invert the first sub-signal, the input end of the fourth AND gate is connected to the second input end, the output end of the fifth NOT gate and the output end of the sixth NOT gate, and is used to perform an AND logic operation on the fourth sub-signal, the inverted signal of the first sub-signal and the inverted signal of the first pixel state signal, and the output end of the fourth AND gate serves as the output end of the fifth logic unit; Furthermore, the first logic unit is used to generate a first heating state signal with the same level as the first pixel state signal according to the first pixel state signal; the second heating state signal includes a second sub-state signal, a third sub-state signal and a fourth sub-state signal, the output end of the third AND gate is used to output the second sub-state signal, the output end of the first AND gate is used to output the third sub-state signal, and the output end of the fourth AND gate is used to output the fourth sub-state signal.

6. The circuit according to claim 2, characterized in that The fourth logic circuit in the logic module includes a first logic unit, a sixth logic unit, a seventh logic unit and an eighth logic unit, the first logic unit includes a signal holder, the sixth logic unit includes a seventh NOT gate, an eighth NOT gate, a fifth AND gate, a sixth AND gate, a third OR gate and a seventh AND gate, the seventh logic unit includes a ninth NOT gate, a tenth NOT gate, an eighth AND gate, a ninth AND gate, a fourth OR gate and a tenth AND gate, the eighth logic unit includes an eleventh NOT gate, a twelfth NOT gate, a thirteenth NOT gate, a fourteenth NOT gate, a fifteenth NOT gate, a fifth OR gate and an eleventh AND gate; The second pixel state signal includes a first sub-signal, a second sub-signal, a third sub-signal, a fourth sub-signal and a fifth sub-signal, wherein the first sub-signal is used to indicate a state signal of a first pixel in a row and a column above the target pixel, the second sub-signal is used to indicate a state signal of a second pixel adjacent to the left side of the first pixel, the third sub-signal corresponds to a state signal of a third pixel adjacent to the right side of the first pixel, the fourth sub-signal is used to indicate a state signal of a fourth pixel in a row and a column below the target pixel, and the fifth sub-signal is used to indicate a state signal of a fifth pixel in a row and a column above the first pixel; The input end of the seventh NOT gate is connected to the second input end, the input end of the eighth NOT gate is connected to the second input end, the seventh NOT gate is used to invert the first sub-signal, the eighth NOT gate is used to invert the fifth sub-signal, the fifth AND gate input end is connected to the output end of the seventh NOT gate and the output end of the eighth NOT gate, and is used to perform an AND logic operation on the inverted signal of the first sub-signal and the inverted signal of the fifth sub-signal, the sixth AND gate input end is connected to the output end of the seventh NOT gate and the second input end, and is used to perform an AND operation on the inverted signal of the first sub-signal and the fifth sub-signal, the third OR gate input end is connected to the output end of the fifth AND gate and the output end of the sixth AND gate, the input end of the seventh AND gate is connected to the output end of the third OR gate and the first input end, and the output end of the seventh AND gate serves as the output end of the sixth logic unit; The input end of the ninth NOT gate is connected to the second input end, the input end of the tenth NOT gate is connected to the second input end, the ninth NOT gate is used to invert the first sub-signal, the tenth NOT gate is used to invert the fifth sub-signal, the input end of the eighth AND gate is connected to the output end of the ninth NOT gate and the output end of the tenth NOT gate, and is used to perform an AND logic operation on the inverted signal of the first sub-signal and the inverted signal of the fifth sub-signal, the input end of the ninth AND gate is connected to the second input end and the output end of the tenth NOT gate, and is used to perform an AND logic operation on the inverted signal of the first sub-signal and the fifth sub-signal, the input end of the fourth OR gate is connected to the output end of the ninth AND gate and the output end of the tenth AND gate, the input end of the tenth AND gate is connected to the output end of the fourth OR gate and the first input end, and the output end of the tenth AND gate serves as the output end of the seventh logic unit; The input end of the eleventh NOT gate is connected to the first input end, the input end of the twelfth NOT gate is connected to the second input end, the input end of the thirteenth NOT gate is connected to the second input end, the input end of the fourteenth NOT gate is connected to the second input end, the input end of the fifteenth NOT gate is connected to the second input end, the eleventh NOT gate is used to invert the first pixel state signal, the twelfth NOT gate is used to invert the first sub-signal, the thirteenth NOT gate is used to invert the fifth sub-signal, the fourteenth NOT gate is used to invert the second sub-signal, the fifteenth NOT gate is used to invert the third sub-signal, the input end of the fifth OR gate is connected to the The output end of the fourteenth NOT gate and the output end of the fifteenth NOT gate are used to perform an OR logic operation on the inverse signal of the second sub-signal and the inverse signal of the third sub-signal. The input end of the eleventh AND gate is connected to the second input end, the output end of the eleventh NOT gate, the output end of the twelfth NOT gate, the output end of the thirteenth NOT gate and the output end of the fifth OR gate, and is used to perform an AND logic operation on the fourth sub-signal, the inverse signal of the first pixel state signal, the inverse signal of the first sub-signal, the inverse signal of the fifth sub-signal and the output signal of the fifth OR gate. The output end of the eleventh AND gate serves as the output end of the eighth logic unit. Furthermore, the first logic unit is used to generate a first heating state signal having the same level as the first pixel state signal according to the first pixel state signal; the second heating state signal includes a second sub-state signal, a third sub-state signal and a fourth sub-state signal, the output end of the seventh AND gate is used to output the second sub-state signal, the output end of the tenth AND gate is used to output the third sub-state signal, and the output end of the eleventh AND gate is used to output the fourth sub-state signal.

7. The circuit according to any one of claims 1 to 6, characterized in that: The output module includes a first clock pin, four FIFO registers and four data signal pins; The first clock pin is connected to the clock pin of the printing module and is used for data transmission clock synchronization; The four FIFO register input ends input the heating state signal in a preset time sequence, and the output ends are respectively connected to four data signal pins, and are used to output the heating state signal at the same time after the heating state signal input is completed; The four data signal pins are respectively connected to the four data pins of the printing module, and are used to output the heating status signal to the printing module.

8. The circuit according to claim 1, characterized in that The circuit also includes a paper detection circuit; The paper detection circuit comprises: A light emitting tube, the light emitting tube is connected to a first power source and is used to emit a light signal; A light receiving tube, wherein the light receiving tube and the sampling resistor are connected in series between the second power supply and the ground voltage, and the light receiving tube is used to generate a current change according to the intensity of the received light; An amplifier circuit, wherein the input end of the amplifier circuit is connected to the connection point of the sampling resistor and the light receiving tube, and is used to collect the voltage on both sides of the sampling resistor, and output a paper detection parameter according to the voltage on both sides of the sampling resistor, wherein the paper detection parameter is used to indicate the printable position of the paper of the printing module.

9. The circuit according to claim 8, characterized in that The amplifying circuit comprises: a first resistor, a second resistor, a third resistor, an integrated operational amplifier and an analog-to-digital converter; The first end of the first resistor is connected to the connection point of the sampling resistor and the light receiving tube as the input end of the amplifier circuit, and the other end of the first resistor is connected to the positive phase input end of the integrated operational amplifier; A first end of the second resistor is connected to an inverting input end of the integrated operational amplifier, and another end of the second resistor is connected to an output end of the integrated operational amplifier; A first end of the third resistor is connected to the inverting input end of the integrated operational amplifier and a first end of the second resistor, and the other end of the third resistor is connected to a ground voltage; The output end of the integrated operational amplifier is connected to the input end of the analog-to-digital converter; The output end of the analog-to-digital converter outputs paper detection parameters.

10. A chip, characterized in that: The thermal printing circuit comprises the thermal printing circuit according to any one of claims 1 to 9.

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