Surge protection circuit of charging box

Abstract

The utility model discloses a surge protection circuit of a charging box, which comprises at least one contact conduction circuit and a power management chip, the contact conduction circuit comprises two conductive contacts, a peak absorption circuit and a clamping circuit, the two conductive contacts are respectively a first contact and a second contact, the peak absorption circuit is connected with the clamping circuit, and the clamping circuit is connected with the peak absorption circuit. The first contact is connected with a voltage output port of the power management chip, the second contact is grounded, the peak absorption circuit is connected between the first contact and the second contact, the input end of the clamping circuit is connected with the first contact, and the output end of the clamping circuit is connected with a PMID pin of the power management chip. According to the surge protection circuit, surge impact is prevented by adopting an integrated scheme of the electrostatic diodes and the transient voltage suppression diodes, three layers of protection are arranged on the basis of not changing an original circuit, and the reliability of surge protection is improved.

Description

Technical Field

[0001] This application relates to the technical field of surge protection, and more specifically, to a surge protection circuit for a charging case. Background Art

[0002] Static electricity is formed when two substances with different dielectric constants are rubbed, and positive and negative charges are respectively accumulated on two objects. For example, static electricity is generated by rubbing between clothes and skin. Electrostatic discharge is a natural phenomenon with the characteristics of high voltage, low power, small current, and short action time. In the electronics industry, electrostatic discharge is a common and serious hazard source that causes component breakdown damage, including two forms: hard breakdown and soft breakdown. Hard breakdown will cause dielectric breakdown, burning, or permanent failure of components, while soft breakdown will cause deterioration of device performance or decline of parameter indicators. At the same time, electrostatic discharge may also cause overstress to the device, resulting in device damage or performance degradation. Therefore, in the process of electronic product design, the protection against electrostatic discharge is crucial.

[0003] In the prior art, there are already mature solutions for the electrostatic discharge protection of electronic devices, but most of these solutions are applied to the input end of electronic devices, while the solutions applied to the output end are relatively rare. Especially for some charging cases that use PogoPin interfaces for output, when hearing aids or Bluetooth headsets are taken and placed on such charging cases, high-voltage surge impacts are likely to occur. For some charging cases with chips having low withstand voltage, the surge impacts are likely to damage the chips of the charging case, resulting in the failure of the functions of the charging case. Currently, the electrostatic protection of electronic devices usually adopts an integrated solution of common-mode inductors and TVS. However, the production of common-mode inductors requires precise winding and magnetic cores, which results in a relatively high cost of common-mode inductors, and the common-mode inductors themselves will introduce certain losses and are likely to affect signal transmission. Summary of the Invention

[0004] The purpose of the present utility model is to provide a surge protection circuit for a charging case to solve the above-mentioned existing technical problems.

[0005] To achieve the above technical purpose, the technical solution adopted by the present utility model is: a surge protection circuit for a charging case, including at least one contact conduction circuit and a power management chip. The contact conduction circuit includes two conductive contacts, a spike absorption circuit, and a clamping circuit. The two conductive contacts are respectively a first contact and a second contact. The first contact is connected to the voltage output port of the power management chip, the second contact is grounded, the spike absorption circuit is connected between the first contact and the second contact, the input end of the clamping circuit is connected to the first contact, and the output end of the clamping circuit is connected to the PMID pin of the power management chip.

[0006] Furthermore, there are two contact conduction circuits.

[0007] Further, the spike absorption circuit is implemented by a transient voltage suppression diode TVS3. The transient voltage suppression diode TVS3 is connected between the first contact and the second contact, and the cathode of the transient voltage suppression diode TVS3 faces the first contact.

[0008] Further, the clamping circuit is implemented by a Schottky diode D2 and an electrostatic diode ESD2. The anode of the Schottky diode D2 is connected to the first contact, the cathode of the Schottky diode D2 is respectively connected to the PMID pin of the power management chip and the electrostatic diode ESD2, and the other end of the electrostatic diode ESD2 is grounded.

[0009] Further, a high-current voltage-regulating MOS transistor is integrated inside the PMID pin of the power management chip.

[0010] Further, the conductive contact is a PogoPin interface.

[0011] Further, a residual voltage peak absorption circuit is further included. The residual voltage peak absorption circuit is implemented by an electrostatic diode ESD4. One end of the electrostatic diode ESD4 is connected to the first contact, and the other end of the electrostatic diode ESD4 is grounded.

[0012] Furthermore, the voltage regulation value of the electrostatic diode ESD4 is 6.3V.

[0013] Further, a voltage regulation circuit is further included. The voltage regulation circuit is implemented by a capacitor C1, a capacitor C2, a capacitor C3, an inductor L1, and a low-dropout linear regulator U2. The inductor L1 is connected between the LX pin and the VSYS pin of the power management chip. The VSYS pin of the power management chip is connected to the VIN pin of the low-dropout linear regulator U2. A capacitor C1 and a capacitor C2 are respectively connected between the VSYS pin of the power management chip and the VIN pin of the low-dropout linear regulator U2, and the other ends of the capacitor C1 and the capacitor C2 are grounded. The GND pin of the low-dropout linear regulator U2 is grounded. The VOUT pin of the low-dropout linear regulator U2 is respectively connected to the positive power supply and the capacitor C3, and the other end of the capacitor C3 is grounded.

[0014] Further, a key anti-static circuit is further included. The key anti-static circuit is implemented by a Schottky diode D3 and an electrostatic diode ESD5. The cathode of the Schottky diode D3 is respectively connected to the IRQ pin of the power management chip and the electrostatic diode ESD5, the other end of the electrostatic diode ESD5 is grounded, and the anode of the Schottky diode D3 is connected to KEY.

[0015] The beneficial technical effects of the present utility model:

[0016] The present utility model adopts an integrated solution of an electrostatic diode and a transient voltage suppression diode to protect against surge impacts, without affecting the functions of the original circuit. Three-layer protection is set up without modifying the original circuit, improving the reliability of surge protection. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is the circuit diagram of the specific embodiment of the present utility model. Detailed Embodiments

[0019] To further illustrate the embodiments, the present utility model provides drawings. These drawings are part of the disclosure of the present utility model, mainly used to illustrate the embodiments, and can be used to explain the operating principles of the embodiments in conjunction with the relevant descriptions in the specification. With reference to these contents, those of ordinary skill in the art should be able to understand other possible implementation manners and the advantages of the present utility model. The components in the drawings are not drawn to scale, and similar component symbols are usually used to represent similar components.

[0020] The present utility model will be further described below in conjunction with the drawings and specific embodiments.

[0021] As Figure 1 shown, a surge protection circuit for a charging case includes a first contact conduction circuit, a second contact conduction circuit, and a power management chip. The first contact conduction circuit includes a first group of contacts, a first spike absorption circuit, and a first clamping circuit. The second contact conduction circuit includes a second group of contacts, a second spike absorption circuit, and a second clamping circuit. The first group of contacts includes contact TP8 and contact TP10, and the second group of contacts includes contact TP9 and contact TP11. Contact TP8, contact TP9, contact TP10, and contact TP11 are preferably implemented using the existing charging contacts of the charging case, with a simple structure and easy implementation.

[0022] Preferably, in other embodiments, there may also be one contact conduction circuit or three contact conduction circuits.

[0023] The contact TP8 is connected to the left ear voltage output port VOL of the power management chip, the contact TP10 is grounded, the contact TP9 is connected to the right ear voltage output port VOR of the power management chip, the contact TP11 is grounded, the first spike absorption circuit is connected between the contact TP8 and the contact TP10, the second spike absorption circuit is connected between the contact TP9 and the contact TP11, the input end of the first clamping circuit is connected to the contact TP8, the output end of the first clamping circuit is connected to the PMID pin of the power management chip, the input end of the second clamping circuit is connected to the contact TP9, and the output end of the second clamping circuit is connected to the PMID pin of the power management chip.

[0024] Preferably, in this specific embodiment, a power management chip with a high-current voltage-regulating MOS transistor integrated inside the PMID pin is used. For details, reference can be made to the prior art and will not be elaborated here.

[0025] In this specific embodiment, the first spike absorption circuit is implemented by the transient voltage suppression diode TVS3, and the second spike absorption circuit is implemented by the transient voltage suppression diode TVS4. The circuit structure is simple and easy to implement. However, this is not a limitation. In some embodiments, the first spike absorption circuit and the second spike absorption circuit can also be implemented by other circuits such as the RCD absorption circuit composed of resistors, capacitors, and diodes.

[0026] Specifically, the cathode of the transient voltage suppression diode TVS3 is connected to the contact TP8, the anode of the transient voltage suppression diode TVS3 is connected to the contact TP10, the cathode of the transient voltage suppression diode TVS4 is connected to the contact TP9, and the anode of the transient voltage suppression diode TVS4 is connected to the contact TP11.

[0027] In this specific embodiment, the first clamping circuit is implemented by the Schottky diode D2 and the electrostatic diode ESD2, and the second clamping circuit is implemented by the Schottky diode D1 and the electrostatic diode ESD2. It has high cost performance and good protection effect. However, this is not a limitation. In some embodiments, the first clamping circuit and the second clamping circuit can also be implemented by circuits such as the forward clamping circuit composed of capacitors, diodes, and resistors.

[0028] Specifically, the anode of the Schottky diode D2 is connected to the contact TP8, the cathode of the Schottky diode D2 is respectively connected to the electrostatic diode ESD2 and the PMID pin of the power management chip, the other end of the electrostatic diode ESD2 is grounded, the anode of the Schottky diode D1 is connected to the contact TP9, the cathode of the Schottky diode D1 is respectively connected to the electrostatic diode ESD2 and the PMID pin of the power management chip, and the other end of the electrostatic diode ESD2 is grounded.

[0029] Further, in this specific embodiment, a first residual voltage peak absorption circuit and a second residual voltage peak absorption circuit are further included. One end of the first residual voltage peak absorption circuit is connected to the contact point TP8, and the other end is grounded. One end of the second residual voltage peak absorption circuit is connected to the contact point TP9, and the other end is grounded. The circuit structure is simple, the cost is low, and the protection effect is good. However, this is not a limitation. In some embodiments, the first residual voltage peak absorption circuit and the second residual voltage peak absorption circuit can also be implemented by other circuits such as an absorption circuit composed of a zener diode and a fast recovery diode.

[0030] In this specific embodiment, the first residual voltage peak absorption circuit is implemented by the electrostatic diode ESD4, and the second residual voltage peak absorption circuit is implemented by the electrostatic diode ESD3. One end of the electrostatic diode ESD4 is connected to the contact point TP8, and the other end is grounded. One end of the electrostatic diode ESD3 is connected to the contact point TP9, and the other end is grounded.

[0031] Preferably, in this specific embodiment, the breakdown voltages of the electrostatic diode ESD3 and the electrostatic diode ESD4 are 6.3V.

[0032] Further, in this specific embodiment, a voltage stabilizing circuit is further included. One end of the voltage stabilizing circuit is connected to the LX pin and the VSYS pin of the power management chip, and the other end is connected to the positive power supply.

[0033] In this specific embodiment, the voltage stabilizing circuit is implemented by an inductor L1, capacitors C1, C2, C3, and a low dropout linear regulator U2. The inductor L1 is connected between the LX pin and the VSYS pin of the power management chip. The VIN pin of the low dropout linear regulator U2 is connected to the VSYS pin of the power management chip. Capacitors C1 and C2 are respectively connected between the VIN pin of the low dropout linear regulator U2 and the VSYS pin of the power management chip, and the other ends of capacitors C1 and C2 are grounded. The GND pin of the low dropout linear regulator U2 is grounded. The VOUT pin of the low dropout linear regulator U2 is respectively connected to capacitor C3 and the positive power supply, and the other end of capacitor C3 is grounded.

[0034] Preferably, in some embodiments, the voltage stabilizing circuit can also be implemented by other circuits such as a Zener voltage stabilizing circuit.

[0035] Preferably, in this specific embodiment, capacitors C1, C2, and C3 are all 10uF, and the inductor L1 is 3.3uH.

[0036] Further, in this specific embodiment, it further includes a key anti-static circuit. One end of the key anti-static circuit is connected to the IRQ pin of the power management chip, and the other end of the key anti-static circuit is connected to the key KEY.

[0037] In this specific embodiment, the key anti-static circuit is implemented by a Schottky diode D3 and an electrostatic diode ESD5. The cathode of the Schottky diode D3 is respectively connected to the IRQ pin of the power management chip and the electrostatic diode ESD5, and the other end of the electrostatic diode ESD5 is grounded. The anode of the Schottky diode D3 is connected to the key KEY.

[0038] Preferably, in some embodiments, the key anti-static circuit can also be implemented by other circuits such as a key anti-static circuit composed of an electrostatic diode and a resistor.

[0039] Working principle

[0040] When the hearing aid or earphone is taken out from or placed into the charging case, the two poles of the transient voltage suppression diode TVS3 and the transient voltage suppression diode TVS4 are subjected to a reverse transient high-energy impact, resulting in the high impedance between the two poles becoming a low impedance, absorbing the peak voltage. At this time, the voltage is still greater than 6V; the voltage is diverted to the electrostatic diode ESD2 through the Schottky diode D1 and the Schottky diode D2. The PN junction of the electrostatic diode ESD2 is reversely broken down, forming a very low-resistance path, allowing the overvoltage to flow into the ground, and then the remaining voltage is diverted to the PMID pin of the power management chip. The large-current voltage-stabilizing MOS transistor inside the PMID pin stabilizes the voltage within the withstand voltage range of the power management chip.

[0041] The present utility model adopts an integrated solution of an electrostatic diode and a transient voltage suppression diode to protect against surge impact, without affecting the functions of the original circuit. Three layers of protection are set without modifying the original circuit, improving the reliability of surge protection.

[0042] Although the present utility model is specifically shown and described in combination with the preferred implementation embodiments, those skilled in the art should understand that various changes can be made to the present utility model in terms of form and details without departing from the spirit and scope of the present utility model defined by the appended claims, and all of them fall within the protection scope of the present utility model.

Claims

1. A charging box surge protection circuit, characterized in that: It includes at least one contact conduction circuit and a power management chip, the contact conduction circuit includes two conductive contacts, a peak absorption circuit and a clamping circuit, the two conductive contacts are respectively a first contact and a second contact, the first contact is connected to the voltage output port of the power management chip, the second contact is grounded, the peak absorption circuit is connected between the first contact and the second contact, the input end of the clamping circuit is connected to the first contact, and the output end of the clamping circuit is connected to the PMID pin of the power management chip.

2. The charging box surge protection circuit according to claim 1, characterized in that: There are two contact conduction circuits.

3. The charging box surge protection circuit according to claim 1, characterized in that: The peak absorption circuit is implemented by a transient voltage suppression diode TVS3. The transient voltage suppression diode TVS3 is connected between the first contact and the second contact, and the cathode of the transient voltage suppression diode TVS3 faces the first contact.

4. The charging box surge protection circuit according to claim 1, characterized in that: The clamping circuit is implemented by a Schottky diode D2 and an electrostatic diode ESD2. The anode of the Schottky diode D2 is connected to the first contact, the cathode of the Schottky diode D2 is respectively connected to the PMID pin of the power management chip and the electrostatic diode ESD2, and the other end of the electrostatic diode ESD2 is grounded.

5. The charging box surge protection circuit according to claim 1, characterized in that: The PMID pin of the power management chip is internally integrated with a high-current voltage-stabilizing MOS tube.

6. The charging box surge protection circuit according to claim 1, characterized in that: The conductive contact is a PogoPin interface.

7. The charging box surge protection circuit according to claim 1, characterized in that: The residual voltage peak absorption circuit is also included. The residual voltage peak absorption circuit is implemented by an electrostatic diode ESD4. One end of the electrostatic diode ESD4 is connected to the first contact point, and the other end of the electrostatic diode ESD4 is grounded.

8. The charging box surge protection circuit according to claim 7, characterized in that: The voltage regulation value of the electrostatic diode ESD4 is 6.3V.

9. The charging box surge protection circuit according to claim 1, characterized in that: It also includes a voltage stabilizing circuit, which is implemented by a capacitor C1, a capacitor C2, a capacitor C3, an inductor L1 and a low-voltage difference linear regulator U2. The inductor L1 is connected between the LX pin and the VSYS pin of the power management chip, the VSYS pin of the power management chip is connected to the VIN pin of the low-voltage difference linear regulator U2, and the capacitors C1 and C2 are respectively connected between the VSYS pin of the power management chip and the VIN pin of the low-voltage difference linear regulator U2. The other ends of the capacitors C1 and C2 are grounded, the GND pin of the low-voltage difference linear regulator U2 is grounded, the VOUT pin of the low-voltage difference linear regulator U2 is respectively connected to the positive pole of the power supply and the capacitor C3, and the other end of the capacitor C3 is grounded.

10. The charging box surge protection circuit according to claim 1, characterized in that: It also includes a key anti-static circuit, which is implemented by a Schottky diode D3 and an electrostatic diode ESD5. The cathode of the Schottky diode D3 is connected to the IRQ pin of the power management chip and the electrostatic diode ESD5 respectively, the other end of the electrostatic diode ESD5 is grounded, and the anode of the Schottky diode D3 is connected to KEY.

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