Substrate structure for avoiding pollution of IDT area of filter chip

Abstract

The utility model discloses a substrate structure for avoiding pollution of an IDT area of a filter chip, which comprises a substrate coated with a solder resist ink layer on the surface and the filter chip mounted on the front surface of the substrate, the IDT area is arranged at the bottom of the filter chip, and a plurality of salient points are arranged around the IDT area; the front surface of the substrate is provided with a plurality of bonding pads corresponding to the bumps and a solder resist window, and the solder resist window is located at the position, corresponding to the IDT area, of the front surface of the substrate, so that a cavity is formed between the front surface of the substrate and the IDT area. According to the utility model, a solder resist ink layer, located below the IDT area at the bottom of the filter chip, on the front surface of the substrate is omitted, so that the volume of a cavity between the bottom of the chip and the front surface of the substrate is increased, and the problems of cavity disappearance and IDT area pollution caused by chip sinking after welding are avoided.

Description

Technical Field

[0001] The utility model belongs to the technical field of chip packaging, and particularly relates to a substrate structure for avoiding the pollution of the IDT area of a filter chip. Background Art

[0002] A surface acoustic wave filter (SAW Filter) is a kind of radio frequency chip made by using the piezoelectric effect of a piezoelectric substrate and the physical characteristics of surface wave propagation. As Figure 1 shown, its working principle is that at the input end, the electrical signal is converted into an acoustic signal through the inverse piezoelectric effect and propagates on the surface of the medium, and at the output end, the acoustic signal is converted into an electrical signal by the piezoelectric effect. The surface acoustic wave filter is composed of a piezoelectric substrate and interdigital transducers (IDT, Interdigital Transducer) on its surface. Among them, the piezoelectric material refers to a substrate that will generate charges on its two end faces under pressure; the interdigital transducer refers to the metal electrodes arranged crosswise on the piezoelectric substrate, which are divided into input and output transducers. The interdigital transducer can directly excite and receive surface acoustic waves. When an electrical signal is input at the input end, the electrical signal is converted into mechanical energy through the inverse piezoelectric effect of the piezoelectric substrate and propagates on the surface of the substrate in the form of surface acoustic waves; when the surface acoustic wave signal reaches the output transducer, it is then converted into an electrical signal output through the piezoelectric effect of the piezoelectric substrate, and functions such as filtering, delay, and sensing are realized through the frequency response and impulse response between the interdigital transducers.

[0003] The surface acoustic wave filter is a flip-chip, and there is an IDT area at the bottom of the chip. As Figure 2 、 Figure 4 and Figure 6 shown, in the conventional substrate design structure, first, a copper plate is laid on the surface of the substrate 100, then the copper plate is etched to form traces 103 and an etching area 106, and finally, a layer of solder mask ink is coated to protect the traces 103. Among them, as Figure 6 shown, the dark green part is the first solder mask ink layer 1011 on the surface of the traces 103, and the light green part is the second solder mask ink layer 1012 on the surface of the etching area 106, but they are solder mask inks of the same composition, and are only represented by different colors because the copper traces 103 or the substrate 100 exposed after etching are covered below. It can be seen from the figure that a solder mask ink is coated at the position corresponding to the IDT area 201 at the bottom of the filter chip 2 on the front surface of the substrate 1. When the filter chip 2 is mounted on the substrate 1, a certain distance needs to be left between the IDT area 201 at the bottom of the chip and the surface of the substrate 1 to form a cavity 3 to achieve the filtering function. The IDT area 201 is a sensitive area of the chip and cannot be contaminated. At the same time, as Figure 3 and Figure 5As shown in the figure, there are bumps 202 at the bottom of the chip for connecting to the pads 102 on the substrate 1. The main component of the bumps 202 is tin. During the soldering process, the solder balls will melt due to heat, resulting in a decrease in the height of the bumps 202, thereby causing the overall sinking of the chip, that is, the distance between the bottom of the chip and the surface of the substrate 1 decreases. The surface of the substrate 1 is a solder mask ink layer 101, and the thickness of the ink layer is generally 25 ± 10 μm. Due to the tolerance of the ink thickness, if the ink on the substrate 1 is too thick, the chip will sink during the soldering process, which may cause the bottom of the chip to contact the ink on the surface of the substrate 1, resulting in contamination of the IDT area 201 and the disappearance of the cavity 3, leading to a decline in the performance of the filter chip 2 or even failure. Summary of the Invention

[0004] Aiming at the above problems, the purpose of the present invention is to provide a substrate structure that can prevent the disappearance of the cavity between the filter chip and the substrate and avoid the contamination of the IDT area of the filter chip.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] The present invention provides a substrate structure for avoiding the contamination of the IDT area of the filter chip, including a substrate with a solder mask ink layer coated on the surface and a filter chip mounted on the front surface of the substrate. Among them, an IDT area is provided at the bottom of the filter chip, and a plurality of bumps are provided around the periphery of the IDT area; a plurality of pads corresponding to the bumps and a solder mask opening are provided on the front surface of the substrate, and the solder mask opening is located at a position corresponding to the IDT area, so as to form a cavity between the front surface of the substrate and the IDT area.

[0007] A preferred implementation manner, the substrate includes a base material and a copper plate laid on the surface of the base material. The copper plate is etched to form traces and etching areas, and the solder mask ink layer includes a first solder mask ink layer located on the surface of the traces and a second solder mask ink layer located on the surface of the etching areas.

[0008] A preferred implementation manner, the area of the solder mask opening is larger than the area of the IDT area and smaller than the area of the filter chip.

[0009] A preferred implementation manner, the edge of the solder mask opening is located at the center connection line of the pads, and a first solder mask ink layer is reserved around the pads falling within the solder mask opening, and a second solder mask ink layer with a corresponding arc length is coated on the etching area outside the first solder mask ink layer, so that the shortest distance from the edge of the pad to the solder mask opening area is greater than the preset distance defined by the process.

[0010] A preferred implementation manner, the pad is an exposed copper surface formed by windowing at a position corresponding to the bump on the substrate, and a gold layer is plated on the exposed copper surface or an organic solderability protective layer is covered.

[0011] A preferred embodiment is that the bumps are solder balls.

[0012] A preferred embodiment is that solder paste or flux is printed on the pads corresponding to the bumps of the filter chip on the front side of the substrate.

[0013] A preferred embodiment is that vias are formed in the pads, the vias are filled with a conductive medium, traces are provided on the back side of the substrate, and the pads are electrically connected to the traces on the back side of the substrate through the vias.

[0014] A preferred embodiment is that the thickness of the solder mask ink layer is 25 ± 10 μm.

[0015] A preferred embodiment is that the filter chip is a flip chip, and at least includes a surface acoustic wave filter chip.

[0016] The utility model has the following beneficial effects:

[0017] The utility model adjusts the design structure of the solder mask ink layer on the front side of the substrate, opens a window in the solder mask ink layer below the chip IDT area, so as to increase the volume of the cavity between the chip and the substrate, prevent the problems of chip sinking and the reduction or disappearance of the cavity volume caused by the thickening of the solder mask ink layer, and avoid the contamination of the chip IDT area by contacting the solder mask ink. At the same time, the solder mask ink around the pads of the substrate is retained to prevent poor soldering caused by the flow of solder paste or flux. In addition, due to the increase in the solder mask opening, the usage amount of the solder mask ink is reduced, and the production cost of the substrate is reduced. Description of the Drawings

[0018] Figure 1 is the working principle diagram of the surface acoustic wave filter;

[0019] Figure 2 is the schematic structural diagram (before soldering) of the filter chip mounted on the front side of the substrate in the prior art;

[0020] Figure 3 is the schematic structural diagram (after soldering) of the filter chip mounted on the front side of the substrate in the prior art;

[0021] Figure 4 is the partial enlarged schematic structural diagram (before soldering) of the filter chip mounted on the front side of the substrate in the prior art;

[0022] Figure 5 is the partial enlarged schematic structural diagram (after soldering) of the filter chip mounted on the front side of the substrate in the prior art;

[0023] Figure 6 is the top view of the substrate structure in the prior art;

[0024] Figure 7 It is a top view of the substrate structure in this embodiment;

[0025] Figure 8 It is a schematic structural diagram (before soldering) of the filter chip mounted on the front side of the substrate in this embodiment;

[0026] Figure 9 It is a schematic structural diagram (after soldering) of the filter chip mounted on the front side of the substrate in this embodiment;

[0027] Figure 10 It is a partially enlarged schematic structural diagram (before soldering) of the filter chip mounted on the front side of the substrate in this embodiment;

[0028] Figure 11 It is a partially enlarged schematic structural diagram (after soldering) of the filter chip mounted on the front side of the substrate in this embodiment.

[0029] In the figure: 1. Substrate; 100. Substrate material; 101. Solder mask layer; 1011. First solder mask layer; 1012. Second solder mask layer; 102. Pad; 103. Trace; 104. Via; 105. Solder mask opening; 106. Etching area; 2. Filter chip; 201. IDT area; 202. Bump; 3. Cavity. Detailed implementation manners

[0030] In order to make the objectives, technical solutions and advantages of the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0031] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present utility model; relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0032] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, an integral connection, or a detachable connection; it can be the communication inside two components; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.

[0033] As Figures 7 - 11 shown, an embodiment of the present utility model discloses a substrate structure for avoiding the contamination of the IDT area of a filter chip, including a substrate 1 with a solder mask ink layer 101 coated on its surface and a filter chip 2 mounted on the front surface of the substrate 1. Among them, an IDT area 201 is provided at the bottom of the filter chip 2, and a plurality of bumps 202 are provided around the IDT area 201 at the bottom of the filter chip 2; a plurality of pads 102 corresponding to the bumps 202 and a solder mask opening 105 are provided on the front surface of the substrate 1, and the solder mask opening 105 is located at a position corresponding to the IDT area 201 on the front surface of the substrate 1, so as to form a cavity 3 between the front surface of the substrate 1 and the IDT area 201 of the filter chip 2.

[0034] Specifically, the substrate 1 includes a base material 100, a copper plate is laid on the surface of the base material 100, and the copper plate is etched to form traces 103 and an etching area 106, and then a solder mask ink layer 101 is coated on the surface to protect the traces 103. It should be understood that for the convenience of distinction, as Figure 7 shown, the solder mask ink layer 101 coated on the surface of the trace 103 is named as the first solder mask ink layer 1011, and the solder mask ink layer 101 coated on the surface of the etching area 106 is named as the second solder mask ink layer 1012. The two are collectively referred to as the solder mask ink layer 101 and contain the same component of solder mask ink.

[0035] It should be noted that in this embodiment, the bumps 202 at the bottom of the filter chip 2 are solder balls mainly composed of tin, which are used to be soldered to the corresponding pads 102 on the front surface of the substrate 1 to form an electrical connection between the filter chip 2 and the substrate 1. It can also be metal balls of other materials, such as gold, silver, copper, cobalt, etc. The pads 102 are formed by opening a window in the area corresponding to the bumps 202 on the substrate 1 to form an exposed copper surface, and then a gold plating process is performed on the exposed copper surface or an organic solderability preservative (OSP) is covered. The main purpose is to prevent the oxidation of the copper surface from affecting the soldering. Among them, the surface gold plating includes nickel-palladium-gold plating or nickel-gold plating. For the pads 102 corresponding to the flip chip, the OSP surface treatment process is preferably used. Further, solder paste or flux is printed on the pads 102, which can further improve the quality and reliability of the soldering and ensure a good electrical connection between the filter chip 2 and the substrate 1. It should be noted that flux is preferably printed on the pads 102 corresponding to the flip chip. AsFigure 7 As shown, in this embodiment, the number of pads 102 corresponding to the bumps 202 is six, and the shape is circular. They are distributed along the circumference direction of the filter chip 2 and are arranged in three parallel rows, with two in each row. It should be noted that the number and shape of the pads 102 can be set as required and are not limited herein.

[0036] It is worth noting that during the soldering process, the solder balls will melt due to heat, resulting in a decrease in the height of the bumps 202, thereby causing the overall sinking of the filter chip 2, that is, the volume of the cavity 3 between the bottom of the filter chip 2 and the front surface of the substrate 1 decreases. As Figure 7 、 Figure 8 and Figure 10 shown, in this embodiment, a solder mask opening 105 is provided at a position corresponding to the IDT region 201 at the bottom of the filter chip 2 on the front surface of the substrate 1. Among them, the area of the solder mask opening 105 is larger than the area of the IDT region 201 and smaller than the area of the filter chip 2, that is, the solder mask ink layer 101 below the IDT region 201 at the bottom of the chip is cancelled, thereby increasing the volume of the cavity 3 between the bottom of the chip and the front surface of the substrate 1. In this way, during the soldering process, as Figure 9 and Figure 11 shown, even if the solder balls of the bumps 202 melt due to heat and the height decreases, a cavity 3 still remains between the IDT region 201 and the front surface of the substrate 1 after soldering and will not be contaminated by the solder mask ink layer 101. Preferably, the edge of the solder mask opening 105 is located at the center connection line of the pads 102, and a first solder mask ink layer 1011 is reserved around the pads 102 falling within the solder mask opening 105, and a second solder mask ink layer 1012 with a corresponding arc length is coated on the etching area 106 outside the first solder mask ink layer 1011. The reason is that the surface of the soldering part of the pads 102 is printed with solder paste or flux. In order to prevent the solder paste or flux from flowing and causing poor soldering, the shortest distance from the edge of the pads 102 to the edge of the solder mask ink layer 101 surrounding the pads 102 must be greater than the preset distance defined by the process. In this embodiment, in order to meet the above standard, a certain thickness of the second solder mask ink layer 1012 is reserved on the etching area 106 around the pads 102 falling within the solder mask opening 105, so that the shortest distance from the edge of the pads 102 to the solder mask opening 105 area is greater than the preset distance defined by the process.

[0037] Furthermore, as Figures 7 - 11As shown, in this embodiment, a copper trace 103 is led out from the pad 102. Electrical connections are formed between adjacent pads 102 through the traces 103, and a first solder mask ink layer 1011 is coated on the surface of the traces 103. Surrounding the pads 102 and the traces 103 is the etching area 106, and a second solder mask ink layer 1012 is coated on the surface of the etching area 106. It should be understood that in some embodiments, the pad 102 may not lead out the trace 103, and there may be no electrical connection between the pads 102.

[0038] Furthermore, in this embodiment, a via 104 is also formed in the pad 102. Traces 103 are also provided on the back surface of the substrate 1. The via 104 is filled with a conductive medium to electrically connect the pad 102 to the trace 103 located on the back surface of the substrate 1. It should be understood that in some embodiments, the substrate 1 includes multiple layers of traces 103, such as 4, 6, 8 layers, etc. The traces 103 on different layers are electrically connected through the vias 104, and the traces 103 on the back surface of the substrate 1 are electrically connected to the pins. In this way, the filter chip 2 is first connected to the pad 102 on the front surface of the substrate 1 through the bumps 202, and then the pad 102 on the front surface of the substrate 1 is finally electrically connected to the pins on the back surface of the substrate 1 through the layers of traces 103. Preferably, in this embodiment, the conductive medium in the via 104 is copper and is filled in the via 104 by electroplating.

[0039] It should be understood that in this embodiment, the thickness of the solder mask ink layer 101 is 25 ± 10 μm, which is the conventional ink thickness of a general substrate 1. It can also be thinned or thickened according to actual needs. The filter chip 2 is a surface acoustic wave filter chip with an IDT area 201 at the bottom, which is a flip chip. The structure of the present invention is also applicable to other chips whose bottom areas cannot be contaminated by the solder mask ink layer 101.

Claims

1. A substrate structure for avoiding contamination of the IDT region of a filter chip, characterized in that: The invention comprises a substrate (1) having a solder resist ink layer (101) coated on its surface, and a filter chip (2) mounted on the front side of the substrate (1), wherein an IDT region (201) is provided at the bottom of the filter chip (2), and a plurality of bumps (202) are provided around the IDT region (201); a plurality of pads (102) corresponding to the bumps (202) and a solder resist window (105) are provided on the front side of the substrate (1), and the solder resist window (105) is located at a position corresponding to the IDT region (201), so that a cavity (3) is formed between the front side of the substrate (1) and the IDT region (201).

2. The substrate structure according to claim 1, characterized in that: The substrate (1) comprises a base material (100) and a copper plate laid on the surface of the base material (100); the copper plate is etched to form a trace (103) and an etching area (106); the solder resist ink layer (101) comprises a first solder resist ink layer (1011) located on the surface of the trace (103) and a second solder resist ink layer (1012) located on the surface of the etching area (106).

3. The substrate structure according to claim 2, characterized in that: The area of ​​the solder resist opening (105) is larger than the area of ​​the IDT region (201) and smaller than the area of ​​the filter chip (2).

4. The substrate structure according to claim 3, characterized in that: The edge of the solder resist window (105) is located at the center line of the pad (102), and a first solder resist ink layer (1011) is retained around the pad (102) within the solder resist window (105), and a second solder resist ink layer (1012) with a corresponding arc length is coated on the etched area (106) outside the first solder resist ink layer (1011), so that the shortest distance from the edge of the pad (102) to the solder resist window (105) area is greater than a preset distance specified by the process.

5. The substrate structure according to claim 1, characterized in that: The pad (102) is an exposed copper surface formed by window opening at a position on the substrate (1) corresponding to the convex point (202), and the exposed copper surface is plated with a gold layer or covered with an organic solderability protective layer.

6. The substrate structure according to claim 1, characterized in that: The bumps (202) are solder balls.

7. The substrate structure according to claim 1, characterized in that: Solder paste or soldering flux is printed on the solder pad (102) on the front side of the substrate (1) corresponding to the bump (202) of the filter chip (2).

8. The substrate structure according to claim 1, characterized in that: A via (104) is provided on the pad (102), the via (104) is filled with a conductive medium, a trace (103) is provided on the back of the substrate (1), and the pad (102) is electrically connected to the trace (103) located on the back of the substrate (1) through the via (104).

9. The substrate structure according to claim 1, characterized in that: The thickness of the solder resist ink layer (101) is 25±10 μm.

10. The substrate structure according to claim 1, characterized in that: The filter chip (2) is a flip chip and at least comprises a surface acoustic wave filter chip.

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