High-low voltage sampling circuit for detecting voltage at two ends of synchronous rectification to input voltage

Abstract

The utility model discloses a high and low voltage sampling circuit for detecting voltages at two ends of synchronous rectification to input the voltages, a pin 19 of a sampling chip IC1 is used as a sampling pin, the pin can collect divided voltages of a resistor R15 and a resistor R18, and an input voltage value of an input end is judged through the voltage of a voltage node VD-1. When it is detected that the VD-1 of the ADC sampling node is smaller than 1.4 V, the input is judged to be low voltage, at the moment, 20 W is output, when it is detected that the VD-1 of the ADC sampling node is larger than 1.4 V, the input is judged to be high voltage, at the moment, 30 W is output, and high-voltage input detection and low-voltage input detection are distinguished by detecting the peak value of the secondary MOSFET.

Description

Technical Field

[0001] The utility model belongs to the technical field of circuit design, and particularly relates to a high and low voltage sampling circuit for input by detecting the voltage at both ends of synchronous rectification. Background Art

[0002] At present, the power bank is a two-in-one power bank. The power bank can be directly connected to alternating current and then charge the battery of the power bank. When there is no alternating current in the usage scenario, the battery inside the power bank provides energy for the Type-C to meet the output. Due to the limited volume of the product and the desire to increase the power of the power bank, generally when the product has a low voltage input of 100V - 125V, the Type-C outputs 20W, and when the product has a low voltage input of 200V - 240V, the Type-C outputs 30W. Currently, on the market, optocouplers are generally used for power switching. The disadvantages of this are that the components increase, the product volume increases, and the input no-load power consumption is large. Content of the Utility Model

[0003] The purpose of the utility model is to provide a high and low voltage sampling circuit for input by detecting the voltage at both ends of synchronous rectification to solve the problems raised in the above background art.

[0004] To achieve the above purpose, the utility model provides the following technical solution: A high and low voltage sampling circuit for input by detecting the voltage at both ends of synchronous rectification, including a transformer T1, a synchronous rectification chip U1, an ADC sampling chip IC1, and a monitoring point potential VD-1. The 1st pin of the synchronous rectification chip U1 is connected to the right end of a capacitor C6, the lower end of a capacitor C4, the lower end of a capacitor C2, and a ground wire GND1. The 2nd pin of the synchronous rectification chip U1 is connected to the right end of the capacitor C6, the lower end of the capacitor C4, the lower end of the capacitor C2, and the ground wire GND1. The 3rd pin of the synchronous rectification chip U1 is connected to the upper end of a resistor R8. The lower end of the resistor R8 is connected to the right end of the capacitor C6, the lower end of the capacitor C4, the lower end of the capacitor C2, and the ground wire GND1. The 4th pin of the synchronous rectification chip U1 is connected to the upper end of the capacitor C4. The lower end of the capacitor C4 is connected to the right end of the capacitor C6, the lower end of the capacitor C2, and the ground wire GND1. The 5th, 6th, 7th, and 8th pins of the synchronous rectification chip U1 are all connected to the B end of the transformer T1, the upper end of a resistor R15, and the left end of a resistor R10. The right end of the resistor R10 is connected to the left end of the capacitor C6. The A end of the transformer T1 is connected to the upper end of the capacitor C2. The resistor R15 is connected to the upper end of a capacitor C51, the upper end of a resistor R18, and the 19th pin of the ADC sampling chip IC1. The 19th pin of the sampling chip IC1 is provided with the monitoring point potential VD-1. The lower end of the capacitor C51 is connected to the lower end of the resistor R18 and the ground wire GND2. The lower end of the resistor R18 is connected to the lower end of the capacitor C51 and the ground wire GND2;

[0005] The right end of resistor R38 is connected to pin 1 of the ADC sampling chip IC1, the right end of resistor R53 is connected to pin 2 of the ADC sampling chip IC1, the right end of capacitor C40 is connected to pin 3 of the ADC sampling chip IC1, the right end of capacitor C41 is connected to pin 4 of the ADC sampling chip IC1, the right end of capacitor C43 is connected to pin 5 of the ADC sampling chip IC1, the right end of capacitor C44 is connected to pin 6 of the ADC sampling chip IC1. The left end of resistor R38 is connected to the left ends of resistor R53, capacitor C40, capacitor C41, capacitor C43, capacitor C44 and ground wire GND3. The left end of resistor R53 is connected to the left ends of resistor R38, capacitor C40, capacitor C41, capacitor C43, capacitor C44 and ground wire GND3. The left end of capacitor C40 is connected to the left ends of resistor R38, resistor R53, capacitor C41, capacitor C43, capacitor C44 and ground wire GND3. The left end of capacitor C41 is connected to the left ends of resistor R38, resistor R53, capacitor C40, capacitor C43, capacitor C44 and ground wire GND3. The left end of capacitor C43 is connected to the left ends of resistor R38, resistor R53, capacitor C40, capacitor C41, capacitor C44 and ground wire GND3. The left end of capacitor C44 is connected to the left ends of resistor R38, resistor R53, capacitor C40, capacitor C43, capacitor C41 and ground wire GND3;

[0006] Pin 20 of the ADC sampling chip IC1 is connected to network DPC, pin 21 of the ADC sampling chip IC1 is connected to network DMC, pin 22 of the ADC sampling chip IC1 is connected to network CC1 and the upper end of capacitor C35. The lower end of capacitor C35 is connected to ground wire GND5. Pin 23 of the ADC sampling chip IC1 is connected to network CC2 and the upper end of capacitor C37. The lower end of capacitor C37 is connected to ground wire GND4. The peak voltage of the MOSFET internally co-packaged in the synchronous rectification chip U1 is 49.23V. The resistance value of resistor R15 is 82KΩ, and the resistance value of resistor R18 is 2.4KΩ.

[0007] Technical effects and advantages of the present utility model: By using pin 19 of the sampling chip IC1 as the sampling pin, this pin will collect the divided voltage of resistor R15 and resistor R18. The input voltage value of the input end is determined by the voltage of this voltage node VD-1. When it is detected that the ADC sampling node VD-1 is less than 1.4V, it is determined that the input is a low voltage, and at this time, 20W is output. When it is detected that the ADC sampling node VD-1 is greater than 1.4V, it is determined that the input is a high voltage, and at this time, 30W is output. The detection of high and low voltage inputs is realized by detecting the peak value of the secondary MOSFET. This can reduce the internal components of the power bank, reduce the product volume, and reduce the no-load power consumption of the input. Brief Description of the Drawings

[0008] Figure 1 This is the MOSFET peak voltage dividing part of the circuit diagram of the present utility model;

[0009] Figure 2 This is the ADC sampling part of the circuit diagram of the present utility model.

[0010] Reference Numerals in the Drawings: Transformer T1, synchronous rectification chip U1, resistors R8, R10, R15, R18, R38, R53, capacitors C2, C4, C6, C35, C37, C40, C41, C43, C44, C51, monitoring point potential VD-1, ADC sampling chip IC1, network CC1, network CC2, network DMC, network DPC, ground wires GND1, 2, 3, 4, 5. Detailed Embodiment

[0011] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0012] The present utility model provides as Figure 1-2A high and low voltage sampling circuit that detects the voltage across a synchronous rectifier, including a transformer T1, a synchronous rectifier chip U1, an ADC sampling chip IC1, and a monitoring point potential VD-1. The 1st pin of the synchronous rectifier chip U1 is connected to the right end of capacitor C6, the lower end of capacitor C4, the lower end of capacitor C2, and the ground wire GND1. The 2nd pin of the synchronous rectifier chip U1 is connected to the right end of capacitor C6, the lower end of capacitor C4, the lower end of capacitor C2, and the ground wire GND1. The 3rd pin of the synchronous rectifier chip U1 is connected to the upper end of resistor R8. The lower end of resistor R8 is connected to the right end of capacitor C6, the lower end of capacitor C4, the lower end of capacitor C2, and the ground wire GND1. The 4th pin of the synchronous rectifier chip U1 is connected to the upper end of capacitor C4. The lower end of capacitor C4 is connected to the right end of capacitor C6, the lower end of capacitor C2, and the ground wire GND1. The 5th, 6th, 7th, and 8th pins of the synchronous rectifier chip U1 are all connected to the B end of the transformer T1, the upper end of resistor R15, and the left end of resistor R10. The right end of resistor R10 is connected to the left end of capacitor C6. The A end of the transformer T1 is connected to the upper end of capacitor C2. The resistor R15 is connected to the upper end of capacitor C51, the upper end of resistor R18, and the 19th pin of the ADC sampling chip IC1. The 19th pin of the sampling chip IC1 is provided with the monitoring point potential VD-1. The lower end of capacitor C51 is connected to the lower end of resistor R18 and the ground wire GND2. The lower end of resistor R18 is connected to the lower end of capacitor C51 and the ground wire GND2;

[0013] The right end of resistor R38 is connected to pin 1 of the ADC sampling chip IC1, the right end of resistor R53 is connected to pin 2 of the ADC sampling chip IC1, the right end of capacitor C40 is connected to pin 3 of the ADC sampling chip IC1, the right end of capacitor C41 is connected to pin 4 of the ADC sampling chip IC1, the right end of capacitor C43 is connected to pin 5 of the ADC sampling chip IC1, the right end of capacitor C44 is connected to pin 6 of the ADC sampling chip IC1. The left end of resistor R38 is connected to the left ends of resistor R53, capacitor C40, capacitor C41, capacitor C43, capacitor C44 and ground wire GND3. The left end of resistor R53 is connected to the left ends of resistor R38, capacitor C40, capacitor C41, capacitor C43, capacitor C44 and ground wire GND3. The left end of capacitor C40 is connected to the left ends of resistor R38, resistor R53, capacitor C41, capacitor C43, capacitor C44 and ground wire GND3. The left end of capacitor C41 is connected to the left ends of resistor R38, resistor R53, capacitor C40, capacitor C43, capacitor C44 and ground wire GND3. The left end of capacitor C43 is connected to the left ends of resistor R38, resistor R53, capacitor C40, capacitor C41, capacitor C44 and ground wire GND3. The left end of capacitor C44 is connected to the left ends of resistor R38, resistor R53, capacitor C40, capacitor C43, capacitor C41 and ground wire GND3;

[0014] Pin 20 of the ADC sampling chip IC1 is connected to network DPC, pin 21 of the ADC sampling chip IC1 is connected to network DMC, pin 22 of the ADC sampling chip IC1 is connected to network CC1 and the upper end of capacitor C35. The lower end of capacitor C35 is connected to ground wire GND5. Pin 23 of the ADC sampling chip IC1 is connected to network CC2 and the upper end of capacitor C37. The lower end of capacitor C37 is connected to ground wire GND4. The peak voltage of the MOSFET co-packaged inside the synchronous rectification chip U1 is 49.23V. The resistance value of resistor R15 is 82KΩ, and the resistance value of resistor R18 is 2.4KΩ.

[0015] Working principle:

[0016] By detecting the peak voltage of the internally integrated MOSFET in the synchronous rectification chip U1 at the secondary side of the transformer T1, the peak voltage of the MOSFET is across the two ends of pins 5, 6, 7, 8 and pins 1, 2 of the synchronous rectification chip U1. Since our synchronous rectification design rectifies at the ground terminal GND, we only need to detect the peak voltage of the MOSFET. Because the voltage withstand of the ADC sampling chip IC1 is insufficient, two resistors are used to divide the peak voltage of the internally integrated MOSFET in the synchronous rectification chip U1. Resistor R15 and resistor R18 are used, and a bypass capacitor C51 is used for filtering to make the collected signal clean and prevent clutter interference. The 19th pin of the ADC sampling chip IC1 is the sampling pin, and this pin will collect the divided voltage of R15 and R18. The input voltage value at the input end is determined by the voltage of this voltage node, that is, the voltage of the monitoring point potential VD-1. The determination formula is Uf = Uac * 1.414 * Ns / Np + Vout + Vf. Due to the leakage inductance of the transformer, there are still spikes. The actual measured peak voltage of the internally integrated MOSFET in the synchronous rectification chip U1 is 49.23V. With the resistance value of resistor R15 being 82KΩ and the resistance value of resistor R18 being 2.4KΩ, the value of the monitoring point potential VD-1 is obtained as 1.4V. When it is detected that the monitoring point potential VD-1 is less than 1.4V, it is determined that the input is low voltage, and at this time the output is 20W. When it is detected that the monitoring point potential VD-1 is greater than 1.4V, it is determined that the input is high voltage, and at this time the output is 30W. The detection of high and low voltage inputs is realized by detecting the peak value of the secondary MOSFET.

[0017] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A circuit for detecting the voltage across the synchronous rectifier to input high and low voltage sampling, comprising a transformer T1, a synchronous rectifier chip U1, an ADC sampling chip IC1, and a monitoring point potential VD-1, characterized in that: Pin 1 of the synchronous rectifier chip U1 is connected to the right end of capacitor C6, the lower end of capacitor C4, the lower end of capacitor C2 and the ground wire GND1, pin 2 of the synchronous rectifier chip U1 is connected to the right end of capacitor C6, the lower end of capacitor C4, the lower end of capacitor C2 and the ground wire GND1, pin 3 of the synchronous rectifier chip U1 is connected to the upper end of resistor R8, the lower end of resistor R8 is connected to the right end of capacitor C6, the lower end of capacitor C4, the lower end of capacitor C2 and the ground wire GND1, pin 4 of the synchronous rectifier chip U1 is connected to the upper end of capacitor C4, the lower end of capacitor C4 is connected to the right end of capacitor C6, the lower end of capacitor C2 and the ground wire GND1, Pins 5, 6, 7 and 8 of the synchronous rectifier chip U1 are all connected to the B end of the transformer T1, the upper end of the resistor R15 and the left end of the resistor R10, the right end of the resistor R10 is connected to the left end of the capacitor C6, the A end of the transformer T1 is connected to the upper end of the capacitor C2, the resistor R15 is connected to the upper end of the capacitor C51, the upper end of the resistor R18 and the pin 19 of the ADC sampling chip IC1, the pin 19 of the sampling chip IC1 is provided with a monitoring point potential VD-1, the lower end of the capacitor C51 is connected to the lower end of the resistor R18 and the ground wire GND2, and the lower end of the resistor R18 is connected to the lower end of the capacitor C51 and the ground wire GND2; Pin 1 of the ADC sampling chip IC1 is connected to the right end of the resistor R38, pin 2 of the ADC sampling chip IC1 is connected to the right end of the resistor R53, pin 3 of the ADC sampling chip IC1 is connected to the right end of the capacitor C40, pin 4 of the ADC sampling chip IC1 is connected to the right end of the capacitor C41, pin 5 of the ADC sampling chip IC1 is connected to the right end of the capacitor C43, pin 6 of the ADC sampling chip IC1 is connected to the right end of the capacitor C44, the left end of the resistor R38 is connected to the left end of the resistor R53, the left end of the capacitor C40, the left end of the capacitor C41, the left end of the capacitor C43, the left end of the capacitor C44 and the ground wire GND3, the left end of the resistor R53 is connected to the left end of the resistor R38, the left end of the capacitor C40, the left end of the capacitor C41, The left end of capacitor C43, the left end of capacitor C44 and the ground line GND3, the left end of capacitor C40 is connected to the left end of resistor R38, the left end of resistor R53, the left end of capacitor C41, the left end of capacitor C43, the left end of capacitor C44 and the ground line GND3, the left end of capacitor C41 is connected to the left end of resistor R38, the left end of resistor R53, the left end of capacitor C40, the left end of capacitor C43, the left end of capacitor C44 and the ground line GND3, the left end of capacitor C43 is connected to the left end of resistor R38, the left end of resistor R53, the left end of capacitor C40, the left end of capacitor C41, the left end of capacitor C44 and the ground line GND3, the left end of capacitor C44 is connected to the left end of resistor R38, the left end of resistor R53, the left end of capacitor C40, the left end of capacitor C43, the left end of capacitor C41 and the ground line GND3; Pin 20 of the ADC sampling chip IC1 is connected to the network DPC, pin 21 of the ADC sampling chip IC1 is connected to the network DMC, pin 22 of the ADC sampling chip IC1 is connected to the network CC1 and the upper end of the capacitor C35, the lower end of the capacitor C35 is connected to the ground wire GND5, pin 23 of the ADC sampling chip IC1 is connected to the network CC2 and the upper end of the capacitor C37, the lower end of the capacitor C37 is connected to the ground wire GND4, the peak voltage of the sealed MOSFET inside the synchronous rectifier chip U1 is 49.23V, the resistance value of the resistor R15 is 82KΩ, and the resistance value of the resistor R18 is 2.4KΩ.

Images