Serial communication line monitoring and data reading circuit
By designing a serial communication line monitoring and reading data circuit including isolated power supply, monitoring data circuit and terminals, the problems of complexity and cost of the serial communication system in the prior art are solved, and the circuit safety, stability and data transmission accuracy are achieved.
Patent Information
- Application Number
- CN202422123017.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-08-30
AI Technical Summary
In the prior art, many interfaces and microcontrollers are required in the serial communication system, resulting in complex structures, many components, high cost, and low security and stability.
A serial communication line monitoring and reading data circuit is designed, including an isolated power supply circuit, a monitoring data circuit and terminals. Through components such as optocouplers, transistors and 485 chips, monitoring and reading of TX and RX level signals is realized, reducing the complexity and cost of the circuit.
This circuit requires fewer components. The safety and stability of the circuit are ensured by isolating components such as power supply and transistors, achieving the accuracy of data transmission, and is low in cost, safe and reliable, and highly practical.
Smart Images

Figure CN223038399U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of serial communication, in particular to a serial communication line monitoring and data reading circuit. Background Art
[0002] As the prior art with the publication number of CN203933026U discloses a TSC system based on FPGA and RS485 communication, including: a switching system, a TSC_DSP controller and a 485 bus. The switching system is composed of switching units of one or more capacity levels connected in parallel. The switching system is connected to the TSC_DSP controller through the 485 bus. The TSC switching capacitor includes a digital signal processor and a 485 interface. The switching unit is composed of a 485 interface and a switching module. The control end of the switching module includes an FPGA chip, an optocoupler group and a 485 chip. A line driver and an asynchronous communication serial port logic circuit are respectively arranged inside the RS485 chip and the FPGA chip. A monitoring element is arranged inside the switching unit.
[0003] In the prior art, a lot of interfaces and single-chip microcomputers are required in the communication circuit, and the communication between many single-chip microcomputers uses a serial communication structure, which is more complex, requires more components, has a higher unit price of components, a higher circuit cost, and lower safety and stability. Summary of the Utility Model
[0004] In order to solve the problems in the prior art, the purpose of the utility model is to provide a serial communication line monitoring and data reading circuit, which requires fewer components, and the safety of the circuit and the stability of the transmission process are ensured by corresponding structures.
[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions: a serial communication line monitoring and data reading circuit, including an isolated power supply circuit, a monitoring data circuit and a terminal block; the pins 2 of the optocouplers of the two monitoring data circuits are connected to the pins 2 and 3 of the terminal block respectively. The TX level signal and the RX level signal enter the two monitoring data circuits through the terminal block respectively. The isolated power supply circuit supplies power to the monitoring data reading circuit. The monitoring data reading circuit includes an optocoupler, a triode, a 485 chip and a green terminal; the pin 3 of the optocoupler is connected to the cold ground end GND of the circuit, the pin 4 of the optocoupler is connected to the DI end of the 485 chip, the pin 4 of the optocoupler is connected to the DE end and the RE end of the 485 chip through a triode, the B end of the 485 chip is connected to the pin 1 of the green terminal through the bus B, and the A end of the 485 chip is connected to the pin 2 of the green terminal through the bus A.
[0006] Preferably, the isolated power supply circuit includes a chip U3, which includes a -VIN terminal, a +VOUT terminal, a +VIN terminal, and a –VOUT terminal; the -VIN terminal of the chip U3 is connected to the cold ground terminal GND, and the -VIN terminal of the chip U3 is connected to the +VIN terminal of the chip U3 through a line with a capacitor C2 installed; the –VOUT terminal of the chip U3 is connected to the hot ground terminal SGND, and the –VOUT terminal and the +VOUT terminal of the chip U3 are connected through a line with a capacitor installed.
[0007] Preferably, the +VOUT terminal of the chip U3 is connected to pin 1 of the optocoupler, and the +VOUT terminal of the chip U3 is connected to the line between pin 2 of the optocoupler and the terminal block; the +VIN terminal of the chip U3 is connected to the Vcc terminal of the 485 chip, the +VIN terminal of the chip U3 is connected to the line between pin 4 of the optocoupler and the DI terminal of the 485 chip, the +VIN terminal of the chip U3 is connected to the collector of the triode, and the +VIN terminal of the chip U3 is connected to bus A.
[0008] Preferably, the +VOUT terminal of the chip U3 is connected to pin 1 of the optocoupler through a resistor, and the +VOUT terminal of the chip U3 is connected to the communication line connected to pin 2 of the optocoupler through a resistor; the +VIN terminal of the chip U3 is connected to the line between pin 4 of the optocoupler and the DI terminal of the 485 chip through a resistor, the +VIN terminal of the chip U3 is connected to the collector of the triode through a resistor, the line between the +VIN terminal of the chip U3 and the capacitor is connected to the Vcc terminal of the 485 chip, the line between the +VIN terminal of the chip U3 and the capacitor is connected to bus A through a resistor, and the +VIN terminal of the chip U3 is connected to the cold ground terminal GND of the circuit through a capacitor.
[0009] Preferably, the +VIN terminal of the chip U3 is connected to pin 1 of the terminal block, and pin 4 of the terminal block is connected to the hot ground terminal SGND of the circuit.
[0010] Preferably, pin 4 of the optocoupler is connected to the base of the triode through a resistor, the emitter of the triode is connected to the cold ground terminal GND of the circuit, the collector of the triode is respectively connected to the RE terminal and the DE terminal of the 485 chip, and the +VIN terminal of the chip of the isolated power supply circuit is connected to the collector of the triode through a resistor.
[0011] Preferably, self - reset fuses are installed on both bus A and bus B.
[0012] Preferably, both bus A and bus B are connected to the cold ground terminal GND of the circuit through transient voltage suppression diodes.
[0013] The beneficial effects of the technical solution of the present utility model are as follows: In this solution, fewer components are required for the circuit. By isolating components such as the power supply circuit and the triode, the safety of the circuit is ensured. The two parallel monitoring data circuits can respectively transmit TX level signals and RX level signals to maintain the accuracy of data transmission. Moreover, the above circuit has the characteristics of low cost, large transmission volume, safety isolation, high practicability, and not being easily damaged. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a structural schematic diagram of two monitoring data reading circuits;
[0015] Figure 2 It is a structural schematic diagram of the isolated power supply circuit;
[0016] Figure 3 It is a structural schematic diagram of the terminal block. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0017] The embodiments of the present utility model will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present utility model, but should not be construed as a limitation of the present utility model.
[0018] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present utility model.
[0019] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise specified, the meaning of "plurality" is two or more, unless otherwise clearly defined.
[0020] In the present utility model, unless otherwise clearly defined and limited, terms such as "installation", "connection", "linkage", "fixation" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0021] In the present utility model, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on the top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature. Embodiment
[0022] As Figures 1-3 Shown, a serial communication line monitoring and data reading circuit includes an isolated power supply circuit, a monitoring data circuit and a terminal block; the pins 2 of the optocouplers of two monitoring data circuits are respectively connected to the pin 2 and pin 3 of the terminal block, and the TX level signal and RX level signal enter the two monitoring data circuits through the terminal block respectively; the isolated power supply circuit supplies power to the monitoring data reading circuit; the monitoring data reading circuit includes an optocoupler, a triode, a 485 chip and a green terminal; the pin 3 of the optocoupler is connected to the cold ground terminal GND of the circuit, the pin 4 of the optocoupler is connected to the DI terminal of the 485 chip, the pin 4 of the optocoupler is connected to the DE terminal and RE terminal of the 485 chip through a triode, the B terminal of the 485 chip is connected to the pin 1 of the green terminal through bus B, and the A terminal of the 485 chip is connected to the pin 2 of the green terminal through bus A.
[0023] With such a setting, data reading, monitoring and recording can be performed on the serial circuit in communication, and it has the characteristics of low circuit cost, safety isolation, high practicability and not being easily damaged.
[0024] In this embodiment, as Figure 1As shown in the figure, the structures of the two monitoring data reading circuits are the same. Taking the monitoring data reading circuit of the RX communication line as an example, the monitoring data reading circuit of the RX communication line includes an optocoupler U1; the RX communication line is connected to pin 2 of the optocoupler U1, the power isolation circuit is connected to pin 1 of the optocoupler U1D, and the power isolation circuit is connected to the RX communication line; pin 4 of the optocoupler U1 is connected to the DI terminal of the 485 chip IC1, and pin 4 of the optocoupler U1 is connected to the DE terminal and RE terminal of the 485 chip IC1 through a triode Q1; pin 3 of the optocoupler U1 is connected to the cold ground terminal GND of the circuit.
[0025] Further, the RX communication line is connected to pin 2 of the optocoupler U1 through a resistor R1, the power isolation circuit is connected to pin 1 of the optocoupler U1 through a resistor R3, and the power isolation circuit is connected to the RX communication line; pin 4 of the optocoupler U1 is connected to the DI terminal of the 485 chip IC1 through a resistor R11, pin 4 of the optocoupler U1 is connected to the triode through a resistor R5, and pin 4 of the optocoupler U1 is connected to the DE terminal and RE terminal of the 485 chip IC1 through a triode Q1; pin 3 of the optocoupler U1 is connected to the cold ground terminal GND of the circuit.
[0026] Further, the specification of the triode is Q-NPN, and the specification of the optocoupler U1 is O-PC817.
[0027] In this embodiment, the B terminal of the 485 chip IC1 is connected to pin 1 of the green terminal X1 through the bus B, and the A terminal of the 485 chip IC1 is connected to pin 2 of the green terminal X1 through the bus A; the green terminal X1 is connected to the host computer.
[0028] Further, the A terminal of the 485 chip IC1 is connected to pin 1 of the green terminal X1 through the bus A installed with the self-resetting fuse PCT2, and the B terminal of the 485 chip IC1 is connected to pin 2 of the green terminal X1 through the bus B of the self-resetting fuse PCT1; the bus A is connected to the cold end GND of the circuit through the transient voltage suppression diode TVS2, and the bus B is connected to the cold ground terminal GND of the circuit through the transient voltage suppression diode TVS1.
[0029] In this implementation, as Figure 2 shown, the two parallel monitoring data reading circuits are powered by an isolation circuit. Specifically, the isolated power supply circuit includes a chip U3, and the chip U3 includes a -VIN terminal, a +VOUT terminal, a +VIN terminal, and a –VOUT terminal; the -VIN terminal of the chip U3 is connected to the cold ground terminal GND, and the -VIN terminal of the chip U3 is connected to the +VIN terminal of the chip U3 through a line installed with a capacitor C2; the –VOUT terminal of the chip U3 is connected to the hot ground terminal SGND, and the –VOUT terminal and the +VOUT terminal of the chip U3 are connected through a line installed with a capacitor C21.
[0030] Further, the model of chip U3 is B0505S-1WR3.
[0031] Further, the +VOUT terminal of chip U3 is connected to pin 1 of optocoupler U1 through resistor R3, and the +VOUT terminal of chip U3 is connected to pin 2 of optocoupler U1 through resistor R1.
[0032] Further, the +VIN terminal of chip U3 is connected to the line between pin 4 of optocoupler U1 and the DI terminal of 485 chip IC1 through resistor R6;
[0033] Pin 4 of optocoupler U1 is connected to the base of triode Q1 through resistor R7. The emitter of triode Q1 is connected to the cold ground terminal GND of the circuit, and the collector of triode Q1 is respectively connected to the RE terminal and DE terminal of 485 chip IC1. The +VIN terminal of chip U3 is connected to the collector of triode Q1 through resistor R9;
[0034] The +VIN terminal of chip U3 is connected to the cold ground terminal of the circuit through capacitor C1. The line between the +VIN terminal of chip U3 and capacitor C1 is respectively connected to the Vcc terminal of 485 chip IC1 and bus A. Bus B is connected to the cold ground terminal GND of the circuit through resistor R13. The GND terminal of 485 chip IC1 is connected to the cold ground terminal GND of the circuit.
[0035] In this embodiment, it further includes a terminal block. Pin 1 of the terminal block is connected to the +VOUT terminal of the isolated power supply circuit. Pin 2 of the terminal block is connected to the RX communication line and pin 2 of optocoupler U1. Pin 1 of the terminal block is connected to the TX communication line and pin 2 of optocoupler U2. Pin 1 of the terminal block is connected to the hot ground terminal SGND.
[0036] In this embodiment, the specifications of resistor R1 and resistor R3 are different; the specification of resistor R1 is: 0603, 10K, 5%; the specification of resistor R3 is: 0603, 680R, 5%.
[0037] The specifications of resistor R6, resistor R9, resistor R13 and resistor R15 are: 10K / 5%; the specification of resistor R5 is: 0603, 10K, 5%; the specification of resistor R11 is: 1K / 5%;
[0038] The specifications of capacitor C1, capacitor C2 and capacitor C3 are: C-0603, 10%, X7R, 50V, 104.
[0039] In this embodiment, the hot ground terminal SGND is grounded together with the ground of the communication line of the serial port to be monitored and read.
[0040] A method for monitoring, reading, and recording the data of a serial communication line using a host computer. Using the above-mentioned serial communication line monitoring and data reading circuit, the communication line TX and communication line RX for communicating and sending data are respectively connected to two parallel monitoring data reading circuits through terminal blocks. The optocouplers on the two monitoring data reading circuits respectively read the high and low level signals of the level signals from the communication line TX and the communication line RX. The read high and low levels are converted into 485 communication signals through a 485 chip. The monitoring data reading circuit is connected to the 485 communication interface of the host computer through a line. The host computer reads and records the 485 communication signals from the monitoring data reading circuit, and then reads, records, and saves the content, information, and data of the mutual communication on the monitored serial communication line; wherein, the monitoring data reading circuit controls the data enabling acceptance of the 485 chip through a triode.
[0041] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.
[0042] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and purposes of the present invention.
Claims
1. A serial communication line monitoring and reading data circuit, characterized in that: Includes isolated power circuit, monitoring data circuit and wiring terminals; Pin 2 of the optocoupler of the two monitoring data circuits is connected to pin 2 and pin 3 of the wiring terminal respectively, and the TX level signal and the RX level signal enter the two monitoring data circuits respectively through the wiring terminal; The isolated power supply circuit supplies power to the monitoring data reading circuit; The monitoring data reading circuit includes an optocoupler, a transistor, a 485 chip and a green terminal; pin 3 of the optocoupler is connected to the cold ground GND of the circuit, pin 4 of the optocoupler is connected to the DI terminal of the 485 chip, pin 4 of the optocoupler is connected to the DE terminal of the 485 chip and the RE terminal of the 485 chip through the transistor, the B terminal of the 485 chip is connected to pin 1 of the green terminal through bus B, and the A terminal of the 485 chip is connected to pin 2 of the green terminal through bus A.
2. A serial communication line monitoring and reading data circuit according to claim 1, characterized in that: The isolated power supply circuit includes a chip U3, and the chip U3 includes a -VIN terminal, a +VOUT terminal, a +VIN terminal and a -VOUT terminal; the -VIN terminal of the chip U3 is connected to the cold ground terminal GND, and the -VIN terminal of the chip U3 is connected to the +VIN terminal of the chip U3 through a line equipped with a capacitor C2; the -VOUT terminal of the chip U3 is connected to the hot ground terminal SGND, and the -VOUT terminal of the chip U3 and the +VOUT terminal of the chip U3 are connected through a line equipped with a capacitor.
3. A serial communication line monitoring and reading data circuit according to claim 2, characterized in that: The +VOUT end of chip U3 is connected to pin 1 of the optocoupler, and the +VOUT end of chip U3 is connected to the line between pin 2 of the optocoupler and the wiring terminal; the +VIN end of chip U3 is connected to the Vcc end of the 485 chip, and the +VIN end of chip U3 is connected to the line between pin 4 of the optocoupler and the DI end of the 485 chip, the +VIN end of chip U3 is connected to the collector of the transistor, and the +VIN end of chip U3 is connected to bus A.
4. A serial communication line monitoring and reading data circuit according to claim 3, characterized in that: The +VOUT terminal of chip U3 is connected to pin 1 of the optocoupler through a resistor, and the +VOUT terminal of chip U3 is connected to a communication line connected to pin 2 of the optocoupler through a resistor; The +VIN terminal of chip U3 is connected to the line between pin 4 of the optocoupler and the DI terminal of the 485 chip through a resistor. The +VIN terminal of chip U3 is connected to the collector of the transistor through a resistor. The line between the +VIN terminal of chip U3 and the capacitor is connected to the Vcc terminal of the 485 chip, the line between the +VIN terminal of chip U3 and the capacitor is connected to bus A through a resistor, and the +VIN terminal of chip U3 is connected to the cold ground terminal GND of the circuit through a capacitor.
5. A serial communication line monitoring and reading data circuit according to claim 3, characterized in that: The +VIN terminal of the chip U3 is connected to pin 1 of the wiring terminal, and pin 4 of the wiring terminal is connected to the hot ground terminal SGND of the circuit.
6. A serial communication line monitoring and reading data circuit according to claim 3, characterized in that: Pin 4 of the optocoupler is connected to the base of the transistor through a resistor, the transmitting electrode of the transistor is connected to the cold ground GND of the circuit, the collector of the transistor is connected to the RE and DE ends of the 485 chip respectively, and the +VIN end of the chip of the isolation power supply circuit is connected to the collector of the transistor through a resistor.
7. A serial communication line monitoring and reading data circuit according to claim 1, characterized in that: Both bus A and bus B are equipped with resettable fuses.
8. The serial communication line monitoring and reading data circuit according to claim 1, characterized in that: Both bus A and bus B are connected to the cold ground GND of the circuit through transient voltage suppression diodes.
Citation Information
Patent Citations
TSC system based on FPGA and RS485 communication
CN203933026U