Equipment access circuit and concentrator

Abstract

The utility model relates to an equipment access circuit and a concentrator, the equipment access circuit comprises a first reset chip, a second reset chip and a logic circuit, the input end of the first reset chip and the input end of the second reset chip are used for connecting ports of accessed equipment; the output end of the first reset chip and the output end of the second reset chip are connected with the input end of the logic circuit, the output end of the logic circuit is used for being connected with the current limiting switch, and the output end of the first reset chip is used for being connected with the change-over switch. The first reset chip and the second reset chip are used for outputting different level signals under the condition that a port of accessed equipment is positively connected or reversely connected, and the logic circuit is used for outputting a high level signal under the condition that the first reset chip and the second reset chip output different level signals so as to conduct the change-over switch. Therefore, the change-over switch can identify positive connection or reverse connection, the logic circuit can supply power to the accessed equipment under the condition that the port of the accessed equipment is positive connection or reverse connection, and the working reliability is high.

Description

Technical Field

[0001] This application relates to the technical field of signal transmission, and particularly to a device access circuit and a hub. Background Art

[0002] With the development of technology, signal interaction between devices has become increasingly frequent. Generally, signal transmission between two devices can be achieved by connecting the two devices, and the devices can be connected through ports. There are various types of device ports. For example, devices with Type-C ports are widely used.

[0003] For devices to be connected to a Type-C port, the hardware circuits designed by the current alternative chip technical solutions cannot control the on and off of the port power supply. In the context of the rapid iteration of consumer electronics products, the fact that the port is always powered on can cause problems and risks that the device access cannot be recognized, and it is also prone to cause circuit failures and pose safety hazards. Therefore, the traditional hardware circuits for access devices have low working reliability. Summary of the Invention

[0004] Based on this, it is necessary to provide a device access circuit and a hub with reliable operation.

[0005] In a first aspect, this application provides a device access circuit, including a first reset chip, a second reset chip, and a logic circuit. The input ends of the first reset chip and the second reset chip are used to connect to the port of the device to be accessed. The output ends of the first reset chip and the second reset chip are connected to the input end of the logic circuit. The output end of the logic circuit is used to connect to a current limiting switch, and the output end of the first reset chip is used to connect to a switching switch;

[0006] The first reset chip and the second reset chip are used to output different level signals when the port of the device to be accessed is connected correctly or reversely; the logic circuit is used to output a high-level signal to turn on the current limiting switch when the first reset chip and the second reset chip output different level signals.

[0007] In a second aspect, this application provides a hub, including a current limiting switch, a switching switch, and the device access circuit as described above.

[0008] The above device access circuit and hub include a first reset chip, a second reset chip, and a logic circuit. The input ends of the first reset chip and the second reset chip are used to connect to the ports of the device to be accessed. The output ends of the first reset chip and the second reset chip are connected to the input end of the logic circuit. The output end of the logic circuit is used to connect to a current-limiting switch, and the output end of the first reset chip is used to connect to a switching switch. The first reset chip and the second reset chip are used to output different level signals when the ports of the device to be accessed are connected correctly or reversely. The logic circuit is used to output a high-level signal to turn on the switching switch when the first reset chip and the second reset chip output different level signals. Thus, the switching switch can access different level signals when the ports of the device to be accessed are connected correctly or reversely, so as to switch different signal channels and identify correct or reverse connection. In addition, the logic circuit can control the current-limiting switch to turn on when the ports of the device to be accessed are connected correctly or reversely to supply power to the device to be accessed, avoiding the port being always energized and having high working reliability. Brief Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0010] Figure 1 It is a schematic block diagram of the structure of the device access circuit in one embodiment;

[0011] Figure 2 It is a schematic block diagram of the structure of the device access circuit in another embodiment;

[0012] Figure 3 It is a schematic diagram of the structure of the device access circuit in one embodiment;

[0013] Figure 4 It is a schematic block diagram of the structure of the device access circuit in yet another embodiment. Detailed Description of the Embodiments

[0014] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0016] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, the first resistor may be referred to as the second resistor, and similarly, the second resistor may be referred to as the first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0017] It will be understood that "connection" in the following embodiments, if there is a transfer of electrical signals or data between the connected circuits, modules, units, etc., should be understood as "electrical connection", "communication connection", etc.

[0018] It will be understood that "at least one" means one or more, and "a plurality" means two or more. "At least a part of an element" means part or all of the element.

[0019] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0020] In one embodiment, a device access circuit is provided for connecting to the port of a device to be accessed and establishing a connection with the device to be accessed. The type of the port of the device to be accessed is not limited. Exemplarily, the port of the device to be accessed is a Type-C port. Since the Type-C port has a symmetric structure, it is easy to confuse the correct connection and the reverse connection during use. In the prior art, some designs of the downstream Type-C ports use a MUX (Multiplexer) chip to identify and switch high-speed signals during the correct and reverse connection of the device, and control the on / off of the port power supply. However, the manufacturing of the MUX chip is complex and the cost is relatively high. The device access circuit provided in this application can supply power to the port of the device to be accessed whether the port of the device to be accessed is correctly connected or reversely connected, and can identify whether the port of the device to be accessed is correctly connected or reversely connected, facilitating the switching of different signal channels and better cooperating with the port of the device to be accessed. The device access circuit provided in this application can be used as a replacement for the MUX chip, with a lower usage cost and higher resource utilization rate.

[0021] Specifically, as Figure 1 shown, the device access circuit includes a first reset chip 110, a second reset chip 120, and a logic circuit 130. The input ends of the first reset chip 110 and the second reset chip 120 are used to connect to the port of the device to be accessed. The output ends of the first reset chip 110 and the second reset chip 120 are connected to the input end of the logic circuit 130. The output end of the logic circuit 130 is used to connect to a current limiting switch 220. The output end of the first reset chip 110 is used to connect to a switching switch 210. The first reset chip 110 and the second reset chip 120 are used to output different level signals when the port of the device to be accessed is correctly connected or reversely connected. The logic circuit 130 is used to output a high-level signal to turn on the current limiting switch 220 when the first reset chip 110 and the second reset chip 120 output different level signals.

[0022] Among them, the input ends of the first reset chip 110 and the second reset chip 120 are respectively connected to different positions of the port of the device to be accessed. The first reset chip 110 outputs different level signals based on the magnitude relationship between the accessed voltage and its monitored voltage. The different level signals can be high-level signals and low-level signals. Generally, the first reset chip 110 outputs a low-level signal when the accessed voltage is less than its monitored voltage, and outputs a high-level signal when the accessed voltage is greater than or equal to its monitored voltage. The second reset chip 120 outputs different level signals based on the magnitude relationship between the accessed voltage and its monitored voltage. Generally, the first reset chip 110 outputs a low-level signal when the accessed voltage is less than its monitored voltage, and outputs a high-level signal when the accessed voltage is greater than or equal to its monitored voltage.

[0023] It should be noted that the forward connection and the reverse connection are two opposite connection directions of the port of the device to be connected and the device access circuit. Taking the port of the device to be connected including opposite first-side port and second-side port as an example, if the first-side port is connected to the first reset chip 110 and the second-side port is connected to the second reset chip 120, it is defined as the forward connection, then the first-side port is connected to the second reset chip 120 and the second-side port is connected to the first reset chip 110 is the reverse connection.

[0024] The first reset chip 110 and the second reset chip 120 are used to output different level signals when the port of the device to be connected is in the forward connection or the reverse connection, which means that the first reset chip 110 outputs different level signals when the port of the device to be connected is in the forward connection or the reverse connection, and the second reset chip 120 outputs different level signals when the port of the device to be connected is in the forward connection or the reverse connection, and when the port of the device to be connected is in the forward connection, the first reset chip 110 and the second reset chip 120 output different level signals, or when the port of the device to be connected is in the reverse connection, the first reset chip 110 and the second reset chip 120 output different level signals. Exemplarily, when the port of the device to be connected is in the forward connection, the first reset chip 110 outputs a low level signal and the second reset chip 120 outputs a high level signal; when the port of the device to be connected is in the reverse connection, the first reset chip 110 outputs a high level signal and the second reset chip 120 outputs a low level signal.

[0025] Since the first reset chip 110 outputs different level signals when the port of the device to be connected is in the forward connection or the reverse connection, the switching switch 210 is connected to the output end of the first reset chip 110. The switching switch 210 includes a plurality of signal channels, for example, including a forward connection signal channel and a reverse connection signal channel. The switching switch 210 can access different level signals when the port of the device to be connected is in the forward connection or the reverse connection, so as to switch different signal channels to identify the forward connection or the reverse connection. And it can be ensured that the matching signal channels can be connected when the port of the device to be connected is in the forward connection or the reverse connection. Exemplarily, when the port of the device to be connected is in the forward connection, the first reset chip 110 outputs a low level, and the forward connection signal channel of the switching switch 210 is turned on. When the port of the device to be connected is in the reverse connection, the first reset chip 110 outputs a high level, and the switching switch 210 switches to the reverse connection signal channel to be turned on.

[0026] The logic circuit 130 is configured to output a high-level signal to turn on the current-limiting switch 220 when the first reset chip 110 and the second reset chip 120 output different level signals. The logic circuit 130 implements the corresponding logic judgment function based on its own structure. In this embodiment, the logic circuit 130 is configured to output a high-level signal when the first reset chip 110 and the second reset chip 120 output different level signals. That is, the logic circuit 130 outputs a high-level signal when the first reset chip 110 outputs a low-level signal and the second reset chip 120 outputs a high-level signal. Alternatively, the logic circuit 130 outputs a high-level signal when the first reset chip 110 outputs a high-level signal and the second reset chip 120 outputs a low-level signal. The structure of the logic circuit 130 is not limited as long as the corresponding function can be achieved.

[0027] The current-limiting switch 220 is connected to the output terminal of the logic circuit 130. Based on the different signals output by the logic circuit 130, the current-limiting switch 220 is in a conducting or non-conducting state. When the logic circuit 130 outputs a high-level signal, the current-limiting switch 220 conducts. The current-limiting switch 220 is used to connect to a voltage. When the current-limiting switch 220 conducts, the current-limiting switch 220 can transmit the connected voltage to the port of the device to be connected and supply power to the port of the device to be connected.

[0028] In this embodiment, the device access circuit includes a first reset chip 110, a second reset chip 120, and a logic circuit 130. The input terminals of the first reset chip 110 and the second reset chip 120 are used to connect to the port of the device to be connected. The output terminals of the first reset chip 110 and the second reset chip 120 are connected to the input terminal of the logic circuit 130. The output terminal of the logic circuit 130 is used to connect to the current-limiting switch 220. The output terminal of the first reset chip 110 is used to connect to the switching switch 210. The first reset chip 110 and the second reset chip 120 are configured to output different level signals when the port of the device to be connected is connected correctly or reversely. The logic circuit 130 is configured to output a high-level signal to turn on the current-limiting switch 220 when the first reset chip 110 and the second reset chip 120 output different level signals. Thus, the switching switch 210 can access different level signals when the port of the device to be connected is connected correctly or reversely to switch different signal channels and identify the correct or reverse connection. In addition, the logic circuit 130 can control the current-limiting switch 220 to conduct when the port of the device to be connected is connected correctly or reversely to supply power to the device to be connected, avoiding the port being always energized and having high working reliability.

[0029] In one embodiment, as Figure 2As shown, the device access circuit further includes a signal inversion circuit 140. The output end of the first reset chip 110 is connected to the switching switch 210 through the signal inversion circuit 140. The signal inversion circuit 140 is in a conducting or non-conducting state when different level signals are output at the output end of the first reset chip 110.

[0030] Specifically, the signal inversion circuit 140 is used to invert the signal output by the first reset chip 110 and then transmit it to the switching switch 210. Based on the signal inversion circuit 140, it can help the switching switch 210 work properly. Exemplarily, if the default channel of the switching switch 210 is the reverse-connected signal channel and the first-channel chip outputs a low-level signal when the port of the device to be connected is forward-connected, then under the action of the signal inversion circuit 140, the low-level signal output by the first-channel chip can be converted into a high-level signal and then transmitted to the switching switch 210, so that the switching switch 210 switches to the forward-connected signal channel to match the port direction of the device to be connected.

[0031] In this embodiment, the device access circuit further includes a signal inversion circuit 140. The output end of the first reset chip 110 is connected to the switching switch 210 through the signal inversion circuit 140. The signal inversion circuit 140 is in a conducting or non-conducting state when different level signals are output at the output end of the first reset chip 110. Through the inversion function of the signal inversion circuit 140, the switching switch 210 can be switched to the working state that matches the port direction of the device to be connected to ensure the normal operation of the circuit.

[0032] Exemplarily, in one embodiment, when a low-level signal is output at the output end of the first reset chip 110, the signal inversion circuit 140 is in a non-conducting state; when a high-level signal is output at the output end of the first reset chip 110, the signal inversion circuit 140 is in a conducting state.

[0033] Specifically, when a low-level signal is output at the output end of the first reset chip 110, the signal inversion circuit 140 is in a non-conducting state, and the signal inversion circuit 140 can output a high-level signal to achieve the function of signal inversion. When a high-level signal is output at the output end of the first reset chip 110, the signal inversion circuit 140 is in a conducting state, and the signal inversion circuit 140 can output a low-level signal to achieve the function of signal inversion.

[0034] The structure and type of the signal inversion circuit 140 are not unique, as long as the function of signal inversion can be achieved. Exemplarily, in one embodiment, the signal inversion circuit 140 is a control switch. The control end of the control switch is connected to the output end of the first reset chip 110. The first end of the control switch is grounded, and the second end of the control switch is connected to the switching switch 210.

[0035] Based on different level signals applied to its control terminal, the control switch can be in a conducting or non-conducting state, so that the level signals accessed by the switching switch 210 connected to the second terminal of the control switch are different. Exemplarily, the control switch can be disconnected when a low-level signal is applied to its control terminal, so that the voltage at the second terminal of the control switch is high, and the switching switch 210 accesses a high-level signal. Further, there are also various choices for the type of the control switch. For example, it can be a MOS transistor, a bipolar transistor, etc. In this embodiment, the control switch can be an NMOS transistor.

[0036] In this embodiment, the signal inversion circuit 140 is a control switch. The control terminal of the control switch is connected to the output terminal of the first reset chip 110. The first terminal of the control switch is grounded, and the second terminal of the control switch is connected to the switching switch 210. Based on different level signals applied to its control terminal, the control switch can be in a conducting or non-conducting state, so that the level signals accessed by the switching switch 210 connected to the second terminal of the control switch are different. The function of signal inversion is realized based on the control switch, and the structure is simple.

[0037] In one embodiment, the monitoring voltages of the first reset chip 110 and the second reset chip 120 are equal.

[0038] Specifically, the monitoring voltage refers to the reference voltage used by the first reset chip 110 and the second reset chip 120 to compare with the accessed voltage. The monitoring voltage is determined based on the structures of the first reset chip 110 and the second reset chip 120, and is generally a fixed value after the structures are determined. When connecting to the port of the device to be accessed, the voltages accessed by the first reset chip 110 and the second reset chip 120 are different. When the monitoring voltages of the first reset chip 110 and the second reset chip 120 are equal, in the case where the input terminals of the first reset chip 110 and the second reset chip 120 are connected to the port of the device to be accessed, the first reset chip 110 and the second reset chip 120 compare the accessed voltage with the same monitoring voltage, and then output corresponding signals according to the magnitude relationship between the accessed voltage and the monitoring voltage, which can improve the accuracy of the comparison result, and help the first reset chip 110 and the second reset chip 120 output different level signals when the port of the device to be accessed is connected correctly, and also output different level signals when the port of the device to be accessed is connected reversely.

[0039] Exemplarily, when the port of the device to be connected is in the correct connection state, the voltage applied to the first reset chip 110 is less than its monitoring voltage, and the first reset chip 110 outputs a low-level signal. The voltage applied to the second reset chip 120 is greater than or equal to its monitoring voltage, and the second reset chip 120 outputs a high-level signal. When the port of the device to be connected is in the reverse connection state, the voltage applied to the first reset chip 110 is greater than or equal to its monitoring voltage, and the first reset chip 110 outputs a high-level signal. The voltage applied to the second reset chip 120 is less than its monitoring voltage, and the second reset chip 120 outputs a low-level signal.

[0040] In this embodiment, the monitoring voltages of the first reset chip 110 and the second reset chip 120 are equal. The first reset chip 110 and the second reset chip 120 compare the applied voltage with the same monitoring voltage, and then output corresponding signals according to the magnitude relationship between the applied voltage and the monitoring voltage, which can improve the accuracy of the comparison result and ensure the normal operation of the circuit.

[0041] Furthermore, in one embodiment, the first reset chip 110 and the second reset chip 120 have the same structure. The same structure of the first reset chip 110 and the second reset chip 120 means that they have the same type and model. Exemplarily, the models of both the first reset chip 110 and the second reset chip 120 are ME2805A1 of Winbond Electronics.

[0042] In this embodiment, the same structure of the first reset chip 110 and the second reset chip 120 can reduce the working error caused by device differences, which is beneficial to improving the working performance of the device connected to the circuit.

[0043] In one embodiment, the logic circuit 130 is a NAND gate circuit. Specifically, the two input terminals of the NAND gate circuit are respectively connected to the output terminal of the first reset chip 110 and the output terminal of the second reset chip 120, and the output terminal of the NAND gate circuit is connected to the current limiting switch 220. When the first reset chip 110 and the second reset chip 120 are connected to the device to be connected, regardless of whether the port of the device to be connected is in the correct connection or reverse connection state, the first reset chip 110 and the second reset chip 120 will output different level signals. When the NAND gate circuit receives different level signals at the two input terminals, it first performs an "AND" operation on the two input signals, and then performs a "NOT" operation on the signal after the "AND" operation, and finally outputs a high-level signal.

[0044] In this embodiment, the logic circuit 130 is a NAND gate circuit. The first input terminal of the NAND gate circuit is connected to the output terminal of the first reset chip 110, the second input terminal of the NAND gate circuit is connected to the output terminal of the second reset chip 120, and the output terminal of the NAND gate circuit is connected to the current limiting switch 220. The NAND gate circuit can output a high-level signal when the first reset chip 110 and the second reset chip 120 output different level signals, so as to turn on the current limiting switch 220 and achieve the purpose of supplying power to the port of the connected device.

[0045] In one embodiment, as Figure 3 shown, the device access circuit further includes a first pull-up resistor R748 and a second pull-up resistor R752. The input terminal of the first reset chip 110 is used to access the power supply through the first pull-up resistor R748, and the input terminal of the second reset chip 120 is used to access the power supply through the second pull-up resistor R752. The resistance values of the first pull-up resistor R748 and the second pull-up resistor R752 are not limited and can be determined according to actual requirements. The first pull-up resistor R748 can pull up the voltage at the input terminal of the first reset chip 110 to correspond to the voltage of the accessed power supply, and the second pull-up resistor R752 can pull up the voltage at the input terminal of the second reset chip 120 to correspond to the voltage of the accessed power supply. Thus, the first pull-up resistor R748 can help the first reset chip 110 work properly, and the second pull-up resistor R752 can help the second reset chip 120 work properly. Further, the voltages of the power supplies accessed by the first pull-up resistor R748 and the second pull-up resistor R752 are equal, and the types of the first pull-up resistor R748 and the second pull-up resistor R752 are the same to better ensure the unity and stability of the circuit structure. In addition, the device access circuit may further include a third pull-up resistor R750 and a fourth pull-up resistor R751. The third pull-up resistor R750 is connected to the first reset chip 110 to ensure the stability of the output level of the first reset chip 110, and the fourth pull-up resistor R751 is connected to the second reset chip 120 to ensure the stability of the output level of the second reset chip 120.

[0046] In one embodiment, the device access circuit further includes a first filter circuit and a second filter circuit. The first filter circuit is connected to the first reset chip 110, and the second filter circuit is connected to the second reset chip 120. The first filter circuit can filter out the clutter that affects the operation of the first reset chip 110, which is beneficial to improving the operation performance of the first reset chip 110. The second filter circuit can filter out the clutter that affects the operation of the second reset chip 120, which is beneficial to improving the operation performance of the second reset chip 120.

[0047] In one embodiment, the first filter circuit and the second filter circuit have the same structure. The first filter circuit is a circuit that assists the first reset chip 110 in working, and the second filter circuit is a circuit that assists the second reset chip 120 in working. When the first filter circuit and the second filter circuit have the same structure, the first reset chip 110 and the second reset chip 120 can work under more similar conditions, and only output different signals due to different input signals, reducing other interferences, which is beneficial to improving the accuracy of the signals output by the first reset chip 110 and the second reset chip 120.

[0048] The structures of the first filter circuit and the second filter circuit are not unique. Exemplarily, as Figure 3 shown, the first filter circuit includes a first filter capacitor C892, which functions as a filter. One end of the first filter capacitor C892 is connected to the output terminal of the first reset chip 110, and the other end is grounded. The second filter circuit includes a second filter capacitor C893, which functions as a filter. One end of the second filter capacitor C893 is connected to the output terminal of the second reset chip 120, and the other end is grounded. It can be understood that in other embodiments, the structures of the first filter circuit and the second filter circuit can also be other as long as those skilled in the art consider it feasible.

[0049] In one embodiment, a hub is provided, which includes a current limiting switch 220, a switching switch 210, and the device access circuit of any of the above embodiments.

[0050] To better understand the above embodiments, the following will be explained in detail with a specific embodiment. In one embodiment, as Figure 3 and 4 shown, the hub includes a current limiting switch 220, a switching switch 210, and a device access circuit. The device access circuit includes a first reset chip 110, a second reset chip 120, a logic circuit 130, a signal inverting circuit 140, a first pull-up resistor R748, a second pull-up resistor R752, a third pull-up resistor R750, a fourth pull-up resistor R751, a first filter circuit, and a second filter circuit. The first filter circuit includes a first filter capacitor C892, and the second filter circuit includes a second filter capacitor C893. Among them, the signal inverting circuit 140 is an NMOS transistor, the first reset chip 110 and the second reset chip 120 are both ME2805A1 of Microgate Electronics, the logic circuit 130 is a NAND gate circuit, specifically it can be SN74LVC1G00 of Meisenke, the current limiting switch 220 can be ETA6280 of Yutai, and the switching switch 210 can be a high-speed switching switch, specifically it can be ASW3410 of Yourong Micro. The device to be connected is a device with a Type-C port.

[0051] The working process of the device access circuit includes:

[0052] The first pull-up resistor R748 connected to the first reset chip 110 is a 12K resistor, and the first pull-up resistor R748 is pulled up to 3.3V. The second pull-up resistor R752 connected to the second reset chip 120 is a 12K resistor, and the second pull-up resistor R752 is pulled up to 3.3V. The Type-C port ensures an output capacity of 1.5A. After the connected device is inserted, since the connected device has an internal resistance Rd, the levels of the input terminals CC1 DFP1 of the first reset chip 110 and CC2 DFP1 of the second reset chip 120 will drop below 2.63V due to voltage division. When the first reset chip 110 and the second reset chip 120 detect that the levels of the input terminals CC1 DFP1 of the first reset chip 110 and CC2 DFP1 of the second reset chip 120 are less than 2.63V, their output terminals will output a low level.

[0053] Case 1:

[0054] When the connected device is being inserted, due to resistor voltage division, the level of the input terminal CC1 DFP1 of the first reset chip 110 will be lower than the monitoring voltage of the first reset chip 110. The signal SEL1 output by the first reset chip 110 is a low-level signal, and the signal SEL2 output by the second reset chip 120 is a high-level signal. The signal PWE output through the NAND gate circuit is a high-level signal, the current-limiting switch 220 is turned on, and the Type-C port power supply is turned on.

[0055] Since the default channel of the switching switch 210 is the reverse connection signal channel, the signal is inverted through the NMOS transistor. When SEL1 is a low-level signal, SEL_SW is a high-level signal, and the switching switch 210 can be switched to the forward connection signal channel.

[0056] Case 2:

[0057] When the connected device is inserted reversely, due to resistor voltage division, the level at the input terminal CC2 DFP1 of the second reset chip 120 will be lower than the monitoring voltage of the second reset chip 120. The signal SEL2 output by the second reset chip 120 is a low-level signal. Since SEL1 is a high-level signal at this time, the switching switch 210 remains in the reverse connection signal channel. At the same time, since SEL2 is a low-level signal, after passing through the NAND gate circuit, the signal PWE output by the NAND gate circuit is a high-level signal, the current-limiting switch 220 is turned on, and the Type-C port power supply is turned on.

[0058] Case 3:

[0059] When no access device is inserted, SEL1 is a high-level signal, and the switching switch 210 maintains the default channel. Without a device connected, the input terminals CC1 DFP1 of the first reset chip 110 and the input terminal CC2 DFP1 of the second reset chip 120 are both high-level signals, that is, both SEL1 / 2 are high. After passing through the NAND gate circuit, PWE is a low-level signal, the current-limiting switch 220 is turned off, and the power supply of the Type-C port is turned off.

[0060] Through the above structure, it is possible to realize the positive and negative connection recognition of signals when a Type-C port device is connected, and control the on / off of the current-limiting switch 220 to control the power supply output of the Type-C port, so as to realize the correct switching of the data channel when the device is inserted in the positive and negative directions and the port is not powered when no device is connected. Compared with directly using a MUX chip, there is an obvious price advantage. Compared with the current design that replaces the MUX chip, there is no problem that the external device used by the user cannot be recognized due to the port being constantly powered.

[0061] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0062] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0063] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A device access circuit, characterized in that: It comprises a first reset chip, a second reset chip and a logic circuit, wherein the input end of the first reset chip and the input end of the second reset chip are used to connect to the port of the connected device, the output end of the first reset chip and the output end of the second reset chip are connected to the input end of the logic circuit, the output end of the logic circuit is used to connect to a current limiting switch, and the output end of the first reset chip is used to connect to a switching switch; The first reset chip and the second reset chip are used to output different level signals when the port of the connected device is connected forward or reversely; The logic circuit is used for outputting a high level signal to turn on the current limiting switch when the first reset chip and the second reset chip output signals of different levels.

2. The circuit according to claim 1, characterized in that It also includes a signal inverting circuit, and the output end of the first reset chip is connected to the switching switch through the signal inverting circuit; The signal inversion circuit is in an on or off state when the output end of the first reset chip outputs signals of different levels.

3. The circuit according to claim 2, characterized in that When the output end of the first reset chip outputs a low level signal, the signal inversion circuit is in a disconnected state; when the output end of the first reset chip outputs a high level signal, the signal inversion circuit is in a conductive state.

4. The circuit according to claim 2, characterized in that The signal inversion circuit is a control switch, a control end of the control switch is connected to the output end of the first reset chip, a first end of the control switch is grounded, and a second end of the control switch is connected to the switching switch.

5. The circuit according to claim 1, characterized in that The monitoring voltages of the first reset chip and the second reset chip are equal.

6. The circuit according to claim 1, characterized in that The first reset chip and the second reset chip have the same structure.

7. The circuit according to claim 1, characterized in that The logic circuit is a NAND gate circuit, a first input end of the NAND gate circuit is connected to the output end of the first reset chip, a second input end of the NAND gate circuit is connected to the output end of the second reset chip, and an output end of the NAND gate circuit is used to connect a current limiting switch.

8. The circuit according to claim 1, characterized in that It also includes a first pull-up resistor and a second pull-up resistor. The input end of the first reset chip is used to access the power supply through the first pull-up resistor, and the input end of the second reset chip is used to access the power supply through the second pull-up resistor.

9. The circuit according to claim 1, characterized in that It also includes a first filter circuit and a second filter circuit, the first filter circuit is connected to the first reset chip, and the second filter circuit is connected to the second reset chip.

10. A hub, characterized in that: It comprises a current limiting switch, a switching switch and a device access circuit as described in any one of claims 1 to 9.

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