Communication chip

Abstract

The utility model provides a communication chip, which works based on a hardware circuit and comprises a bus communication pin, a first local output pin, a second local output pin and a local signal input pin. And the first local output pin is used for decoding a twisted pair bus signal into a signal 0 or 1. And the second local output pin decodes 01 of the first local output pin into 0 and decodes 11 of the first local output pin into 1. And the bus communication pin is used for coding a signal 0 of the local signal input pin into 01 and coding 1 into 11. According to the configuration, encoding and decoding are carried out in a hardware decoding mode, software encoding and decoding do not need to be carried out in the MCU or other logic control devices, the calculation burden of the MCU or other logic control devices is relieved, the universality of the communication chip is improved, and a hardware basis is provided for implementation of other anti-interference functions. The communication chip can improve the long-distance communication effect, and solves the problems in the prior art.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuit chips, and particularly relates to a communication chip. Background Art

[0002] In industrial application fields such as commercial air conditioners, master-slave communication usually uses the HBS communication protocol (Home Bus System). It is a concept jointly proposed by Japanese enterprises such as Hitachi, Mitsubishi, Panasonic, and Toshiba, and is formulated by the HBS Standard Committee of the Japan Electronics Industry Association / Institute of Radio Engineers. The HBS protocol supports communication and power supply between the master and slave machines using a pair of twisted wires. The signal transceiver processing uses AMI encoding. The signals on the two transmission lines are differential signals (that is, signals are transmitted on both lines, and the amplitudes of these two signals are the same, but the phases are opposite; the signal receiving end compares the difference between these two voltages to judge the logical state sent by the sending end). The farthest communication distance is generally within 1000m, and the communication rate is generally 9600bps.

[0003] However, with the development of technology, there are more nodes, longer communication distances, and higher communication rates in the communication network. In a more complex communication network, traditional solutions and communication chips face problems such as high bit error rates and slow device response speeds, and the communication effects of traditional solutions and communication chips are not good.

[0004] Specific analysis is as follows: The longer the communication distance and the higher the communication rate, the more severely the signals transmitted on the bus are interfered by the parasitic parameters of the bus, and there will be adverse phenomena such as signal oscillation or distortion. In order to ensure the accuracy of signal transmission on the bus, the previous solution was to add a matching resistor with a lower resistance value between the buses at the farthest node of the communication network to reduce signal reflection and avoid oscillation, so as to achieve the purpose of improving signal quality. However, as the communication distance becomes longer and the communication rate becomes higher, the adverse effects caused by the parasitic parameters of the bus become more obvious. At some remote nodes close to the terminal resistor, good communication effects can still be maintained, but most nodes farther away from the terminal resistor may have abnormal communication. If matching resistors are added between the buses at multiple nodes, it will cause a decrease in the impedance between the buses and an increase in the bus current, and severely, the signal amplitude will be pulled down and communication will be impossible. Therefore, it is not possible to improve the communication situation of each node by adding matching resistors between the buses at each node. A new communication solution and chip are needed to improve the communication situation of each node, reduce the influence of bus parasitic parameters on bus signals, and meet the requirements of more communication nodes, longer communication distances, and higher communication rates.

[0005] In summary, for existing communication solutions, it is difficult to further improve or effectively avoid the impact caused by the parasitic parameters of the bus. Therefore, they cannot be applied to scenarios with longer communication distances and higher communication rates. Specific products may also be restricted from being upgraded due to this. So, a new solution or communication chip is needed to ensure the bus signal quality and improve the communication effect. Summary of the Invention

[0006] The purpose of the present utility model is to provide a communication chip to solve the technical problem in the prior art that it is necessary to ensure the bus signal quality and improve the communication effect.

[0007] To solve the above technical problem, the present utility model provides a communication chip for HBS protocol communication. The communication chip operates based on a hardware circuit and includes: bus communication pins and MCU communication pins. The MCU communication pins include a first local output pin, a second local output pin, and a local signal input pin.

[0008] The first local output pin is used to output signal 0 or 1 based on the differential value of the twisted pair bus signal received by the bus communication pins.

[0009] The second local output pin is used to synchronously output signal 0 when the first local output pin outputs signal 01, and synchronously output signal 1 when the first local output pin outputs signal 11.

[0010] The bus communication pins are used to synchronously output signal 01 when the signal of the local signal input pin is 0, and synchronously output signal 11 when the signal of the local signal input pin is 1.

[0011] Optionally, the communication chip further includes a PWM modulation signal pin, which is used to receive a PWM signal. The communication chip determines a duration of the signals of the bus communication pins and the first local output pin based on half a cycle of the PWM signal, and determines a duration of the signals of the second local output pin and the local signal input pin based on one cycle of the PWM signal.

[0012] Optionally, the communication chip further includes an impedance switching switch and a dynamic impedance matching pin. The bus communication pins include two bus output pins. In at least one connection mode of the communication chip, the dynamic impedance matching pin is used to externally connect a matching resistor.

[0013] The communication chip is used to connect the matching resistor between the two bus output pins through the impedance switching switch when the output signal of the bus output pin drops from a high level to an intermediate level or rises from a low level to an intermediate level, and is used to disconnect the matching resistor from the bus output pin through the impedance switching switch when the duration after connection reaches a preset duration.

[0014] Optionally, the bus communication pin includes a bus output pin, and a voltage stabilizing diode for enhancing the ESD protection ability is provided at the bus output pin.

[0015] Optionally, the communication chip further includes a signal pulse width correction pin, the bus communication pin includes a bus output pin, and the signal pulse width correction pin is used to externally connect a correction resistor.

[0016] The correction resistor is used to eliminate the influence of bus parasitic parameters to compensate the output pulse width of the high level of the bus output pin.

[0017] Optionally, the communication chip includes a decoding and error correction module for filtering out the oscillation of the bus signal, the bus communication pin includes a bus input pin, and the bus input pin is connected to the MCU communication pin through the decoding and error correction module.

[0018] Optionally, the decoding and error correction module includes a signal detection unit, a signal judgment unit, a reference potential providing unit, and an output unit.

[0019] The signal detection unit is used to convert the twisted pair bus signal received by the bus input pin into two-way first intermediate signals.

[0020] The reference potential providing unit is used to provide a reference voltage.

[0021] The signal judgment unit is used to compare the first intermediate signal with the reference voltage. When any one of the first intermediate signals is greater than the reference voltage, the signal judgment unit outputs a first level, otherwise, it outputs a second level.

[0022] The output unit is used to correspondingly change its own output signal based on the output signal of the signal judgment unit.

[0023] Among them, the signal detection unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first constant current source, a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, and an eighth triode.

[0024] The first end of the first resistor is used to receive one of the twisted pair bus signals, and the first end of the seventh resistor is used to receive the other of the twisted pair bus signals.

[0025] The first end of the first resistor is sequentially connected to the first end of the second resistor, the fifth resistor, and the seventh resistor. The connection point of the second resistor and the fifth resistor is also connected to a working voltage.

[0026] The third triode is an NPN type triode. The emitter of the third triode is used to connect to the power supply. The base of the third triode is connected to its own collector. The collector of the third triode is connected to the second end of the first resistor.

[0027] The fourth triode is an NPN type triode. The collector of the fourth triode is connected to the power supply through the third resistor. The base of the fourth triode is connected to the second end of the first resistor. The collector of the fourth triode is used to output one of the first intermediate signals.

[0028] The eighth triode is an NPN type triode. The emitter of the eighth triode is used to connect to the power supply. The base of the eighth triode is connected to its own collector. The collector of the eighth triode is connected to the second end of the seventh resistor.

[0029] The sixth triode is an NPN type triode. The collector of the sixth triode is connected to the power supply through the sixth resistor. The base of the sixth triode is connected to the second end of the seventh resistor. The collector of the sixth triode is used to output the other of the first intermediate signals.

[0030] The emitter of the fourth triode is connected to the emitter of the sixth triode through the fourth resistor.

[0031] The first triode is an NPN type triode. The input end of the first constant current source is used to connect to the power supply. The output end of the first constant current source is connected to the collector of the first triode. The emitter of the first triode is used to connect to the ground.

[0032] The second triode is an NPN type triode. The collector of the second triode is used to connect to the power supply. The base of the second triode is connected to the collector of the first triode. The emitter of the second triode is connected to the base of the first triode.

[0033] The fifth triode is an NPN type triode. The collector of the fifth triode is connected to the emitter of the fourth triode. The base of the fifth triode is connected to the base of the first triode. The emitter of the fifth triode is used to connect to the ground.

[0034] The seventh triode is an NPN type triode. The collector of the seventh triode is connected to the emitter of the sixth triode. The base of the seventh triode is connected to the base of the first triode. The emitter of the seventh triode is used for grounding.

[0035] Optionally, the reference potential providing unit includes an eighth resistor, a second constant current source, a ninth triode, a thirteenth triode, an eleventh triode, a twelfth triode, a thirteenth triode, a fourteenth triode, a fifteenth triode, and a sixteenth triode.

[0036] The ninth triode is an NPN type triode. The base of the ninth triode is connected to the base of the first triode. The emitter of the ninth triode is used for grounding.

[0037] The thirteenth triode is an NPN type triode. The collector of the thirteenth triode is connected to the collector of the ninth triode. The emitter of the thirteenth triode is used for grounding.

[0038] The thirteenth triode is an NPN type triode. The input end of the second constant current source is used for connecting to a power supply. The output end of the second constant current source is connected to the collector of the thirteenth triode. The collector of the thirteenth triode is connected to its own base. The base of the thirteenth triode is connected to the base of the thirteenth triode. The emitter of the thirteenth triode is used for grounding.

[0039] The sixteenth triode is an NPN type triode. The collector of the sixteenth triode is connected to the collector of the thirteenth triode. The emitter of the sixteenth triode is used for grounding. The base of the sixteenth triode is used for receiving a second intermediate signal. The second intermediate signal and the output signal of the output unit change simultaneously.

[0040] The first end of the eighth resistor is used for connecting to a power supply. The second end of the eighth resistor is connected to the collector of the ninth triode.

[0041] The eleventh triode is an NPN type triode. The collector of the eleventh triode is used for connecting to a power supply. The base of the eleventh triode is connected to the second end of the eighth resistor. The emitter of the eleventh triode is used for outputting the reference voltage.

[0042] The twelfth triode is an NPN type triode. The collector of the twelfth triode is connected to the emitter of the eleventh triode. The emitter of the twelfth triode is used for grounding. The base of the twelfth triode is connected to the base of the first triode.

[0043] The fourteenth triode is an NPN-type triode. The collector of the fourteenth triode is used to connect to the power supply. The base of the fourteenth triode is connected to the second end of the eighth resistor. The emitter of the fourteenth triode is used to output the reference voltage.

[0044] The fifteenth triode is an NPN-type triode. The collector of the fifteenth triode is connected to the emitter of the fourteenth triode. The emitter of the fifteenth triode is used to connect to the ground. The base of the fifteenth triode is connected to the base of the first triode.

[0045] Optionally, the signal judgment unit includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a seventeenth triode, an eighteenth triode, a nineteenth triode, a twenty-third triode, a twenty-first triode, a twenty-second triode, a twenty-third triode, a twenty-fourth triode, a twenty-fifth triode, a twenty-sixth triode, a twenty-seventh triode, a twenty-eighth triode, a twenty-ninth triode, and a thirty-third triode.

[0046] The seventeenth triode, the eighteenth triode, the twenty-third triode, the twenty-second triode, the twenty-third triode, the twenty-fourth triode, the twenty-sixth triode, the twenty-eighth triode, the twenty-ninth triode, and the thirty-third triode are all NPN-type triodes; the nineteenth triode, the twenty-first triode, the twenty-fifth triode, and the twenty-seventh triode are all PNP-type triodes.

[0047] The collector of the seventeenth triode is used to connect to the power supply. The collector of the eighteenth triode is connected to the emitter of the seventeenth triode. The base of the eighteenth triode is connected to the base of the first triode. The first end of the ninth resistor is used to connect to the power supply. The second end of the ninth resistor is connected to the emitter of the nineteenth triode. The base of the nineteenth triode is connected to the emitter of the seventeenth triode. The collector of the twenty-third triode is connected to the collector of the nineteenth triode. The collector of the twenty-third triode is also connected to its own base. The emitter of the twenty-third triode is used to connect to the ground. The second end of the ninth resistor is also connected to the emitter of the twenty-first triode. The base of the twenty-first triode is used to obtain the reference voltage. The collector of the twenty-second triode is connected to the collector of the twenty-first triode. The emitter of the twenty-second triode is used to connect to the ground. The base of the twenty-third triode is connected to the collector of the twenty-first triode through the tenth resistor. The emitter of the twenty-third triode is used to connect to the ground. The collector of the twenty-third triode is configured as the output end of the signal judgment unit.

[0048] The collector of the twenty-ninth triode is used to connect to the power supply. The collector of the thirty-third triode is connected to the emitter of the twenty-ninth triode. The base of the thirty-third triode is connected to the base of the first triode. The first end of the twelfth resistor is used to connect to the power supply. The second end of the twelfth resistor is connected to the emitter of the twenty-seventh triode. The base of the twenty-seventh triode is connected to the emitter of the twenty-ninth triode. The collector of the twenty-eighth triode is connected to the collector of the twenty-seventh triode. The collector of the twenty-eighth triode is also connected to its own base. The emitter of the twenty-eighth triode is used to connect to the ground. The second end of the twelfth resistor is also connected to the emitter of the twenty-fifth triode. The base of the twenty-fifth triode is used to obtain the reference voltage. The collector of the twenty-sixth triode is connected to the collector of the twenty-fifth triode. The emitter of the twenty-sixth triode is used to connect to the ground. The base of the twenty-fourth triode is connected to the collector of the twenty-fifth triode through the eleventh resistor. The emitter of the twenty-fourth triode is used to connect to the ground. The collector of the twenty-fourth triode is connected to the collector of the twenty-third triode.

[0049] The base of the twenty-ninth triode is used to receive one path of the first intermediate signal. The base of the seventeenth triode is used to receive the other path of the intermediate signal.

[0050] Optionally, the output unit includes a thirteenth resistor, a fourteenth resistor, a thirty-first triode, a thirty-second triode, a thirty-third triode, a thirty-fourth triode, a thirty-fifth triode, a thirty-sixth triode, a thirty-seventh triode, a thirty-eighth triode, a thirty-ninth triode, a forty-third triode, a forty-first triode, and a forty-second triode.

[0051] The thirty-first triode is a PNP type triode. The emitter of the thirty-first triode is used to connect to the power supply.

[0052] The thirty-second triode is an NPN type triode. The collector of the thirty-second triode is connected to the collector of the thirty-first triode. The emitter of the thirty-second triode is used to connect to the ground. The collector of the thirty-second triode is used to output a second intermediate signal. The second intermediate signal and the output signal of the output unit change simultaneously. The second intermediate signal is used to provide a basis for logical judgment for other units of the decoding and error correction module.

[0053] The thirty-third triode is a PNP type triode. The emitter of the thirty-third triode is used to connect to the power supply. The base of the thirty-third triode is connected to the base of the thirty-first triode. The collector of the thirty-third triode is connected to the base of the thirty-second triode.

[0054] The thirty-fourth triode is an NPN-type triode. The collector of the thirty-fourth triode is connected to the collector of the thirty-third triode, and the emitter of the thirty-fourth triode is used for grounding.

[0055] The thirty-fifth triode is a PNP-type triode. The emitter of the thirty-fifth triode is used for connecting to a power supply. The base of the thirty-fifth triode is connected to the base of the thirty-first triode. The collector of the thirty-fifth triode is connected to the base of the thirty-fourth triode through the thirteenth resistor, and the collector of the thirty-fifth triode is also connected to the output end of the signal judgment unit.

[0056] The thirty-sixth triode is a PNP-type triode. The emitter of the thirty-sixth triode is used for connecting to a power supply, and the base of the thirty-sixth triode is connected to the base of the thirty-first triode.

[0057] The thirty-seventh triode is an NPN-type triode. The collector of the thirty-seventh triode is connected to the collector of the thirty-sixth triode. The base of the thirty-seventh triode is connected to the collector of the thirty-fifth triode through the fourteenth resistor, and the emitter of the thirty-seventh triode is used for grounding.

[0058] The thirty-eighth triode is a PNP-type triode. The emitter of the thirty-eighth triode is used for connecting to a power supply, and the base of the thirty-eighth triode is connected to the base of the thirty-first triode.

[0059] The thirty-ninth triode is an NPN-type triode. The collector of the thirty-ninth triode is connected to the collector of the thirty-eighth triode. The base of the thirty-ninth triode is connected to the collector of the thirty-sixth triode. The emitter of the thirty-ninth triode is used for grounding, and the collector of the thirty-ninth triode is also configured as the output end of the output unit.

[0060] The forty-third triode is a PNP-type triode. The emitter of the forty-third triode is connected to the base of the thirty-first triode, and the collector of the forty-third triode is used for grounding.

[0061] The forty-first triode is a PNP-type triode. The emitter of the forty-first triode is used for connecting to a power supply, and the collector of the forty-first triode is connected to the base of the forty-third triode.

[0062] The forty-second triode is an NPN-type triode. The collector of the forty-second triode is connected to the collector of the forty-first triode. The base of the forty-second triode is connected to the base of the first triode. The emitter of the forty-second triode is used for grounding.

[0063] Optionally, the communication chip further includes at least one of the following pins: a bootstrap capacitor pin, a reset control input pin, a power input pin, and a ground pin.

[0064] Compared with the prior art, a communication chip provided by the present utility model operates based on a hardware circuit. The communication chip includes: a bus communication pin and an MCU communication pin. The MCU communication pin includes a first local output pin, a second local output pin, and a local signal input pin. The first local output pin is used to output signal 0 or 1 based on the differential value of the twisted pair bus signal received by the bus communication pin. The second local output pin is used to synchronously output signal 0 when the first local output pin outputs signal 01, and synchronously output signal 1 when the first local output pin outputs signal 11. The bus communication pin is used to synchronously output signal 01 when the signal of the local signal input pin is 0, and synchronously output signal 11 when the signal of the local signal input pin is 1. With such a configuration, encoding and decoding are performed in a hardware decoding manner, without the need for software encoding and decoding inside the MCU or other logic control devices, reducing the computing burden on the MCU or other logic control devices, increasing the versatility of the communication chip, and providing a hardware basis for the implementation of other anti-interference functions. The communication chip can improve the communication effect over a long distance and solve the problems existing in the prior art. Description of the Drawings

[0065] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present utility model and do not constitute any limitation to the scope of the present utility model. Among them:

[0066] Figure 1 is a connection schematic diagram of the communication chip according to an embodiment of the present utility model;

[0067] Figure 2 is a pin schematic diagram of the communication chip according to an embodiment of the present utility model;

[0068] Figure 3 is the signal timing of the communication chip according to an embodiment of the present utility model;

[0069] Figure 4 is an abnormal waveform diagram of a communication chip without dynamic impedance matching in the prior art;

[0070] Figure 5Waveform schematic of a communication chip according to an embodiment of the present utility model Figure 1 ;

[0071] Figure 6 Waveform schematic of a communication chip according to an embodiment of the present utility model Figure 2 ;

[0072] Figure 7 Waveform comparison diagram of a communication chip of the prior art and an embodiment of the present utility model;

[0073] Figure 8 Abnormal waveform diagram of a communication chip without decoding and error correction function in the prior art;

[0074] Figure 9 Waveform schematic of a communication chip according to an embodiment of the present utility model Figure 3 ;

[0075] Figure 10 Circuit diagram of a decoding and error correction module according to an embodiment of the present utility model.

[0076] Wherein:

[0077] 1 - Signal detection unit; 2 - Reference potential providing unit; 3 - Signal judgment unit; 4 - Output unit. Specific implementation manner

[0078] To make the objectives, advantages and features of the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in very simplified forms and are not drawn to scale, only for facilitating and clearly assisting in explaining the objectives of the embodiments of the present utility model. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases and sometimes different scales are used.

[0079] As used in the present utility model, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. "One end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only the endpoints. The terms "mounted", "connected", "coupled" shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or an integral body; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and may be the internal communication between two components or the interaction relationship between two components. In addition, as used in the present utility model, one component being disposed on another component generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two components, and the two components may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate component, and cannot be construed as indicating or implying the spatial position relationship between the two components, that is, one component may be inside, outside, above, below or on one side of the other component, etc. in any orientation, unless otherwise explicitly specified in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0080] The core idea of the present utility model is to provide a communication chip to solve the technical problems in the prior art that it is necessary to ensure the quality of bus signals and improve the communication effect.

[0081] The following is a description with reference to the accompanying drawings.

[0082] To solve the problems in the above DC carrier communication solution, this embodiment proposes a communication chip and its internal structure, as Figure 1 shown. The chip pins can be compatible with the existing solutions in the prior art to increase compatibility; and by further improving the integration level, the functions of some pins are redefined; the achieved effects are: a chip that can reduce the interference of bus parasitic parameters to improve the communication effect, increase the communication rate to 200 Kbps, and support various communication topologies.

[0083] Compared with the prior art, this embodiment has the following five new functions:

[0084] 1. Built-in encoding function, which changes the signal TXD sent by the MCU to this communication chip from "0" to "01" and from "1" to "11". In the previous solutions, this part of the encoding work needed to be completed by the MCU software encoding. Now it is integrated into the chip internally without software encoding, reducing the occupancy of MCU resources.

[0085] 2. Built-in decoding function, which changes the bus signal received by this communication chip from "01" to "0" and from "11" to "1". In the previous solutions, this part of the decoding work needed to be completed by the MCU software decoding. Now it is integrated into the chip internally without software decoding, reducing the occupancy of MCU resources; at the same time, the waveform after decoding can be corrected through other pins to compensate for the problem of insufficient high-level pulse width caused under complex working conditions and improve the communication quality.

[0086] 3. Built-in dynamic impedance matching function. In the solution based on the HBS communication protocol, only one device sends signals at the same time. The dynamic impedance matching function in the communication chip is enabled when the chip sends signals. Through the internal switch control of the chip, the potentials of the two buses are quickly pulled to be equal, making the bus differential value stable at 0 and the decoding stable at 1. This function can solve the problem that the bus differential waveform on the transmission line is not "steep" enough or even oscillates when changing from "low level to intermediate level" or "high level to intermediate level", ensuring the accuracy of the decoded signal. Since only the dynamic impedance matching function of one node is in effect at the same time, it will not cause the situation that the impedance between the buses decreases due to multiple matching resistors being incorporated into the bus as in the previous communication solutions. The intervention time of the dynamic impedance matching function can also be adjusted to further reduce the bus power consumption.

[0087] 4. Built-in signal correction function, through which the high-level pulse width of the decoded signal (referring to the RXD signal finally given to the MCU) can be compensated, improving the problem of insufficient pulse width of the decoded signal under complex working conditions such as long-distance communication in the previous communication solutions and ensuring the communication quality.

[0088] 5. Built-in decoding error correction function. By building the decoding error correction function in the bus signal receiving pin of the communication chip, the error codes caused by bus interference or oscillation can be solved, improving the decoding accuracy and stability.

[0089] Specifically, the communication chip is used for HBS protocol communication. The communication chip works based on the hardware circuit. The communication chip includes: bus communication pins and MCU communication pins. The MCU communication pins include a first local output pin, a second local output pin, and a local signal input pin.

[0090] Figure 1 Among them, the numbers 1 to 16 represent the pin numbers, that is, the abbreviated form of PIN1 to PIN16, not the reference numbers in the attached drawings, Figure 2 and it should also be understood in this way.Figure 1 Among them, XL1195 is the serial number of the communication chip.

[0091] In this embodiment, PIN9 - OUT(A), PIN10 - OUT(B), PIN15 - IN2, and PIN16 - IN1. The above four pins are the bus communication pins; PIN1 - DATA OUTA is the first local output pin, PIN2 - DATA OUTB is the second local output pin, and PIN6 - DATA IN is the local signal input pin. The above content can also be referred to Figure 2 for understanding.

[0092] Among them, the first local output pin is used to output signal 0 or 1 based on the differential value of the twisted - pair bus signal received by the bus communication pin.

[0093] The second local output pin is used to synchronously output signal 0 when the first local output pin outputs signal 01, and synchronously output signal 1 when the first local output pin outputs signal 11.

[0094] The bus communication pin is used to synchronously output signal 01 when the signal of the local signal input pin is 0, and synchronously output signal 11 when the signal of the local signal input pin is 1.

[0095] It can be understood that the signal durations of the bus communication pin, the first local output pin, the second local output pin, and the local signal input pin are not exactly the same. Their specific lengths and the proportional relationships between them can be understood according to the above description.

[0096] The above logic can also be referred to Figure 3 for understanding. In Figure 3 , the signal output by the MCU is the initial signal. Then, on the premise that there is no abnormality in the communication link, the signal of the local signal input pin is consistent with the initial signal. The internal coding logic of the communication chip is to convert 0 into 01 and 1 into 11, and then output the expected twisted - pair bus signal to the bus as Figure 3 shown. When the absolute value of the difference of the signal is relatively large, it is regarded as 1, otherwise it is regarded as 0. If necessary, the internal coding signal can also be output through the first local output pin and the second local output pin. The output logic has been described above, and its waveform is as Figure 3 shown.

[0097] Through the encoding and decoding of the internal hardware circuit of the communication chip, the chip has more powerful functions and higher integration. It does not require software encoding and decoding, reducing the occupation of MCU resources.

[0098] The communication chip further includes a PWM modulation signal pin, which is used to receive a PWM signal. The communication chip determines a duration of signals of the bus communication pin and the first local output pin based on a half cycle of the PWM signal, and determines a duration of signals of the second local output pin and the local signal input pin based on a cycle of the PWM signal. PIN7 - PWM is the PWM modulation signal pin, and the above logic can also be referred to Figure 3 for understanding.

[0099] The communication chip further includes an impedance switching switch and a dynamic impedance matching pin. The bus communication pin includes two bus output pins. In at least one connection mode of the communication chip, the dynamic impedance matching pin is used to externally connect a matching resistor. PIN8 - RT is the dynamic impedance matching pin, and RT is the matching resistor.

[0100] The communication chip is used to connect the matching resistor between the two bus output pins through the impedance switching switch when the output signal of the bus output pin drops from a high level to an intermediate level or rises from a low level to an intermediate level, and is used to disconnect the matching resistor from the bus output pin through the impedance switching switch when the duration after connection reaches a preset duration.

[0101] As Figure 4 shown, in complex working conditions such as long - distance communication, due to large bus parasitic parameters, the signals transmitted on the bus will be significantly interfered, resulting in oscillation when turning to the intermediate level. The communication chips in the previous HBS communication solutions cannot completely eliminate such interference in long - distance communication, so it will lead to abnormal decoded signals, a certain bit error rate in the communication device, slow response speed or even unsuccessful communication. For a chip with dynamic impedance matching function, the communication effect is as Figure 5 shown. The dynamic impedance matching function can be enabled at the rising edge of the signal after internal encoding of the DATAIN and PWM signals. The internal switch is used to connect the built - in matching resistor in parallel to PIN9 (OUTA) and PIN10 (OUTB) to improve the signals transmitted on the bus, making the waveform steep and stable when turning to the intermediate level, and the dynamic impedance matching equalization duration can be adjusted by adjusting the resistance of chip PIN8 (RT) to reduce the bus power consumption. Figure 4 and Figure 5 The circled parts in

[0102] are the main contents of concern.

[0103] Further, the bus communication pins include bus output pins, and a voltage stabilizing diode is provided at the bus output pins to enhance the ESD (Electro-Static Discharge) protection ability. The bus output pins are PIN9-OUT(A) and PIN10-OUT(B). Since PIN9 and PIN10 are connected to the bus through capacitors, the interference voltage on the bus, especially high-voltage spikes such as coupled strong electrical signals and lightning surges, can cause breakdown damage to pins 9 and 10 of the chip. By adding a voltage stabilizing diode (increasing the wafer area of the voltage stabilizing diode to improve its instantaneous power tolerance) at pins 9 and 10 to absorb high-voltage, high-frequency, and high-energy spike signals, the ESD protection ability is enhanced, and the chip is protected from being damaged by interference signals such as static electricity and spike signals on the bus.

[0104] The communication chip further includes a signal pulse width correction pin, the bus communication pins include bus output pins, and the signal pulse width correction pin is used to externally connect a correction resistor.

[0105] The correction resistor is used to eliminate the influence of bus parasitic parameters to compensate for the output pulse width of the high level of the bus output pin. PIN14-RD is the signal pulse width correction pin, and RD is the correction resistor. In this embodiment, the correction resistor is used to compensate the output signal of PIN2-DATAOUTB. In other embodiments, according to different pin settings, other output signals can be compensated.

[0106] As Figure 6 shown, in complex working conditions such as long-distance communication, due to the large bus parasitic parameters, the signals transmitted on the bus will be significantly interfered. When the bus signal turns to the intermediate level, it is not fast and steep enough. The communication chips in the previous HBS communication solutions cannot completely eliminate such interference in long-distance communication, so the high-level pulse width of the decoded signal is insufficient, affecting the communication quality. However, a chip with a signal correction function can adjust the resistance value of PIN14 (RD) to compensate for the high-level pulse width of the DATAOUT(B) signal in complex working conditions, making it basically consistent with the DATAIN signal to ensure the communication quality.

[0107] The communication chip includes a decoding and error correction module, the bus communication pins include bus input pins, the bus input pins are connected to the MCU communication pins through the decoding and error correction module, and the decoding and error correction module is used to filter out the oscillation of the bus signal to ensure the accuracy of the output signal of the MCU communication pins. The bus input pins are PIN15-IN2 and PIN16-IN1.

[0108] In the past, the HBS communication chip simply obtained logic "0" or "1" by judging the magnitude of the differential value of the bus signal. For example, when the differential value of the bus signal was greater than a0 (a certain value), logic "0" was obtained, and when it was less than a0, logic "1" was obtained. However, for the chip with decoding and error correction functions, the signal inversion points of the decoded signals are different. The starting point (rising edge) of the inversion of the decoded signal is VH, and the closing point (falling edge) is VL.

[0109] The schematic diagram of the decoding and error correction function in terms of communication effect is as Figure 7 , Figure 8 , Figure 9 shown. Figure 8 Combined with Figure 9 the content of Figure 7 and Figure 8 and Figure 9 are essentially the same in nature, but Figure 8 and Figure 9 are simulation result diagrams and are more persuasive. Figures 7 - 9 In

[0110] From Figures 7 - 9 the content, it can be seen that when there is no decoding and error correction module, the communication chip is prone to errors in the decoded signal, while when there is a decoding and error correction module, the communication chip is not prone to errors in the decoded signal.

[0111] Specifically, please refer to Figure 10 , the decoding and error correction module includes a signal detection unit 1, a signal judgment unit 3, a reference potential providing unit 2 (which can also be understood as an error correction unit), and an output unit 4.

[0112] The signal detection unit 1 is used to convert the twisted pair bus signal received by the bus input pin into two-way first intermediate signals (i.e., the output signals at points A and B in the figure).

[0113] The reference potential providing unit 2 is used to provide a reference voltage (i.e., the voltages at F1 and F2 in the figure).

[0114] The signal determination unit 3 is configured to compare the first intermediate signal with the reference voltage. When any one of the first intermediate signals is greater than the reference voltage, the signal determination unit 3 outputs a first level; otherwise, it outputs a second level.

[0115] The output unit 4 is configured to correspondingly change its output signal based on the output signal of the signal determination unit 3.

[0116] Among them, the signal detection unit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first constant current source IS1, a first triode Q1, a second triode Q2, a third triode Q3, a fourth triode Q4, a fifth triode Q5, a sixth triode Q6, a seventh triode Q7, and an eighth triode Q8.

[0117] The first end of the first resistor is used to receive one of the twisted pair bus signals, and the first end of the seventh resistor is used to receive the other of the twisted pair bus signals.

[0118] The first end of the first resistor is sequentially connected to the first ends of the second resistor, the fifth resistor, and the seventh resistor, and the connection point between the second resistor and the fifth resistor is also connected to a working voltage.

[0119] The third triode is an NPN type triode. The emitter of the third triode is used to connect to the power supply. The base of the third triode is connected to its own collector, and the collector of the third triode is connected to the second end of the first resistor.

[0120] The fourth triode is an NPN type triode. The collector of the fourth triode is connected to the power supply through the third resistor. The base of the fourth triode is connected to the second end of the first resistor, and the collector of the fourth triode is used to output one of the first intermediate signals.

[0121] The eighth triode is an NPN type triode. The emitter of the eighth triode is used to connect to the power supply. The base of the eighth triode is connected to its own collector, and the collector of the eighth triode is connected to the second end of the seventh resistor.

[0122] The sixth triode is an NPN type triode. The collector of the sixth triode is connected to the power supply through the sixth resistor. The base of the sixth triode is connected to the second end of the seventh resistor, and the collector of the sixth triode is used to output the other of the first intermediate signals.

[0123] The emitter of the fourth triode is connected to the emitter of the sixth triode through the fourth resistor.

[0124] The first triode is an NPN type triode. The input end of the first constant current source is used to connect to a power supply. The output end of the first constant current source is connected to the collector of the first triode. The emitter of the first triode is used to connect to ground.

[0125] The second triode is an NPN type triode. The collector of the second triode is used to connect to a power supply. The base of the second triode is connected to the collector of the first triode. The emitter of the second triode is connected to the base of the first triode.

[0126] The fifth triode is an NPN type triode. The collector of the fifth triode is connected to the emitter of the fourth triode. The base of the fifth triode is connected to the base of the first triode. The emitter of the fifth triode is used to connect to ground.

[0127] The seventh triode is an NPN type triode. The collector of the seventh triode is connected to the emitter of the sixth triode. The base of the seventh triode is connected to the base of the first triode. The emitter of the seventh triode is used to connect to ground.

[0128] The reference potential providing unit 2 includes an eighth resistor R8, a second constant current source IS2, a ninth triode Q9, a thirteenth triode Q10, an eleventh triode Q11, a twelfth triode Q12, a thirteenth triode Q13, a fourteenth triode Q14, a fifteenth triode Q15, and a sixteenth triode Q16.

[0129] The ninth triode is an NPN type triode. The base of the ninth triode is connected to the base of the first triode. The emitter of the ninth triode is used to connect to ground.

[0130] The thirteenth triode is an NPN type triode. The collector of the thirteenth triode is connected to the collector of the ninth triode. The emitter of the thirteenth triode is used to connect to ground.

[0131] The thirteenth triode is an NPN type triode. The input end of the second constant current source is used to connect to a power supply. The output end of the second constant current source is connected to the collector of the thirteenth triode. The collector of the thirteenth triode is connected to its own base. The base of the thirteenth triode is connected to the base of the thirteenth triode. The emitter of the thirteenth triode is used to connect to ground.

[0132] The sixteenth triode is an NPN type triode. The collector of the sixteenth triode is connected to the collector of the thirteenth triode. The emitter of the sixteenth triode is used to connect to ground. The base of the sixteenth triode is used to receive a second intermediate signal, and the second intermediate signal and the output signal of the output unit change simultaneously.

[0133] The first end of the eighth resistor is used to connect to a power supply, and the second end of the eighth resistor is connected to the collector of the ninth triode.

[0134] The eleventh triode is an NPN type triode. The collector of the eleventh triode is used to connect to a power supply. The base of the eleventh triode is connected to the second end of the eighth resistor. The emitter of the eleventh triode is used to output the reference voltage.

[0135] The twelfth triode is an NPN type triode. The collector of the twelfth triode is connected to the emitter of the eleventh triode. The emitter of the twelfth triode is used to connect to ground. The base of the twelfth triode is connected to the base of the first triode.

[0136] The fourteenth triode is an NPN type triode. The collector of the fourteenth triode is used to connect to a power supply. The base of the fourteenth triode is connected to the second end of the eighth resistor. The emitter of the fourteenth triode is used to output the reference voltage.

[0137] The fifteenth triode is an NPN type triode. The collector of the fifteenth triode is connected to the emitter of the fourteenth triode. The emitter of the fifteenth triode is used to connect to ground. The base of the fifteenth triode is connected to the base of the first triode.

[0138] The signal determination unit 3 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a seventeenth triode Q17, an eighteenth triode Q18, a nineteenth triode Q19, a twentieth triode Q20, a twenty - first triode Q21, a twenty - second triode Q22, a twenty - third triode Q23, a twenty - fourth triode Q24, a twenty - fifth triode Q25, a twenty - sixth triode Q26, a twenty - seventh triode Q27, a twenty - eighth triode Q28, a twenty - ninth triode Q29, and a thirtieth triode Q30.

[0139] The seventeenth triode, the eighteenth triode, the twentieth triode, the twenty - second triode, the twenty - third triode, the twenty - fourth triode, the twenty - sixth triode, the twenty - eighth triode, the twenty - ninth triode, and the thirtieth triode are all NPN type triodes; the nineteenth triode, the twenty - first triode, the twenty - fifth triode, and the twenty - seventh triode are all PNP type triodes.

[0140] The collector of the seventeenth triode is used to connect to the power supply. The collector of the eighteenth triode is connected to the emitter of the seventeenth triode. The base of the eighteenth triode is connected to the base of the first triode. The first end of the ninth resistor is used to connect to the power supply. The second end of the ninth resistor is connected to the emitter of the nineteenth triode. The base of the nineteenth triode is connected to the emitter of the seventeenth triode. The collector of the twenty-third triode is connected to the collector of the nineteenth triode. The collector of the twenty-third triode is also connected to its own base. The emitter of the twenty-third triode is used to connect to the ground. The second end of the ninth resistor is also connected to the emitter of the twenty-first triode. The base of the twenty-first triode is used to obtain the reference voltage. The collector of the twenty-second triode is connected to the collector of the twenty-first triode. The emitter of the twenty-second triode is used to connect to the ground. The base of the twenty-third triode is connected to the collector of the twenty-first triode through the tenth resistor. The emitter of the twenty-third triode is used to connect to the ground. The collector of the twenty-third triode is configured as the output terminal of the signal judgment unit.

[0141] The collector of the twenty-ninth triode is used to connect to the power supply. The collector of the thirty-third triode is connected to the emitter of the twenty-ninth triode. The base of the thirty-third triode is connected to the base of the first triode. The first end of the twelfth resistor is used to connect to the power supply. The second end of the twelfth resistor is connected to the emitter of the twenty-seventh triode. The base of the twenty-seventh triode is connected to the emitter of the twenty-ninth triode. The collector of the twenty-eighth triode is connected to the collector of the twenty-seventh triode. The collector of the twenty-eighth triode is also connected to its own base. The emitter of the twenty-eighth triode is used to connect to the ground. The second end of the twelfth resistor is also connected to the emitter of the twenty-fifth triode. The base of the twenty-fifth triode is used to obtain the reference voltage. The collector of the twenty-sixth triode is connected to the collector of the twenty-fifth triode. The emitter of the twenty-sixth triode is used to connect to the ground. The base of the twenty-fourth triode is connected to the collector of the twenty-fifth triode through the eleventh resistor. The emitter of the twenty-fourth triode is used to connect to the ground. The collector of the twenty-fourth triode is connected to the collector of the twenty-third triode.

[0142] The base of the twenty-ninth triode is used to receive one path of the first intermediate signal. The base of the seventeenth triode is used to receive the other path of the intermediate signal.

[0143] The output unit 4 includes a thirteenth resistor R13, a fourteenth resistor R14, a thirty-first triode Q31, a thirty-second triode Q32, a thirty-third triode Q33, a thirty-fourth triode Q34, a thirty-fifth triode Q35, a thirty-sixth triode Q36, a thirty-seventh triode Q37, a thirty-eighth triode Q38, a thirty-ninth triode Q39, a fortieth triode Q40, a forty-first triode Q41, and a forty-second triode Q42.

[0144] The thirty-first triode is a PNP type triode, and the emitter of the thirty-first triode is used to connect to the power supply.

[0145] The thirty-second triode is an NPN type triode. The collector of the thirty-second triode is connected to the collector of the thirty-first triode. The emitter of the thirty-second triode is used to connect to the ground. The collector of the thirty-second triode is used to output a second intermediate signal. The second intermediate signal and the output signal of the output unit change simultaneously. The second intermediate signal is used to provide a basis for logical judgment for other units of the decoding and error correction module.

[0146] The thirty-third triode is a PNP type triode. The emitter of the thirty-third triode is used to connect to the power supply. The base of the thirty-third triode is connected to the base of the thirty-first triode. The collector of the thirty-third triode is connected to the base of the thirty-second triode.

[0147] The thirty-fourth triode is an NPN type triode. The collector of the thirty-fourth triode is connected to the collector of the thirty-third triode. The emitter of the thirty-fourth triode is used to connect to the ground.

[0148] The thirty-fifth triode is a PNP type triode. The emitter of the thirty-fifth triode is used to connect to the power supply. The base of the thirty-fifth triode is connected to the base of the thirty-first triode. The collector of the thirty-fifth triode is connected to the base of the thirty-fourth triode through the thirteenth resistor. The collector of the thirty-fifth triode is also connected to the output terminal of the signal judgment unit.

[0149] The thirty-sixth triode is a PNP type triode. The emitter of the thirty-sixth triode is used to connect to the power supply. The base of the thirty-sixth triode is connected to the base of the thirty-first triode.

[0150] The thirty-seventh triode is an NPN type triode. The collector of the thirty-seventh triode is connected to the collector of the thirty-sixth triode. The base of the thirty-seventh triode is connected to the collector of the thirty-fifth triode through the fourteenth resistor. The emitter of the thirty-seventh triode is used to connect to the ground.

[0151] The thirty-eighth triode is a PNP type triode. The emitter of the thirty-eighth triode is used to connect to the power supply, and the base of the thirty-eighth triode is connected to the base of the thirty-first triode.

[0152] The thirty-ninth triode is an NPN type triode. The collector of the thirty-ninth triode is connected to the collector of the thirty-eighth triode. The base of the thirty-ninth triode is connected to the collector of the thirty-sixth triode. The emitter of the thirty-ninth triode is used to connect to the ground, and the collector of the thirty-ninth triode is further configured as the output terminal of the output unit.

[0153] The forty-third triode is a PNP type triode. The emitter of the forty-third triode is connected to the base of the thirty-first triode, and the collector of the forty-third triode is used to connect to the ground.

[0154] The forty-first triode is a PNP type triode. The emitter of the forty-first triode is used to connect to the power supply, and the collector of the forty-first triode is connected to the base of the forty-third triode.

[0155] The forty-second triode is an NPN type triode. The collector of the forty-second triode is connected to the collector of the forty-first triode. The base of the forty-second triode is connected to the base of the first triode. The emitter of the forty-second triode is used to connect to the ground.

[0156] Figure 10 In it, both VDD and VCC are power supplies, but their voltage values are different. In one embodiment, VDD is 2.5V and VCC is 5V.

[0157] The working logic of the decoding and error correction module is introduced as follows:

[0158] In the signal detection unit 1, VDD is a 2.5V constant voltage source, and IS1 is constant current source 1. Through Q1, Q5, Q7, Q9, Q12, Q15, Q18, etc., multiple 1:1 mirror currents are formed; constant current source IS2 = 0.1IS1, resistor R2 = R5, R1 = R7, R3 = R6, (the resistance value of resistor R8 is less than that of R3, so that the currents through R8, R3 or R6 are the same, but the voltage drops are different). Resistor R4 is used to adjust the base voltage difference between Q4 and Q6, that is, when the base voltage difference between Q4 and Q6 reaches a preset value and the IC current difference between Q4 and Q6 reaches a preset value, the voltages at points A or B are lower than the voltage at point G. For example, when the voltage of IN2 is higher than the voltage of IN1 by a first preset value, the emitter current of Q6 is greater than the emitter current of Q4. Since the current pulled by Q7 is fixed, the excess current will flow through R4 to Q5. This current is defined as IR4. Then the difference by which the base voltage of Q6 is higher than the base voltage of Q4 is the product of IR4 and the resistance value of R4, which is the first preset value. Since the current flowing through Q4 decreases, the potential at point A rises (higher than the potential at point G), and it can be considered that the signal detection unit 1 outputs a high level. Similarly, if the potential of IN1 is higher than the potential of IN2 by the first preset value, the potential at point B will be higher than the potential at point G, and it can be considered that the signal detection unit 1 outputs a high level. When the voltage difference between the two is less than the first preset value, the emitter current difference between Q4 and Q6 is not significant, both around IS1, so the potentials at points A and B are lower than the potential at point G, and it can be considered that the signal detection unit 1 module outputs a low level.

[0159] In the signal judgment unit 3, the voltage at point C is smaller than the voltage at point B by VBE, and the voltage at point H is smaller than the voltage at point A by VBE; the voltages at points F1 and F2 are lower than the voltage at point G by VBE. Comparing the potentials of A / B and G is equivalent to comparing H / C and F1 / F2. When the voltage at point H is higher than the voltage at point F2, or the voltage at point C is higher than the voltage at point F1, the output terminal J of the signal judgment unit 3 is at a low potential; when the voltage at point H is lower than the voltage at point F2 and the voltage at point C is lower than the voltage at point F1, the output terminal J of the signal judgment unit 3 is at a high potential.

[0160] In the output unit 4, when the input terminal J is at a low potential, DATA OUTA outputs a low level, and at the same time QB is low. At this time, I1 = IQ9 + IQ10; when the input terminal J is at a high potential, DATAOUTA outputs a high level, and at the same time QB is high. At this time, I1 = IQ9. It can be understood that in different embodiments, DATA OUTA can be used as the output pin of the communication chip, or indirectly connected to the first local output pin through other modules to output a signal. The signal at QB is also the second intermediate signal.

[0161] For the reference potential providing unit 2, when the input terminal QB is at a low level, I1 = IQ9 + IQ10, and when the input terminal QB is at a high level, I1 = IQ9; since the voltage at point G = VC - R8 * I1, the voltage at point G corresponding to QB being high is higher than that when QB is low; this potential provides a reference potential for the comparator in the signal determination unit 3. Due to the change in this potential, the corresponding flip points of IN1 and IN2 in the signal detection unit 1 will change, and the glitch signals at IN1 and IN2 can be effectively filtered out. The four units together implement the signal decoding and error correction function.

[0162] The working process of the decoding and error correction module is as follows: The signal detection unit 1 is used to collect the difference signal between signals IN1 and IN2. When the absolute value of the difference in signal amplitude reaches and is greater than the first preset value, a high-level signal is output (either A is high or B is high, where this high is compared with the potential of point G). When the signal judgment unit 3 detects that either A or B is a high-level signal (the high level is relative to the potential of point G), a low-level signal is output. When the output unit 4 detects that the input signal is low, DATAOUTA outputs a low-level signal, and at the same time, the QB signal is low. When the reference potential providing unit 2 detects that QB is low, the current I1 flowing through resistor R8 is I1 = IS1 + IS2, and the voltage at point G is G1 = VCC - I1 * R8. Conversely, when the absolute difference between IN1 and IN2 in the SATAGE1 module is less than the second preset value, the voltage values of output signals A and B are close, but both voltages are lower than the voltage at point G. Then the signal judgment unit 3 outputs a high level, DATA OUTA of the output unit 4 outputs a high level, and at this time, QB is also at a high level. QB conducts, pulling IS2 to ground, so the current I1' on resistor R8 is I1' = IS1 (Q9 and Q1 form a 1:1 current mirror), and the voltage at point G is G2 = VCC - I1' * R8. Since I1 > I1', the voltage G1 < G2. Since DATAOUA flips once, the voltage at point G changes once, that is, the reference voltage of the signal judgment unit 3 also changes once. When the entire large module detects that the bus difference signal reaches and is greater than the first preset value, it starts to flip (realizing that the output DATA OUTA signal is low), and synchronously adjusts the preset voltage value. The preset value decreases (the realized function is that when DATA OUTA outputs a low level, the flip point is adjusted to the second preset value, and when DATAOUTA outputs a high level, the flip point is adjusted to the first preset value. The voltage of the first preset value is greater than the voltage of the second preset value; it can be understood as similar to a hysteresis function). In this way, each time the pressure difference between IN1 and IN2 is greater than the first preset value, it will flip and output, and the DATAOUTA signal will output low, which can avoid misinterpreting the oscillation signal on the bus. Compared with existing products, it will not output misdecoded signals and realizes the decoding and error correction function. Existing products do not have this function. When the bus differential signal changes from high to low, there will be oscillations on the bus, resulting in low-level signals being mixed in the high-level output signal DATA OUTA, affecting the communication quality.

[0163] Please continue to refer to Figure 1 Or Figure 2 , the communication chip further includes the following pins: PIN3 - BC1, PIN4 - BC2 which are bootstrap capacitor pins, PIN5 - RESET which is a reset control input pin, PIN11 - VCC which is a power input pin, PIN13 - GND which is a ground pin, and PIN12 - NC which is a no-connection pin.

[0164] The external connection relationship of the communication chip can be referred to Figure 1 for understanding, and the parameters of external electrical components are also Figure 1 shown in. For some parameters not shown, they can be set according to the common general knowledge in the art and actual needs. It can be understood that the external connection relationship of the communication chip is not limited to only Figure 1 one shown. For example, the PIN5-RESET pin can be connected to a reset control output terminal of a superior control chip to facilitate the overall reset of the system.

[0165] The beneficial effects of this embodiment are analyzed as follows: Problems existing in previous communication solutions: The longer the communication distance and the higher the communication rate, the more severely the signals transmitted on the bus are interfered by the parasitic parameters of the bus, resulting in signal oscillation or distortion, causing high decoding error rate due to abnormal decoding, slow response or inability to communicate of the communication device; Although the bus signal can be improved by adding a matching resistor between the buses of remote nodes, there will still be problems such as inaccurate decoded signals and insufficient high-level pulse width for nodes far from the matching resistor, and dynamic impedance matching resistors cannot be added to each node because it will reduce the bus impedance and cause communication failure. However, the dynamic impedance matching technology proposed in this embodiment is only enabled when the node sends a signal, and other nodes are in the receiving state without affecting the bus impedance, realizing the improvement of the bus signal when each node sends a signal through the dynamic impedance matching technology and improving the decoding accuracy;

[0166] At the same time, the chip for improving the communication effect in this embodiment can also adjust the high-level pulse width of the decoded signal through the signal correction function to avoid the problem of insufficient pulse width of the decoded signal caused by the interference of the bus parasitic parameters; The chip for improving the communication effect in this embodiment also has a decoding error correction function, using a new decoded signal inversion principle to suppress the interference signals received from the bus; By the above multiple functions and from multiple aspects, the interference of the bus parasitic parameters is reduced to ensure the communication quality; Since the solution using this communication chip is hardly affected by the bus parasitic parameters, it can be applied to longer communication distances, higher communication rates and more communication nodes, which is conducive to the upgrade of traditional communication solutions. The chip for improving the communication effect in this embodiment also integrates encoding and decoding functions, eliminating the need for software encoding and decoding, saving MCU resources, having a higher integration degree of the communication chip and richer functions, so it has stronger market competitiveness and higher profit margins.

[0167] In summary, this embodiment provides a communication chip that operates based on a hardware circuit. The communication chip includes: a bus communication pin and an MCU communication pin. The MCU communication pin includes a first local output pin, a second local output pin, and a local signal input pin. The first local output pin is used to output signal 0 or 1 based on the differential value of the twisted pair bus signal received by the bus communication pin. The second local output pin is used to synchronously output signal 0 when the first local output pin outputs signal 01, and synchronously output signal 1 when the first local output pin outputs signal 11. The bus communication pin is used to synchronously output signal 01 when the signal of the local signal input pin is 0, and synchronously output signal 11 when the signal of the local signal input pin is 1. With such a configuration, encoding and decoding are performed in a hardware decoding manner, without software encoding and decoding inside the MCU or other logical control devices, reducing the computational burden on the MCU or other logical control devices, increasing the versatility of the communication chip, and providing a hardware basis for the implementation of other anti-interference functions. The communication chip can improve the communication effect over long distances and solve the problems existing in the prior art.

[0168] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A communication chip, characterized in that: Used for HBS protocol communication, the communication chip works based on hardware circuits, and the communication chip includes: a bus communication pin and an MCU communication pin, and the MCU communication pin includes a first local output pin, a second local output pin and a local signal input pin; The first local output pin is used to output a signal 0 or 1 based on a differential value of the twisted pair bus signal received by the bus communication pin; The second local output pin is used to synchronously output signal 0 when the first local output pin outputs signal 01, and synchronously output signal 1 when the first local output pin outputs signal 11; The bus communication pin is used to synchronously output a signal 01 when the signal of the local signal input pin is 0, and to synchronously output a signal 11 when the signal of the local signal input pin is 1.

2. The communication chip according to claim 1, characterized in that: The communication chip also includes a PWM modulation signal pin, which is used to receive a PWM signal. The communication chip determines a duration of the signal between the bus communication pin and the first local output pin based on half a cycle of the PWM signal, and determines a duration of the signal between the second local output pin and the local signal input pin based on a cycle of the PWM signal.

3. The communication chip according to claim 1, characterized in that: The communication chip further includes an impedance switching switch and a dynamic impedance matching pin, the bus communication pin includes two bus output pins, and in at least one connection mode of the communication chip, the dynamic impedance matching pin is used to connect an external matching resistor; The communication chip is used to connect the matching resistor between the two bus output pins through the impedance switching switch when the output signal of the bus output pin drops from a high level to an intermediate level or rises from a low level to an intermediate level, and is used to disconnect the matching resistor from the bus output pin through the impedance switching switch when the duration after connection reaches a preset time.

4. The communication chip according to claim 1, characterized in that: The bus communication pins include bus output pins, and the bus output pins are provided with voltage regulator tubes for enhancing ESD protection capability.

5. The communication chip according to claim 1, characterized in that: The communication chip further comprises a signal pulse width correction pin, the bus communication pin comprises a bus output pin, and the signal pulse width correction pin is used to connect an external correction resistor; The correction resistor is used to eliminate the influence of bus parasitic parameters to compensate for the high-level output pulse width of the bus output pin.

6. The communication chip according to claim 1, characterized in that: The communication chip includes a decoding error correction module for filtering out oscillations of bus signals, and the bus communication pin includes a bus input pin, and the bus input pin is connected to the MCU communication pin through the decoding error correction module.

7. The communication chip according to claim 6, characterized in that: The decoding error correction module includes a signal detection unit, a signal judgment unit, a reference potential providing unit and an output unit; The signal detection unit is used to convert the twisted pair bus signal received by the bus input pin into two-way first intermediate signals; The reference potential providing unit is used to provide a reference voltage; The signal determination unit is used to compare the first intermediate signal with the reference voltage. When any one of the first intermediate signals is greater than the reference voltage, the signal determination unit outputs a first level, otherwise, the signal determination unit outputs a second level. The output unit is used to change its own output signal accordingly based on the output signal of the signal judgment unit; Wherein, the signal detection unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first constant current source, a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode and an eighth triode; The first end of the first resistor is used to receive one of the twisted pair bus signals, and the first end of the seventh resistor is used to receive the other of the twisted pair bus signals; The first end of the first resistor is connected to the first ends of the second resistor, the fifth resistor and the seventh resistor in sequence, and the connection point between the second resistor and the fifth resistor is also connected to a power supply; The third transistor is an NPN transistor, the emitter of the third transistor is used to connect to a power supply, the base of the third transistor is connected to its collector, and the collector of the third transistor is connected to the second end of the first resistor; The fourth transistor is an NPN transistor, the collector of the fourth transistor is connected to the power supply through the third resistor, the base of the fourth transistor is connected to the second end of the first resistor, and the collector of the fourth transistor is used to output one of the first intermediate signals; The eighth transistor is an NPN transistor, the emitter of the eighth transistor is used to connect to a power supply, the base of the eighth transistor is connected to its collector, and the collector of the eighth transistor is connected to the second end of the seventh resistor; The sixth transistor is an NPN transistor, the collector of the sixth transistor is connected to the power supply through the sixth resistor, the base of the sixth transistor is connected to the second end of the seventh resistor, and the collector of the sixth transistor is used to output another path of the first intermediate signal; The emitter of the fourth transistor is connected to the emitter of the sixth transistor through the fourth resistor; The first transistor is an NPN transistor, the input end of the first constant current source is used to connect to a power supply, the output end of the first constant current source is connected to the collector of the first transistor, and the emitter of the first transistor is used to be grounded; The second transistor is an NPN transistor, the collector of the second transistor is used to connect to a power supply, the base of the second transistor is connected to the collector of the first transistor, and the emitter of the second transistor is connected to the base of the first transistor; The fifth transistor is an NPN transistor, the collector of the fifth transistor is connected to the emitter of the fourth transistor, the base of the fifth transistor is connected to the base of the first transistor, and the emitter of the fifth transistor is grounded; The seventh transistor is an NPN transistor, the collector of the seventh transistor is connected to the emitter of the sixth transistor, the base of the seventh transistor is connected to the base of the first transistor, and the emitter of the seventh transistor is used for grounding.

8. The communication chip according to claim 7, characterized in that: The reference potential providing unit includes an eighth resistor, a second constant current source, a ninth triode, a tenth triode, an eleventh triode, a twelfth triode, a thirteenth triode, a fourteenth triode, a fifteenth triode and a sixteenth triode; The ninth transistor is an NPN transistor, the base of the ninth transistor is connected to the base of the first transistor, and the emitter of the ninth transistor is grounded; The thirteenth transistor is an NPN transistor, the collector of the thirteenth transistor is connected to the collector of the ninth transistor, and the emitter of the thirteenth transistor is used for grounding; The thirteenth transistor is an NPN transistor, the input end of the second constant current source is used to connect to a power supply, the output end of the second constant current source is connected to the collector of the thirteenth transistor, the collector of the thirteenth transistor is connected to its own base, the base of the thirteenth transistor is connected to the base of the thirteenth transistor, and the emitter of the thirteenth transistor is used to be grounded; The sixteenth transistor is an NPN transistor, the collector of the sixteenth transistor is connected to the collector of the thirteenth transistor, the emitter of the sixteenth transistor is used for grounding, and the base of the sixteenth transistor is used for receiving a second intermediate signal, and the second intermediate signal and the output signal of the output unit change simultaneously; The first end of the eighth resistor is used to connect to a power source, and the second end of the eighth resistor is connected to the collector of the ninth transistor; The eleventh transistor is an NPN transistor, the collector of the eleventh transistor is used to connect to a power supply, the base of the eleventh transistor is connected to the second end of the eighth resistor, and the emitter of the eleventh transistor is used to output the reference voltage; The twelfth transistor is an NPN transistor, the collector of the twelfth transistor is connected to the emitter of the eleventh transistor, the emitter of the twelfth transistor is used for grounding, and the base of the twelfth transistor is connected to the base of the first transistor; The fourteenth transistor is an NPN transistor, the collector of the fourteenth transistor is used to connect to a power supply, the base of the fourteenth transistor is connected to the second end of the eighth resistor, and the emitter of the fourteenth transistor is used to output the reference voltage; The fifteenth transistor is an NPN transistor, the collector of the fifteenth transistor is connected to the emitter of the fourteenth transistor, the emitter of the fifteenth transistor is used for grounding, and the base of the fifteenth transistor is connected to the base of the first transistor.

9. The communication chip according to claim 7, characterized in that: The signal determination unit includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twenty-third transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor and a thirty-third transistor; The seventeenth triode, the eighteenth triode, the twenty-third triode, the twenty-second triode, the twenty-third triode, the twenty-fourth triode, the twenty-sixth triode, the twenty-eighth triode, the twenty-ninth triode and the thirty-third triode are all NPN triodes; the nineteenth triode, the twenty-first triode, the twenty-fifth triode and the twenty-seventh triode are all PNP triodes; The collector of the seventeenth transistor is used to connect to a power supply, the collector of the eighteenth transistor is connected to the emitter of the seventeenth transistor, the base of the eighteenth transistor is connected to the base of the first transistor, the first end of the ninth resistor is used to connect to a power supply, the second end of the ninth resistor is connected to the emitter of the nineteenth transistor, the base of the nineteenth transistor is connected to the emitter of the seventeenth transistor, the collector of the twenty-third transistor is connected to the collector of the nineteenth transistor, the collector of the twenty-third transistor is also connected to its own base, and the second The emitter of the triode is used for grounding, the second end of the ninth resistor is also connected to the emitter of the twenty-first triode, the base of the twenty-first triode is used for obtaining the reference voltage, the collector of the twenty-second triode is connected to the collector of the twenty-first triode, the emitter of the twenty-second triode is used for grounding, the base of the twenty-third triode is connected to the collector of the twenty-first triode through the tenth resistor, the emitter of the twenty-third triode is used for grounding, and the collector of the twenty-third triode is configured as the output end of the signal judgment unit; The collector of the twenty-ninth transistor is used to connect to a power supply, the collector of the thirty-third transistor is connected to the emitter of the twenty-ninth transistor, the base of the thirty-third transistor is connected to the base of the first transistor, the first end of the twelfth resistor is used to connect to a power supply, the second end of the twelfth resistor is connected to the emitter of the twenty-seventh transistor, the base of the twenty-seventh transistor is connected to the emitter of the twenty-ninth transistor, the collector of the twenty-eighth transistor is connected to the collector of the twenty-seventh transistor, and the collector of the twenty-eighth transistor is also connected to its own base. The emitter of the twenty-eighth triode is used for grounding, the second end of the twelfth resistor is also connected to the emitter of the twenty-fifth triode, the base of the twenty-fifth triode is used for obtaining the reference voltage, the collector of the twenty-sixth triode is connected to the collector of the twenty-fifth triode, the emitter of the twenty-sixth triode is used for grounding, the base of the twenty-fourth triode is connected to the collector of the twenty-fifth triode through the eleventh resistor, the emitter of the twenty-fourth triode is used for grounding, and the collector of the twenty-fourth triode is connected to the collector of the twenty-third triode; The base of the twenty-ninth transistor is used to receive one path of the first intermediate signal, and the base of the seventeenth transistor is used to receive the other path of the one intermediate signal.

10. The communication chip according to claim 7, characterized in that: The output unit includes a thirteenth resistor, a fourteenth resistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, a forty-third transistor, a forty-first transistor and a forty-second transistor; The thirty-first transistor is a PNP transistor, and the emitter of the thirty-first transistor is used to connect to a power supply; The thirty-second transistor is an NPN transistor, the collector of the thirty-second transistor is connected to the collector of the thirty-first transistor, the emitter of the thirty-second transistor is used for grounding, the collector of the thirty-second transistor is used for outputting a second intermediate signal, the second intermediate signal and the output signal of the output unit change simultaneously, and the second intermediate signal is used for providing a basis for logic judgment for other units of the decoding and error correction module; The thirty-third triode is a PNP triode, the emitter of the thirty-third triode is used to connect to a power supply, the base of the thirty-third triode is connected to the base of the thirty-first triode, and the collector of the thirty-third triode is connected to the base of the thirty-second triode; The thirty-fourth triode is an NPN triode, the collector of the thirty-fourth triode is connected to the collector of the thirty-third triode, and the emitter of the thirty-fourth triode is grounded; The thirty-fifth transistor is a PNP transistor, the emitter of the thirty-fifth transistor is used to connect to a power supply, the base of the thirty-fifth transistor is connected to the base of the thirty-first transistor, the collector of the thirty-fifth transistor is connected to the base of the thirty-fourth transistor through the thirteenth resistor, and the collector of the thirty-fifth transistor is also connected to the output end of the signal judgment unit; The thirty-sixth transistor is a PNP transistor, the emitter of the thirty-sixth transistor is used to connect to a power supply, and the base of the thirty-sixth transistor is connected to the base of the thirty-first transistor; The thirty-seventh transistor is an NPN transistor, the collector of the thirty-seventh transistor is connected to the collector of the thirty-sixth transistor, the base of the thirty-seventh transistor is connected to the collector of the thirty-fifth transistor through the fourteenth resistor, and the emitter of the thirty-seventh transistor is grounded; The thirty-eighth transistor is a PNP transistor, the emitter of the thirty-eighth transistor is used to connect to a power supply, and the base of the thirty-eighth transistor is connected to the base of the thirty-first transistor; The thirty-ninth transistor is an NPN transistor, the collector of the thirty-ninth transistor is connected to the collector of the thirty-eighth transistor, the base of the thirty-ninth transistor is connected to the collector of the thirty-sixth transistor, the emitter of the thirty-ninth transistor is used for grounding, and the collector of the thirty-ninth transistor is also configured as the output end of the output unit; The forty-third transistor is a PNP transistor, the emitter of the forty-third transistor is connected to the base of the thirty-first transistor, and the collector of the forty-third transistor is grounded; The forty-first transistor is a PNP transistor, the emitter of the forty-first transistor is used to connect to a power supply, and the collector of the forty-first transistor is connected to the base of the forty-third transistor; The 42nd transistor is an NPN transistor, the collector of the 42nd transistor is connected to the collector of the 41st transistor, the base of the 42nd transistor is connected to the base of the first transistor, and the emitter of the 42nd transistor is used for grounding.

Images