Passivation contact structure, solar cell and photovoltaic module

Abstract

The utility model discloses a passivation contact structure, a solar cell and a photovoltaic module, and the passivation contact structure comprises a dielectric layer with the thickness of 1-2.5 nm; the doped silicon carbide layer is stacked on the surface of the dielectric layer, and the thickness of the doped silicon carbide layer is 3-40nm; and the first doped polycrystalline silicon layer is stacked on the surface of the doped silicon carbide layer, and the thickness of the first doped polycrystalline silicon layer is 5nm-50nm. The passivation contact structure not only can form ohmic contact with the first electrode, but also can prevent the dielectric layer from being damaged, and is beneficial to further improvement of the conversion efficiency of the solar cell.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and particularly to a passivated contact structure, a solar cell, and a photovoltaic module. Background Art

[0002] The back surface of a solar cell usually forms a passivated contact structure with a dielectric layer and a doped polysilicon layer, and a metal electrode forms an ohmic contact with the doped polysilicon layer through electrode paste sintering. Increasing the thickness of the doped polysilicon layer can effectively prevent the electrode paste from penetrating the doped polysilicon layer during sintering, damaging the underlying dielectric layer and causing a decrease in the passivation effect. Therefore, people generally choose to increase the thickness of the polysilicon layer to reduce the risk of the electrode paste burning through. However, when the thickness of the doped polysilicon layer is higher, the parasitic absorption is also higher, which is not conducive to improving the cell efficiency. Summary of the Invention

[0003] The present application provides a passivated contact structure, a solar cell, and a photovoltaic module. This passivated contact structure can not only form an ohmic contact with the electrode, but also avoid damaging the dielectric layer, and can also reduce parasitic absorption, which is beneficial to further improving the conversion efficiency of the solar cell.

[0004] In a first aspect, an embodiment of the present application provides a passivated contact structure.

[0005] This passivated contact structure includes:

[0006] A dielectric layer with a thickness of 1 nm to 2.5 nm;

[0007] A doped silicon carbide layer stacked on the surface of the dielectric layer, with a thickness of 3 nm to 40 nm;

[0008] A first doped polysilicon layer stacked on the surface of the doped silicon carbide layer, with a thickness of 5 nm to 50 nm.

[0009] As an optional implementation manner, in an embodiment of the present invention, the thickness of the dielectric layer is 1.5 nm to 2.5 nm; and / or, the thickness of the first doped polysilicon layer is 15 nm to 35 nm, and the thickness of the doped silicon carbide layer is 5 nm to 25 nm.

[0010] As an optional implementation manner, in an embodiment of the present invention, the edge of the doped silicon carbide layer covers the edge of the dielectric layer, and the doping elements of the doped silicon carbide layer and the first doped polysilicon layer are one or more of phosphorus, arsenic, antimony, or gallium.

[0011] As an alternative embodiment, in the embodiments of the present invention, a second doped polysilicon layer is further provided between the dielectric layer and the doped silicon carbide layer. The thickness of the second doped polysilicon layer is 5 nm to 150 nm, and the doping element concentration of the second doped polysilicon layer is lower than that of the first doped polysilicon layer.

[0012] As an alternative embodiment, in the embodiments of the present invention, the concentration of the doping element in the first doped polysilicon layer is 8×10 20 ~3×10 20 / cm -3 ; and / or, the doping concentration of the doping element in the second doped polysilicon layer is 2×10 20 ~6×10 20 / cm -3 ; and / or, the doping concentration of the doping element in the doped silicon carbide layer is 5×10 20 ~1×10 21 / cm -3 .

[0013] As an alternative embodiment, in the embodiments of the present invention, the concentration of the doping element in the first doped polysilicon layer is 1×10 21 ~3×10 21 / cm -3 ; and / or, the doping concentration of the doping element in the second doped polysilicon layer is 2×10 20 ~5×10 20 / cm -3 .

[0014] As an alternative embodiment, in the embodiments of the present invention, the dielectric layer is a silicon oxide layer.

[0015] In a second aspect, an embodiment of the present application provides a solar cell.

[0016] A solar cell includes the passivation contact structure as described in the first aspect.

[0017] As an alternative embodiment, in the embodiments of the present invention, the solar cell is a passivation contact solar cell, and the passivation contact solar cell includes:

[0018] A silicon wafer;

[0019] A passivation contact structure, in which the dielectric layer in the passivation contact structure is stacked on the backlight surface of the silicon wafer;

[0020] A first electrode, and the first doped polysilicon layer and the doped silicon carbide layer in the passivation contact structure simultaneously form an ohmic contact with the first electrode.

[0021] As an alternative embodiment, in the embodiments of the present invention, when the silicon wafer is of N-type, the conduction types of the first doped polysilicon layer, the doped silicon carbide layer, and the second doped polysilicon layer are N-type; when the silicon wafer is of P-type, the conduction types of the first doped polysilicon layer, the doped silicon carbide layer, and the second doped polysilicon layer are P-type.

[0022] As an alternative embodiment, in the embodiments of the present invention, the resistivity of the silicon wafer is 0.3 Ω·cm to 7 Ω·cm; and / or, a first functional layer is further stacked on a side of the first doped polysilicon layer away from the silicon wafer, and the first electrode penetrates through the first functional layer to make an ohmic contact with both the first doped polysilicon layer and the doped silicon carbide layer.

[0023] As an alternative embodiment, in the embodiments of the present invention, the first functional layer is a first antireflection layer, and the thickness of the first antireflection layer is 60 nm to 130 nm; and / or, the material of the first antireflection layer is one or a combination of silicon nitride, silicon oxynitride, and silicon oxide.

[0024] As an alternative embodiment, in the embodiments of the present invention, the passivated contact solar cell further includes a doped layer and a second functional layer that are sequentially stacked on a light-receiving surface side of the silicon wafer.

[0025] As an alternative embodiment, in the embodiments of the present invention, the doping concentration of the doped layer is 3×10 18 / cm -3 ~3×10 19 / cm -3 ; and / or, the sheet resistance of the doped layer is 40 Ω / sq to 300 Ω / sq.

[0026] As an alternative embodiment, in the embodiments of the present invention, the second functional layer is a passivation layer and a second antireflection layer stacked on the doped layer.

[0027] As an alternative embodiment, in the embodiments of the present invention, the material of the passivation layer is aluminum oxide; and / or, the material of the second antireflection layer is one or a combination of silicon nitride, silicon oxynitride, and silicon oxide; and / or, the thickness of the passivation layer is 2 nm to 7 nm; and / or, the thickness of the second antireflection layer is 60 nm to 130 nm.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] A passivation contact structure provided by an embodiment of the present invention. In this application, a doped silicon carbide layer is disposed between a first doped polysilicon layer and a dielectric layer. The doped silicon carbide layer has high-temperature etching stability and good resistance to electrode paste ablation. On the one hand, the contact performance between the electrode paste and the first doped polysilicon layer is excellent, while the contact performance with the doped silicon carbide layer is relatively poor. The electrode paste contacts the first doped polysilicon layer through ablation, which is beneficial to reducing the contact resistance of the electrode and improving the carrier transport effect. On the other hand, the doped silicon carbide layer of the above thickness is not easily burned through during the ablation of the electrode paste. Therefore, this application can reduce the thickness of the doped polysilicon layer, realize the reduction of parasitic absorption, and at the same time effectively reduce the risk that the metal elements of the electrode paste diffuse into the silicon wafer by burning through the relatively thin dielectric layer, so that it is not easy to damage the silicon wafer interface and increase the interface defects and interface passivation of the silicon wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 is a schematic structural diagram of a solar cell disclosed in an embodiment of the present invention;

[0032] Figure 2 is a schematic structural diagram of another solar cell disclosed in an embodiment of the present invention.

[0033] Reference numerals: 1, silicon wafer; 2, dielectric layer; 3, doped silicon carbide layer; 41, first doped polysilicon layer; 42, second doped polysilicon layer; 5, first antireflection layer; 6, doped layer; 7, passivation layer; 8, second antireflection layer; 9, second electrode; 10, first electrode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0035] In the present invention, the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", etc. is based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit that the indicated device, element or component must have a specific orientation, or be constructed and operated in a specific orientation.

[0036] Moreover, in addition to being used to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0037] In addition, the terms "mounted", "arranged", "provided with", "connected", "linked" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there can be internal communication between two devices, elements or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] In addition, the terms "first", "second", etc. are mainly used to distinguish different devices, elements or components (the specific types and structures may be the same or different), and are not used to indicate or imply the relative importance and quantity of the indicated devices, elements or components. Unless otherwise specified, the meaning of "a plurality" is two or more.

[0039] The doped polysilicon layer is one of the important film layers that affect solar cells (especially passivated contact solar cells). Limited by the thickness setting requirements of the doped polysilicon layer, it is difficult to further optimize the performance of the doped polysilicon layer, and it is difficult to further improve the performance of solar cells. The reason for the limitation in the thickness setting of the doped polysilicon layer is that although increasing the thickness of the doped polysilicon layer is beneficial to reducing the risk of electrode paste burn-through, it increases parasitic absorption; while reducing the thickness of the doped polysilicon layer can reduce parasitic absorption, but it makes the electrode paste extremely easy to burn through the doped polysilicon layer, and when the doped polysilicon layer is burned through, it is often easy to further damage the dielectric layer with a thickness of 1 nm to 2.5 nm, resulting in the diffusion of metal elements in the electrode paste to the surface of the silicon wafer, causing a decrease in the interface passivation effect in the passivated contact structure. In currently mass-produced solar cells, the thickness of the doped polysilicon layer needs to be set between 100 nm and 150 nm. If the doped polysilicon layer is further thinned, the risk of the electrode paste burning through the doped polysilicon layer increases. It can be seen that the above limitations make it difficult to thin the doped polysilicon layer.

[0040] To overcome the above problems, the present application provides a passivated contact structure, a solar cell, and a photovoltaic module. This passivated contact structure can not only ensure good ohmic contact between the doped polysilicon layer and the electrode, but also reduce parasitic absorption and the risk of dielectric layer breakdown, avoid damage to the dielectric layer, and is conducive to further improving the photoelectric conversion efficiency of the solar cell.

[0041] The technical solutions of the present invention will be further described below with reference to embodiments and drawings.

[0042] In a first aspect, an embodiment of the present application provides a passivated contact structure.

[0043] Referring to Figure 1 , the passivated contact structure includes:

[0044] A dielectric layer 2 with a thickness of 1 nm to 2.5 nm;

[0045] A doped silicon carbide layer stacked on the surface of the dielectric layer, with a thickness of 3 nm to 40 nm;

[0046] A first doped polysilicon layer stacked on the surface of the doped silicon carbide layer, with a thickness of 5 nm to 50 nm.

[0047] In the present application, the doped silicon carbide layer 3 is disposed between the first doped polysilicon layer 41 and the dielectric layer 2. The doped silicon carbide layer 3 has high-temperature etching stability and good resistance to electrode paste ablation. On the one hand, the contact performance between the electrode paste and the first doped polysilicon layer 41 is excellent, while the contact performance with the doped silicon carbide layer 3 is relatively poor. The electrode paste can contact the first doped polysilicon layer through ablation, which is beneficial to reducing the contact resistance of the electrode and improving the carrier transport effect;

[0048] On the other hand, the electrode paste is not easily burned through the doped silicon carbide layer 3. Therefore, the present application can reduce the thickness of the first doped polysilicon layer, achieve a reduction in parasitic absorption, and at the same time effectively reduce the risk that the electrode paste burns through the relatively thin dielectric layer 2 and the metal elements in the electrode paste diffuse into the silicon wafer 1 in contact with the dielectric layer 2, thereby not easily causing problems such as damaging the interface of the silicon wafer 1 and increasing the interface defects of the silicon wafer 1.

[0049] In some embodiments, the thickness of the dielectric layer is 1.5 nm to 2.5 nm; and / or, the thickness of the first doped polysilicon layer is 15 nm to 35 nm, and the thickness of the doped silicon carbide layer is 5 nm to 25 nm.

[0050] In some embodiments, the edge of the doped silicon carbide layer 3 covers the edge of the dielectric layer 2, and the doping elements of the doped silicon carbide layer 3 and the first doped polysilicon layer 41 are one or more of phosphorus, arsenic, antimony, or gallium.

[0051] Preferably, the doping element is phosphorus. The solid solubility of phosphorus in the silicon carbide layer is significantly lower than that in the polysilicon layer. When the edge of the doped silicon carbide layer 3 covers the edge of the dielectric layer 2, during the high-temperature annealing process, the doped silicon carbide layer 3 can effectively block the diffusion of phosphorus in the first doped polysilicon layer 41 into the dielectric layer 2, reducing the doping concentration of phosphorus in the dielectric layer 2, thereby improving the passivation effect of the dielectric layer 2.

[0052] Referring to Figure 2 , in some embodiments, a second doped polysilicon layer 42 is further provided between the dielectric layer 2 and the doped silicon carbide layer 3, and the doping element concentration of the second doped polysilicon layer 42 is lower than that of the first doped polysilicon layer 41.

[0053] Before the annealing treatment, the first doped polysilicon layer 41 corresponds to a first doped amorphous silicon layer, the doped silicon carbide layer 3 corresponds to a doped amorphous silicon carbide layer, and the second doped polysilicon layer 42 corresponds to a second doped amorphous silicon layer or a second intrinsic amorphous silicon layer. During the annealing treatment, not only does the first doped amorphous silicon material transform into the first doped polysilicon layer 41 at high temperature, but also due to the relatively high doping element concentration in the first doped amorphous silicon layer, it is prone to diffuse towards the doped amorphous silicon carbide layer, the second doped amorphous silicon layer or the second intrinsic amorphous silicon layer with a relatively low doping element concentration, causing some doping elements in the first doped amorphous silicon layer to enter the doped amorphous silicon carbide layer and form the doped silicon carbide layer 3, and an even smaller amount of doping elements to enter the second doped amorphous silicon layer or the second intrinsic amorphous silicon layer and form the second doped polysilicon layer 42. Therefore, the doping element concentration of the second doped polysilicon layer 42 is lower than that of the first doped polysilicon layer 41.

[0054] By providing the above-mentioned second doped polysilicon layer 42, the concentration of doping elements in the dielectric layer 2 can be further reduced, and the probability of doping elements diffusing through the relatively thin dielectric layer 2 into the silicon wafer 1 can be decreased. In addition, the second doped polysilicon layer 42 can also serve as a barrier layer for the doped silicon carbide layer 3, reducing the probability of carbon elements in the doped silicon carbide layer 3 diffusing into the dielectric layer 2 and the probability of carbon elements passing through the dielectric layer 2 into the silicon wafer 1, thereby reducing the possibility of the structure of the dielectric layer 2 being damaged and its passivation performance being affected.

[0055] In some embodiments, the concentration of the doping element in the first doped polysilicon layer is 8×10 20 ~3×10 21 / cm -3 ; and / or, the doping concentration of the doping element in the second doped polysilicon layer is 2×10 20 ~6×10 20 / cm -3; and / or, the doping concentration of the doping element in the doped silicon carbide layer is 5×10 20 ~1×10 21 / cm -3 。

[0056] Increasing the doping concentration of the first doped polysilicon layer 41 is an effective way to improve the electrical contact performance between the first doped polysilicon layer 41 and the electrode material. Raising the concentration of the doping element in the first doped polysilicon layer 41 to the above range is conducive to enhancing the contact performance between the first doped polysilicon layer 41 and the electrode material. Combining with the blocking effect of the doped silicon carbide layer 3 on the diffusion of phosphorus element, the doping element in the first doped polysilicon layer 41 is not easily penetrated through the doped silicon carbide layer and the second doped polysilicon layer. Therefore, through the above settings, both the contact performance between the first doped polysilicon layer 41 and the electrode is improved, and the problem of the increase in the defects on the surface of the silicon wafer 1 caused by the diffusion of phosphorus element into the dielectric layer 2 is avoided.

[0057] Further preferably, the doping concentration of the doping element in the first doped polysilicon layer is 1×10 21 / cm -3 ~3×10 21 / cm -3 ; and / or, the doping concentration of the doping element in the second doped polysilicon layer after doping is 2×10 20 / cm -3 ~5×10 20 / cm -3 。

[0058] Furthermore, the thickness of the second doped polysilicon layer is 5 nm to 15 nm.

[0059] The temperature required for crystallization of the above-mentioned doped amorphous silicon carbide layer is relatively high. During the annealing and crystallization process, the phosphorus element and carbon element in the doped amorphous silicon carbide layer are likely to diffuse toward the silicon wafer, resulting in a poor passivation effect on the surface of the silicon wafer; when the annealing temperature is low, the crystallization effect of silicon carbide is poor, and direct contact with the dielectric layer is likely to cause large tunneling and lateral resistance, and the process window is small. Therefore, in this application, the second doped polysilicon layer is arranged between the doped silicon carbide layer and the dielectric layer, which not only avoids the poor passivation effect of the contact interface between the doped silicon carbide and the dielectric layer when the annealing temperature is high, but also can effectively increase the process window of the doped silicon carbide when the annealing temperature is low, and improve the passivation quality and process operability of the passivation contact structure.

[0060] In some embodiments, the material of the dielectric layer 2 may include a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the dielectric layer 2 may be composed of a silicon oxide layer. This is because the silicon oxide layer has excellent passivation performance, can minimize the recombination rate of minority carriers on the surface of the semiconductor substrate, and is a film with excellent durability for subsequent high-temperature processes.

[0061] The dielectric layer 2 can act as a pinhole channel, enabling the free movement of carriers in the solar cell, selectively passing the majority carriers through the first doped polycrystalline silicon, increasing the distribution concentration of minority carriers between the solar cell substrate and the first doped polycrystalline silicon, and facilitating the reduction of recombination losses of minority carriers. Additionally, the dielectric layer 2 can be used as a diffusion barrier to prevent the doping elements of the first doped polycrystalline silicon layer or the second doped polycrystalline silicon layer from diffusing into the silicon wafer.

[0062] In a second aspect, an embodiment of the present application provides a solar cell.

[0063] A solar cell includes a passivation contact structure as in the first aspect.

[0064] In some embodiments, the solar cell is a passivation contact solar cell, and the passivation contact solar cell includes:

[0065] A silicon wafer 1;

[0066] A passivation contact structure, in which the dielectric layer 2 is stacked on the backlight surface of the silicon wafer 1;

[0067] A first electrode 10, and an ohmic contact is formed between the first doped polycrystalline silicon layer 41 in the passivation contact structure and the first electrode 10.

[0068] In some embodiments, when the silicon wafer 1 is N-type, the conduction types of the first doped polycrystalline silicon layer 41, the doped silicon carbide layer 3, and the second doped polycrystalline silicon layer 42 are N-type; when the silicon wafer 1 is P-type, the conduction types of the first doped polycrystalline silicon layer 41, the doped silicon carbide layer 3, and the second doped polycrystalline silicon layer 42 are P-type.

[0069] When the conduction types of the first doped polycrystalline layer, the doped silicon carbide layer 3, and the second doped polycrystalline silicon layer 42 are N-type, the doping element of the first doped polycrystalline layer, the doped silicon carbide layer 3, and the second doped polycrystalline silicon layer 42 is phosphorus; when the conduction types of the first doped polycrystalline layer, the doped silicon carbide layer 3, and the second doped polycrystalline silicon are P-type, the doping element of the first doped polycrystalline layer, the doped silicon carbide layer 3, and the second doped polycrystalline silicon layer 42 is boron.

[0070] In some embodiments, the resistivity of the silicon wafer 1 is 0.3 Ω·cm to 7 Ω·cm; and / or, a first functional layer is further stacked on the side of the first doped polysilicon layer 41 away from the silicon wafer 1.

[0071] In some embodiments, the first functional layer is a first antireflection layer 5, and the thickness of the first antireflection layer 5 is 60 nm to 130 nm; and / or, the material of the first antireflection layer 5 is one or a combination of silicon nitride, silicon oxynitride, and silicon oxide.

[0072] In some embodiments, the passivated contact solar cell further includes a doped layer 6 and a second functional layer sequentially stacked on the light-receiving surface side of the silicon wafer 1.

[0073] In some embodiments, the second functional layer is a passivation layer 7 and a second antireflection layer 8 stacked on the doped layer 6.

[0074] In some embodiments, the doping concentration of the doped layer 6 is 3×10 18 / cm -3 ~3×10 19 / cm -3 ; and / or, the sheet resistance of the doped layer 6 is 40 Ω / sq to 300 Ω / sq; and / or, the thickness of the passivation layer 7 is 2 nm to 7 nm; and / or, the thickness of the second antireflection layer 8 is 60 nm to 130 nm.

[0075] In some embodiments, the material of the passivation layer 7 is aluminum oxide, and the material of the second antireflection layer 8 is one or a combination of silicon nitride, silicon oxynitride, and silicon oxide.

[0076] Next, the preparation method of the solar cell according to the embodiments of the present application will be introduced.

[0077] The preparation method of the solar cell includes the following steps:

[0078] Double-sided texturing: Provide an N-type silicon wafer 1 with a resistivity of 0.3 Ω·cm to 7 Ω·cm, and use alkaline texturing to form a pyramid-shaped textured surface with a height of 0.5 μm to 3 μm on the light-receiving surface and the backlight surface of the N-type silicon wafer 1;

[0079] Prepare the doped layer 6: Use plasma enhanced chemical vapor deposition (PECVD) to deposit a layer of boron-doped amorphous silicon on the light-receiving surface of the N-type silicon wafer 1, and obtain the doped layer 6 after annealing treatment;

[0080] Backside polishing: Use a single-sided chain equipment to remove the silicon oxide on the backlight surface of the N-type silicon wafer 1 with hydrofluoric acid, then remove the edge plating and the backlight surface plating of the N-type silicon wafer 1 by alkaline polishing, and finally perform a cleaning treatment;

[0081] Fabrication of a passivated contact structure:

[0082] Fabrication of dielectric layer 2: Deposit a dielectric layer 2 on the back surface by plasma-enhanced chemical vapor deposition. The dielectric layer 2 is a silicon oxide layer, and the reaction gas for depositing the dielectric layer 2 can be nitrous oxide, can be a combination of nitrous oxide and argon, or can be carbon dioxide;

[0083] Fabrication of a doped amorphous silicon carbide layer: Deposit a doped amorphous silicon carbide layer by plasma-enhanced chemical vapor deposition, or deposit multiple lightly doped amorphous silicon carbide layers with different doping concentrations; The reaction gases are silane, methane, phosphine, and hydrogen. Among them, the gas flow rate of silane is 1000 mL / min to 4000 mL / min, the gas flow rate of methane is 1000 mL / min to 4000 mL / min, the gas flow rate of phosphine is 100 mL / min to 1500 mL / min, the gas flow rate of hydrogen is 6000 mL / min to 15000 mL / min, the gas flow rate ratio of silane to methane is 2:1 to 0.5:1, the deposition power is 4000 W to 20000 W, and the deposition pressure is 150 Pa to 500 Pa; Hydrogen can also be replaced by argon;

[0084] Fabrication of a first doped amorphous silicon layer: Deposit a doped amorphous silicon layer by plasma-enhanced chemical vapor deposition, or deposit multiple heavily doped amorphous silicon layers with different doping concentrations; The reaction gases are silane, phosphine, and hydrogen. Among them, the gas flow rate of silane is 1000 mL / min to 4000 mL / min, the gas flow rate of phosphine is 100 mL / min to 1500 mL / min, and the gas flow rate of hydrogen is 6000 mL / min to 15000 mL / min;

[0085] Fabrication of a silicon oxide mask;

[0086] Annealing: Perform annealing treatment in a furnace. The annealing temperature is 880 °C to 980 °C, preferably 900 °C to 950 °C. After annealing, the crystallization rate of the second doped amorphous silicon layer, the doped amorphous silicon carbide layer, and the first doped amorphous silicon layer increases, and they are transformed into a second doped polycrystalline silicon layer 42, a doped silicon carbide layer 3, and a first doped polycrystalline silicon layer 41;

[0087] Removing the overplating and cleaning: Use a single-sided chain equipment to remove the silicon oxide mask on the light-receiving surface of the N-type silicon wafer 1 with hydrofluoric acid, then remove the overplating on the edge and the light-receiving surface of the N-type silicon wafer 1 by alkaline polishing, and finally perform wet chemical cleaning treatment;

[0088] Fabrication of the passivation layer 7: Deposit the passivation layer 7 on the doped layer 6 by atomic layer deposition (ALD);

[0089] Fabricating an antireflection layer: The first antireflection layer 5 is deposited on the first doped polysilicon layer 41 on the backlight side of the N-type silicon wafer 1, and the second antireflection layer 8 is deposited on the surface of the passivation layer 7 on the light-receiving side of the N-type silicon wafer 1 by plasma-enhanced chemical vapor deposition method;

[0090] Fabricating metal electrodes: The first electrode 10 and the second electrode 9 are printed by screen printing, and then sintered and photo-injected, or electro-injection is used to replace photo-injection to form an ohmic contact between the first electrode 10 and the first doped polysilicon layer 41 and the doped silicon carbide 3 layer at the same time, and an ohmic contact between the second electrode 9 and the doped layer 6.

[0091] Preferably, before fabricating the doped amorphous silicon carbide layer, a second doped amorphous silicon layer is fabricated first, and the fabrication method of the second doped amorphous silicon layer is as follows:

[0092] The second doped polysilicon layer 42 can be deposited with a lightly doped amorphous silicon layer by plasma-enhanced chemical vapor deposition method, or multiple lightly doped amorphous silicon layers with different doping concentrations can be deposited. The reaction gases are silane, phosphine and hydrogen, where the gas flow rate of silane is 1000 mL / min to 4000 mL / min, the gas flow rate of phosphine is 100 mL / min to 1500 mL / min, and the gas flow rate of hydrogen is 6000 mL / min to 15000 mL / min;

[0093] In a third aspect, the present application provides a photovoltaic module.

[0094] A photovoltaic module includes a solar cell as mentioned in the second aspect.

[0095] The technical solution of the present invention will be further described below in conjunction with more specific embodiments and drawings.

[0096] Embodiment 1

[0097] The embodiment of the present application provides a passivated contact solar cell, including:

[0098] An N-type silicon wafer, including a light-receiving side and a backlight side opposite to the light-receiving side;

[0099] A boron-doped layer, disposed on one side of the N-type silicon wafer on the light-receiving side, with a boron doping concentration of 3.5×10 18 / cm -3 , and a sheet resistance of 130 Ω / sq;

[0100] A passivation layer, stacked on the side of the boron-doped layer away from the N-type silicon wafer. The passivation layer is an alumina layer with a thickness of 4 nm;

[0101] A passivated contact structure, including:

[0102] A dielectric layer disposed on the backlight side of the N-type silicon wafer, the dielectric layer being a silicon oxide layer with a thickness of 1.5 nm;

[0103] A doped silicon carbide layer stacked on the side of the dielectric layer facing away from the N-type silicon wafer, the phosphorus doping concentration of the doped silicon carbide layer being 7.5×10 20 / cm -3 , with a thickness of 20 nm;

[0104] A first doped polysilicon layer stacked on the side of the doped silicon carbide layer facing away from the N-type silicon wafer, the phosphorus doping concentration in the first doped polysilicon layer being 1×10 21 / cm -3 , with a thickness of 25 nm;

[0105] A first anti-reflection layer stacked on the side of the first doped polysilicon facing away from the N-type silicon wafer, the first anti-reflection layer being a silicon nitride layer with a thickness of 70 nm;

[0106] A second anti-reflection layer stacked on the side of the passivation layer facing away from the N-type silicon wafer, the second anti-reflection layer being a silicon nitride layer with a thickness of 70 nm;

[0107] A first electrode passing through the first anti-reflection layer to form an ohmic contact with the first doped polysilicon layer and the doped silicon carbide layer, the first electrode being a silver electrode;

[0108] A second electrode passing through the second anti-reflection layer and the passivation layer to form an ohmic contact with the doped layer, the second electrode being a silver electrode.

[0109] The preparation method of the above passivated contact solar cell includes the following steps:

[0110] Double-sided texturing: Provide an N-type silicon wafer with a resistivity of 0.5 Ω·cm, and use alkaline texturing to form a pyramid-shaped textured surface with a height of 2 μm on the light-receiving surface and the backlight surface of the N-type silicon wafer;

[0111] Prepare the doped layer: Use plasma enhanced chemical vapor deposition (PECVD) to deposit a layer of boron-doped amorphous silicon on the light-receiving surface of the N-type silicon wafer, and obtain the doped layer after annealing treatment;

[0112] Backside polishing: Use a single-sided chain equipment to remove the silicon oxide on the backlight side of the N-type silicon wafer with hydrofluoric acid, then remove the edge and the overplating on the backlight side of the N-type silicon wafer by alkaline polishing, and finally clean and process it by wet chemical cleaning method;

[0113] Prepare the passivated contact structure, and the passivated contact structure is prepared by plasma enhanced chemical vapor deposition method, specifically as follows:

[0114] Preparation of dielectric layer: The reaction gas for depositing the dielectric layer is nitrous oxide;

[0115] Preparation of doped amorphous silicon carbide layer: The reaction gases are silane, methane, phosphine and hydrogen. Among them, the gas flow rate of silane is 2500 mL / min, the gas flow rate of methane is 2500 mL / min, the gas flow rate of phosphine is 600 mL / min phosphine, the gas flow rate of hydrogen is 8000 mL / min, the deposition power is 8000 W, and the deposition pressure is 420 Pa;

[0116] Preparation of the first doped amorphous silicon layer: The reaction gases are silane, phosphine and hydrogen. Among them, the gas flow rate of silane is 3000 mL / min, the gas flow rate of phosphine is 600 mL / min phosphine, the gas flow rate of hydrogen is 9000 mL / min, the deposition pressure is 420 Pa, and the deposition power is 8000 W;

[0117] Preparation of silicon oxide mask: Using silane and nitrous oxide, the deposition pressure is 180 Pa, the deposition power is 9000 W, the silane flow rate is 1800 mL / min, the nitrous oxide flow rate is 9000 mL / min, and a silicon oxide mask with a thickness of 7 nm is obtained;

[0118] Annealing: Annealing treatment is carried out in a furnace. The annealing temperature is 930 °C and the time is 45 min. After annealing, the crystallization rate of the second doped amorphous silicon layer, doped amorphous silicon carbide layer and the first doped amorphous silicon layer is increased, and they are transformed into the second doped polycrystalline silicon layer, doped silicon carbide layer and the first doped polycrystalline silicon layer;

[0119] Removing the edge plating and cleaning: Using a single-sided chain equipment, hydrofluoric acid is used to remove the silicon oxide on the light-receiving surface of the N-type silicon wafer. Then, the edge plating of the N-type silicon wafer and the light-receiving surface is removed by alkaline polishing. Finally, wet chemical cleaning is used for cleaning treatment;

[0120] Preparation of passivation layer: The passivation layer is deposited on the doped layer by atomic layer deposition (ALD);

[0121] Preparation of antireflection layer: Plasma enhanced chemical vapor deposition method is used to deposit the first antireflection layer on the first doped polycrystalline silicon layer on the backlight surface of the N-type silicon wafer, and the second antireflection layer is deposited on the surface of the passivation layer on the light-receiving surface of the N-type silicon wafer;

[0122] Preparation of metal electrodes: The first electrode and the second electrode are printed by screen printing, and then sintering and light injection treatment are carried out to make the first electrode form an ohmic contact with the first doped polycrystalline silicon layer and the doped silicon carbide layer at the same time, and the second electrode forms an ohmic contact with the doped layer.

[0123] Example 2

[0124] An embodiment of the present application provides a passivated contact solar cell, which is different from that of Embodiment 1 in that a second doped polysilicon layer with a thickness of 20 nm is provided between the dielectric layer and the doped silicon carbide layer.

[0125] The steps for preparing the passivated contact structure are as follows:

[0126] Prepare the dielectric layer: The reaction gas for depositing the dielectric layer is nitrous oxide, the deposition pressure is 140 Pa, the gas flow rate is 12000 mL / min, and the deposition power is 12000 W;

[0127] Prepare the second doped amorphous silicon layer:

[0128] Deposit a 5-nm intrinsic amorphous silicon layer and a 15-nm phosphorus-doped amorphous silicon layer. The reaction gas for the intrinsic amorphous silicon layer is silane and hydrogen, where the gas flow rate of silane is 2500 mL / min and the gas flow rate of hydrogen is 9000 mL / min, the deposition pressure is 350 Pa, and the deposition power is 7000 W. The reaction gas for the phosphorus-doped amorphous silicon layer is silane, phosphine, and hydrogen, where the gas flow rate of silane is 3000 mL / min, the gas flow rate of phosphine is 600 mL / min, and the gas flow rate of hydrogen is 9000 mL / min, the deposition pressure is 420 Pa, and the deposition power is 8000 W;

[0129] Prepare the doped amorphous silicon carbide layer: The reaction gases are silane, methane, phosphine, and hydrogen, where the gas flow rate of silane is 2500 mL / min, the gas flow rate of methane is 2500 mL / min, the gas flow rate of phosphine is 600 mL / min, the gas flow rate of hydrogen is 8000 mL / min, the deposition power is 8000 W, and the deposition pressure is 420 Pa;

[0130] Prepare the first doped amorphous silicon layer: The reaction gases are silane, phosphine, and hydrogen, where the gas flow rate of silane is 3000 mL / min, the gas flow rate of phosphine is 600 mL / min, the gas flow rate of hydrogen is 9000 mL / min, the deposition pressure is 420 Pa, and the deposition power is 8000 W;

[0131] Prepare the silicon oxide mask. Using silane and nitrous oxide, the deposition pressure is 180 Pa, the deposition power is 9000 W, the silane flow rate is 1800 mL / min, and the nitrous oxide flow rate is 9000 mL / min, to obtain a silicon oxide mask with a thickness of 7 nm;

[0132] Annealing activation: By performing annealing treatment in a furnace, the annealing temperature is 930 °C and the time is 30 min. After annealing, the crystallization rates of the second doped amorphous silicon layer, the doped amorphous silicon carbide layer, and the first doped amorphous silicon layer are increased, and they are transformed into the second doped polysilicon layer, the doped silicon carbide layer, and the first doped polysilicon layer;

[0133] The rest is the same as that of Embodiment 1.

[0134] Example 3

[0135] The embodiment of the present application provides a passivated contact solar cell, which is different from the embodiment 2 in that the passivated contact structure includes:

[0136] A dielectric layer is provided on the backlight side of the N-type silicon wafer, the dielectric layer is a silicon oxide layer, and the thickness is 1nm;

[0137] A second doped polysilicon layer is stacked on the side of the dielectric layer away from the N-type silicon wafer, and the doping concentration of phosphorus in the second doped polysilicon layer is 2×10 20 / cm -3 , thickness is 5nm;

[0138] The doped silicon carbide layer is stacked on the side of the second doped polysilicon layer away from the N-type silicon wafer, and the phosphorus doping concentration of the doped silicon carbide layer is 6×10 20 / cm -3 , thickness is 40nm;

[0139] A first doped polysilicon layer is stacked on the side of the doped silicon carbide layer away from the N-type silicon wafer, and the phosphorus doping concentration in the first doped polysilicon layer is 8×10 20 / cm -3 , thickness is 5nm;

[0140] The rest is the same as that of Example 2.

[0141] Example 4

[0142] This embodiment of the application provides a passivated contact solar cell, which is different from Embodiment 2 in that:

[0143] Passivated contact structures, including:

[0144] A dielectric layer is provided on the backlight side of the N-type silicon wafer, the dielectric layer is a silicon oxide layer, and the thickness is 2.5nm;

[0145] A second doped polysilicon layer is stacked on the side of the dielectric layer away from the N-type silicon wafer, and the doping concentration of phosphorus in the second doped polysilicon layer is 5×10 20 / cm -3 , thickness is 30nm;

[0146] The doped silicon carbide layer is stacked on the side of the second doped polysilicon layer away from the N-type silicon wafer, and the phosphorus doping concentration of the doped silicon carbide layer is 2×10 20 / cm -3 , thickness is 5nm;

[0147] A first doped polysilicon layer is stacked on the side of the doped silicon carbide layer facing away from the N-type silicon wafer. The doping concentration of phosphorus element in the first doped polysilicon layer is 3×10 21 / cm -3 , and the thickness is 25 nm;

[0148] The rest is the same as that of Example 2.

[0149] Comparative Example 1

[0150] The comparative example of the present application provides a passivated contact solar cell. The difference from Example 1 is that the thickness of the first doped polysilicon layer is set to 120 nm, and no doped silicon carbide layer is provided between the dielectric layer and the first doped polysilicon layer. The rest is the same as that of Example 1.

[0151] Comparative Example 2

[0152] The comparative example of the present application provides a passivated contact solar cell. The difference from Example 1 is that the thickness of the doped silicon carbide layer is 2 nm, and the rest is the same as that of Example 1.

[0153] Comparative Example 3

[0154] The comparative example of the present application provides a passivated contact solar cell. The difference from Example 1 is that the thickness of the doped silicon carbide layer is 50 nm, and the rest is the same as that of Example 1.

[0155] Experiment

[0156] The performance of the passivated contact solar cell was tested using a Wavelabs solar simulator. Test conditions: AM1.5, 1000 W / m 2 , and the test ambient temperature was 25°C. Before the test, the standard silicon cell was used to correct the sunlight intensity simulated by the light source. The performance test was the photoelectric conversion efficiency Eff, unit %, open circuit voltage Voc, unit mV, short circuit current Jsc, unit mA / cm 2 , fill factor FF, unit %, series resistance Rs, unit mΩ.

[0157] The experimental test results are shown in Table 1.

[0158] Table 1

[0159]

[0160]

[0161] It can be seen from the data comparison between Example 1 and Comparative Example 1 in Table 1 that the photoelectric conversion efficiency of Example 1 is increased by 0.25% compared with that of Comparative Example 1, the open circuit voltage is increased by 3.4 mV, and the short circuit current is increased by 0.15 mA / cm 2, the fill factor is increased by 0.12%, which proves that introducing a doped silicon carbide layer between the dielectric layer and the doped polysilicon layer can better reduce parasitic absorption and improve the contact performance of the solar cell compared with increasing the thickness of the doped polysilicon layer, promoting the increase of the open-circuit voltage, short-circuit current, fill factor and photoelectric conversion efficiency of the solar cell, and the series resistance decreases.

[0162] Combining the experimental data of Comparative Example 2 and Comparative Example 3, it can be seen that in Comparative Example 2, the thickness of the doped silicon carbide layer is too thin, which is not conducive to blocking the diffusion of phosphorus elements in the first doped polysilicon layer, and the electrode paste is easy to ablate and penetrate the doped silicon carbide layer, which is not conducive to the improvement of the open-circuit voltage and fill factor of the solar cell. In Comparative Example 3, the thickness of the doped silicon carbide layer is too thick, the open-circuit voltage and fill factor of the solar cell decrease, and the photoelectric conversion efficiency of the solar cell decreases.

[0163] From the comparison of the experimental data of Example 1 and Example 2 in Table 1, it can be obtained that compared with Example 1, the open-circuit voltage of Example 2 is increased by 1.3 mV, the fill factor is increased by 0.31%, and the photoelectric conversion efficiency is increased by 0.13%. It is proved that adding a second doped polycrystalline layer between the doped silicon carbide layer and the dielectric layer is beneficial to reducing the defects of the solar cell and improving the photoelectric conversion efficiency of the solar cell.

[0164] The passivation contact structure, solar cell and photovoltaic module disclosed in the embodiments of the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the passivation contact structure, solar cell and photovoltaic module of the present invention and its core idea: At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A passivation contact structure, characterized in that: include: A dielectric layer, wherein the thickness of the dielectric layer is 1 nm to 2.5 nm; A doped silicon carbide layer stacked on the surface of the dielectric layer, wherein the thickness of the doped silicon carbide layer is 3nm to 40nm; A first doped polysilicon layer is stacked on the surface of the doped silicon carbide layer, and the thickness of the first doped polysilicon layer is 5nm-50nm.

2. The passivation contact structure according to claim 1, characterized in that: The thickness of the dielectric layer is 1.5 nm to 2.5 nm; and / or the thickness of the doped silicon carbide layer is 5 nm to 25 nm, and the thickness of the first doped polysilicon layer is 15 nm to 35 nm.

3. The passivation contact structure according to claim 1, characterized in that: The edge of the doped silicon carbide layer covers the edge of the dielectric layer, and the doping elements of the doped silicon carbide layer and the first doped polysilicon layer are one or more of phosphorus, arsenic and antimony.

4. The passivation contact structure according to claim 1, characterized in that: A second doped polysilicon layer is further disposed between the dielectric layer and the doped silicon carbide layer, and the thickness of the second doped polysilicon layer is 5 nm to 150 nm.

5. The passivation contact structure according to any one of claims 1 to 4, characterized in that: The dielectric layer is a silicon oxide layer.

6. A solar cell, characterized in that: It comprises the passivation contact structure as claimed in any one of claims 1 to 5.

7. The solar cell according to claim 6, characterized in that: The solar cell is a passivated contact solar cell, and the passivated contact solar cell comprises: Silicon wafer; A passivation contact structure, in which a dielectric layer is stacked on the backlight surface of the silicon wafer; The first electrode, the first doped polysilicon layer and the doped silicon carbide layer in the passivation contact structure simultaneously form an ohmic contact with the first electrode.

8. The solar cell according to claim 7, characterized in that: When the silicon wafer is N-type, the conductivity type of the first doped polysilicon layer and the doped silicon carbide layer is N-type; when the silicon wafer is P-type, the conductivity type of the first doped polysilicon layer and the doped silicon carbide layer is P-type.

9. The solar cell according to claim 7, characterized in that: The resistivity of the silicon wafer is 0.3Ω·cm to 7Ω·cm; and / or a first functional layer is stacked on the side of the first doped polysilicon layer facing away from the silicon wafer, and the first electrode penetrates the first functional layer and is in ohmic contact with the first doped polysilicon layer and the doped silicon carbide layer.

10. The solar cell according to claim 9, characterized in that: The first functional layer includes a first anti-reflection layer, the thickness of the first anti-reflection layer is 60nm-130nm, and the material of the first anti-reflection layer is one or a combination of silicon nitride, silicon oxynitride and silicon oxide.

11. The solar cell according to claim 7, characterized in that: The passivated contact solar cell further comprises a doping layer and a second functional layer which are sequentially stacked and arranged on one side of the light-receiving surface of the silicon wafer.

12. The solar cell according to claim 11, characterized in that: The second functional layer includes a passivation layer and a second anti-reflection layer stacked on the doping layer.

13. The solar cell according to claim 12, characterized in that: The material of the passivation layer is aluminum oxide; and / or the material of the second anti-reflection layer is one or more combinations of silicon nitride, silicon oxynitride and silicon oxide; and / or the thickness of the passivation layer is 2nm to 7nm; and / or the thickness of the second anti-reflection layer is 60nm to 130nm.

14. A photovoltaic module, characterized in that: It comprises a solar cell as claimed in any one of claims 6 to 13.

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