Electronic package
By designing multiple convex parts on the heat dissipation structure and increasing their bonding area with the cladding layer, the problem of easy delamination of the heat sink in the prior art is solved, and a more stable packaging effect is achieved.
Patent Information
- Application Number
- CN202421830692.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-30
- Filing Date
- 2024-07-31
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-07-31
AI Technical Summary
In existing semiconductor packages, the bonding area between the heat sink and the packaging colloid is small, which makes the heat sink easily delaminated, especially after the single cutting process.
The designed heat dissipation structure has multiple convex portions facing the load-bearing structure, increasing the bonding area between the heat dissipation structure and the cladding layer, so as to effectively avoid the problem of delamination after the single cutting process.
By increasing the bonding area between the heat dissipation structure and the cladding layer, the problem of delamination of the heat dissipation structure after the single cutting process is effectively avoided, and the stability and reliability of the package are improved.
Smart Images
Figure CN223052137U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor device, especially an electronic package that can meet the thinning requirements. Background Art
[0002] With the booming development of the electronics industry, electronic products are gradually moving towards the trend of multi-function and high-performance. Currently, technologies applied in the field of chip packaging, such as flip-chip type packaging modules like Wafer Scale Package (abbreviated as CSP) or Direct Chip Attached (abbreviated as DCA), have become the mainstream of packaging.
[0003] Figures 1A to 1B FIG. is a schematic cross-sectional view of the manufacturing method of the existing semiconductor package 1.
[0004] As Figure 1A shown, first, a plurality of semiconductor chips 11 are flip-chip bonded on a whole-panel packaging substrate 10, and then each of the semiconductor chips 11 is coated with a packaging colloid 14. After that, a heat sink 15 is formed on the packaging colloid 14 to contact these semiconductor chips 11.
[0005] As Figure 1B shown, a dicing process is performed along the dicing path S as Figure 1A shown to obtain a plurality of semiconductor packages 1, and the heat dissipation effect of the semiconductor chips 11 can be improved through the heat sink 15.
[0006] However, in the existing semiconductor package 1, when the whole-panel heat sink 15 (as Figure 1C shown) is combined with a plurality of semiconductor chips 11, since the actual bonding area between the heat sink 15 and the packaging colloid 14 is small (only local dot bonding), it is easy to cause the problem of delamination (peeling) of the heat sink 15. Especially after the dicing process, delamination will occur at the corners of the heat sink 15.
[0007] Therefore, how to overcome the problems of the above-mentioned existing technologies has actually become an urgent issue to be solved currently. Utility Model Content
[0008] In view of the above-mentioned various deficiencies of the existing technologies, this application provides an electronic package, including: a carrier structure having a circuit layer; an electronic component disposed on the carrier structure and electrically connected to the circuit layer; a heat dissipation structure disposed on the carrier structure to cover the electronic component, wherein the heat dissipation structure has a convex portion facing the carrier structure; and a coating layer disposed on the carrier structure to cover the electronic component.
[0009] The present application also provides a method for manufacturing an electronic package, including: disposing an electronic component on a carrier structure having a circuit layer, wherein the electronic component is electrically connected to the circuit layer; disposing a heat dissipation structure on the carrier structure such that the heat dissipation structure covers the electronic component, wherein the heat dissipation structure has a convex portion facing the carrier structure; forming a coating layer between the carrier structure and the heat dissipation structure to coat the electronic component with the coating layer; and performing a dicing process along a dicing path, wherein the dicing path passes through the plurality of convex portions.
[0010] In the foregoing electronic package and its manufacturing method, the convex portion is located at at least one corner of the coating layer.
[0011] In the foregoing electronic package and its manufacturing method, the heat dissipation structure is made of a metal material. For example, the heat dissipation structure includes a heat sink, and the convex portion is disposed on the heat sink.
[0012] In the foregoing electronic package and its manufacturing method, the heat dissipation structure includes a heat sink covering the electronic component and support legs connecting the heat sink, such that the support legs are disposed on the carrier structure.
[0013] In the foregoing electronic package and its manufacturing method, it further includes a conductive component electrically connected to the carrier structure.
[0014] As can be seen from the above, in the electronic package and its manufacturing method of the present application, mainly by providing a plurality of convex portions on the heat dissipation structure, compared with the prior art, the bonding area between the heat dissipation structure and the coating layer can be increased, thus effectively avoiding the problem of delamination (peeling) of the heat dissipation structure during the dicing process. Especially after the dicing process, the corners of the heat dissipation structure are clamped by the convex portions to strengthen the bonding between the heat dissipation structure and the coating layer. Description of the Drawings
[0015] Figures 1A to 1B It is a cross-sectional schematic view of a method for manufacturing an existing semiconductor package.
[0016] Figure 1C It is a schematic view of an integral surface heat sink of an existing semiconductor package.
[0017] Figures 2A to 2E It is a cross-sectional schematic view of a method for manufacturing the electronic package of the present application, wherein Figure 2C It is a partial top view schematic view.
[0018] Figure 3A and Figure 3B is Figure 2C a cross-sectional schematic view of different embodiments of
[0019] Description of the Main Component Symbols
[0020] 1 Semiconductor package
[0021] 10 Encapsulation Substrate
[0022] 11 Semiconductor Chip
[0023] 14 Encapsulation Colloid
[0024] 15 Heat Sink
[0025] 2 Electronic Encapsulation Component
[0026] 20 Carrier Structure
[0027] 20a First Side
[0028] 20b Second Side
[0029] 200 Circuit Layer
[0030] 21 Electronic Component
[0031] 210 Conductive Bump
[0032] 211 Bonding Wire
[0033] 24 Coating Layer
[0034] 24a First Surface
[0035] 24b Second Surface
[0036] 25 Heat Dissipation Structure
[0037] 25a Heat Sink
[0038] 25b Support Leg
[0039] 250 Protrusion
[0040] 26 Conductive Component
[0041] L, S Cutting Paths Detailed Embodiments
[0042] The following describes the embodiments of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification.
[0043] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions for the implementation of this application. Therefore, they do not have any technical substance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that this application can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in this application. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in this specification are only for the convenience of clear description and are not used to limit the scope of implementation of this application. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope that this application can implement.
[0044] Figures 2A to 2E It is a cross-sectional schematic view of the manufacturing method of the electronic package 2 of this application, where Figure 2C is a partial top view schematic diagram.
[0045] As Figure 2A shown, a full-panel carrier structure 20 is provided, which has opposite first side 20a and second side 20b, and electronic components 21 separated from each other are provided on the first side 20a of the carrier structure 20. Then, a plurality of conductive components 26 such as solder balls are formed on the second side 20b of the carrier structure 20 for subsequent connection of electronic devices (not shown in the figure) such as packaging structures or other structures (such as chips).
[0046] The described carrier structure 20 is a circuit structure with a core layer or a coreless circuit structure, and a circuit layer 200 is formed in the insulating layer, such as a fan-out type redistribution layer (RDL).
[0047] In this embodiment, the material for forming the circuit layer 200 is copper, and the material for forming the insulating layer is a dielectric material such as Polybenzoxazole (PBO), Polyimide (PI), Prepreg (PP), etc. It should be understood that the carrier structure 20 can also be other carriers for carrying chips, such as organic boards, wafers, or other carrier plates with metal routing, and is not limited to the above.
[0048] The described electronic components 21 are active components, passive components, or a combination of the two. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.
[0049] In this embodiment, the electronic component 21 is a semiconductor chip, which is disposed on the carrier structure 20 in a flip-chip manner through a plurality of conductive bumps 210 such as solder materials and electrically connected to the circuit layer 200 on the first side 20a; alternatively, the electronic component 21 can be electrically connected to the circuit layer 200 on the first side 20a by a plurality of bonding wires 211 in a wire bonding manner. However, the manner in which the electronic component is electrically connected to the carrier structure is not limited to the above.
[0050] Moreover, a Under Bump Metallurgy (UBM) (not shown) can be formed on the outermost circuit layer 200 of the second side 20b of the carrier structure 20 as required to facilitate the bonding of the conductive element 26.
[0051] As Figure 2B shown, a heat dissipation structure 25 is provided and disposed on the first side 20a of the carrier structure 20 such that the heat dissipation structure 25 covers the electronic component 21.
[0052] In this embodiment, the heat dissipation structure 25 includes a heat sink 25a and support legs 25b connecting the heat sink 25a, so that the support legs 25b are disposed on the first side 20a of the carrier structure 20 and the heat sink 25a covers the electronic component 21. For example, the material forming the heat dissipation structure 25 is a metal such as gold, silver, copper (Cu), nickel (Ni), iron (Fe), aluminum (Al), stainless steel (Sus), etc.
[0053] Furthermore, the heat sink 25a has a plurality of convex portions 250 facing the carrier structure 20. For example, the shape of the convex portion 250 is a cross, as Figure 2C shown, which corresponds to the cutting path L as Figure 2D shown.
[0054] As shown in 2D, a coating layer 24 is formed on the first side 20a of the carrier structure 20 such that the coating layer 24 fills between the heat sink 25a and the first side 20a of the carrier structure 20 and the coating layer 24 covers the electronic component 21.
[0055] The coating layer 24 has opposite first and second surfaces 24a and 24b, and the first surface 24a of the coating layer 24 is bonded to the first side 20a of the carrier structure 20.
[0056] In this embodiment, the coating layer 24 is an insulating material such as polyimide (PI), dry film, epoxy resin, or molding compound, and it can be formed on the first side 20a of the carrier structure 20 by lamination or molding.
[0057] As shown Figure 2E in, a singulation process is performed along a cutting path L as shown Figure 2D to remove the support leg 25b, thereby obtaining the electronic package 2 of the present application.
[0058] In this embodiment, a plurality of the protrusions 250 are disposed on the cutting path L. However, in other embodiments, as shown Figure 3A and Figure 3B in, some of the cutting path L may not be provided with the protrusions 250.
[0059] Therefore, the manufacturing method of the electronic package 2 of the present application provides a heat dissipation structure 25 having a plurality of protrusions 250 on one side, and through the design corresponding to the protrusions 250 on the cutting path L, when the heat dissipation structure 25 of the entire layout (as shown Figure 2D in) is combined with a plurality of electronic components 21, the bonding area between the heat dissipation structure 25 and the coating layer 24 can be increased, thereby effectively avoiding the problem of delamination (peeling) of the heat dissipation structure 25. Therefore, compared with the prior art, after the singulation process of the manufacturing method of the present application, the corners of the heat dissipation structure 25 are clamped by the protrusions 250, and the delamination problem will not occur.
[0060] The present application also provides an electronic package 2, which includes: a carrier structure 20 having a circuit layer 200, at least one electronic component 21, a coating layer 24, and a heat dissipation structure 25.
[0061] The electronic component 21 is disposed on the carrier structure 20 and electrically connected to the circuit layer 200.
[0062] The heat dissipation structure 25 is disposed on the carrier structure 20 such that the heat dissipation structure 25 covers the electronic component 21. Among them, the heat dissipation structure 25 has protrusions 250 facing the carrier structure 20.
[0063] The coating layer 24 is disposed on the carrier structure 20 to cover the electronic component 21.
[0064] In one embodiment, the protrusion 250 is located at at least one corner of the coating layer 24.
[0065] In one embodiment, the heat dissipation structure 25 is made of a metal material.
[0066] In one embodiment, the heat dissipation structure 25 includes a heat sink 25a, and the protrusion 250 is disposed on the heat sink 25a.
[0067] In one embodiment, the electronic package 2 further includes a conductive element 26 electrically connected to the circuit layer 200.
[0068] In summary, for the electronic package and its manufacturing method of the present application, through the design of providing a convex portion on the side of the heat dissipation structure for placing the coating layer, the bonding area between the heat dissipation structure and the coating layer can be increased, thus effectively avoiding the problem of delamination (peeling) of the heat dissipation structure.
[0069] The above embodiments are used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of the rights protected by the present application shall be as listed in the claims.
Claims
1. An electronic package, characterized in that: include: A bearing structure having a circuit layer; An electronic component, which is disposed on the supporting structure and electrically connected to the circuit layer; A heat dissipation structure is disposed on the supporting structure so that the heat dissipation structure covers the electronic component, wherein the heat dissipation structure has a convex portion facing the supporting structure; as well as The covering layer is arranged on the supporting structure to cover the electronic element.
2. The electronic package according to claim 1, wherein: The convex portion is located at at least one corner of the cladding layer.
3. The electronic package according to claim 1, wherein: The heat dissipation structure is made of metal.
4. The electronic package according to claim 1, wherein: The heat dissipation structure comprises a heat dissipation sheet, and the convex part is arranged on the heat dissipation sheet.
5. The electronic package according to claim 1, wherein: The electronic package also includes a conductive element electrically connected to the supporting structure.