Electronic package

Abstract

An electronic package provides a plurality of conductive posts having separable blocks and a first electronic component having a separable block, and a cladding layer wraps the first electronic component, the separable blocks and the conductive posts to expose the separable blocks out of a surface of the cladding layer, and then the separable blocks are removed to form a plurality of conductive posts having a plurality of separable blocks and a plurality of conductive posts having a plurality of separable blocks and a plurality of conductive posts having a plurality of separable blocks and a plurality of conductive posts having a plurality of separable blocks. And a plurality of conductive columns are arranged on the surface of the cladding layer so as to form a plurality of concave parts on the surface of the cladding layer, and the plurality of conductive columns and the first electronic element are exposed out of the concave parts, so that through the design of the concave parts, the contact area between a circuit part subsequently formed on the cladding layer and the cladding layer is increased, and the condition of delamination of the circuit part is avoided during thermal circulation.

Description

Technical Field

[0001] This application relates to a semiconductor packaging technology, particularly an electronic package capable of improving reliability and its manufacturing method. Background Art

[0002] With the evolution of semiconductor packaging technology, different packaging forms have been developed for semiconductor devices. To improve electrical performance and save packaging space, different three-dimensional packaging technologies have been developed to integrate integrated circuits with different functions into a single packaging structure. For example, electronic components with different functions (such as memories, central processing units, graphics processing units, video application processors, etc.) are stacked to achieve system integration for use in thin and light electronic products.

[0003] Figures 1A to 1D FIG. is a schematic cross-sectional view of the manufacturing method of an existing semiconductor package 1.

[0004] As Figure 1A shown, a plurality of conductive posts 13 are formed on a carrier plate 6, and a plurality of semiconductor chips 11 are disposed on the carrier plate 6. Among them, a plurality of conductors 112 are bonded and electrically connected to the semiconductor chip 11, and a protective film 111 covers the conductors 112. An isolation layer 60, a metal layer 62, and a passivation layer 61 are sequentially formed on the carrier plate 6 for the plurality of conductive posts 13 to be disposed on the passivation layer 61 by electroplating (a seed layer is not shown in the figure).

[0005] As Figure 1B shown, an encapsulant 15 is formed on the passivation layer 61 of the carrier plate 6 to cover the semiconductor chips 11, the protective film 111, and the conductive posts 13. Then, a part of the material of the protective film 111, a part of the material of the plurality of conductive posts 13, a part of the material of the plurality of conductors 112, and a part of the material of the encapsulant 15 are removed by grinding to make the upper surface of the encapsulant 15 flush with the protective film 111, the plurality of conductive posts 13, and the plurality of conductors 112, so that the plurality of conductive posts 13, the protective film 111, and the plurality of conductors 112 are exposed from the encapsulant 15.

[0006] As Figure 1C shown, a circuit structure 10 is formed on the encapsulant 15, and the circuit structure 10 is electrically connected to the plurality of conductive posts 13 and the plurality of conductors 112. Among them, the circuit structure 10 includes a plurality of insulating layers 100 and a plurality of circuit layers 101 disposed on the plurality of insulating layers 100.

[0007] As Figure 1DAs shown, an electronic component 18 is electrically connected to the circuit layer 101 through a plurality of conductive bumps 180, so as to be combined with the circuit structure 10, and an underfill 19 is formed between the circuit structure 10 and the electronic component 18 to cover the conductive bumps 180.

[0008] Then, the carrier plate 6 and the release layer 60 and the metal layer 62 thereon are removed, and the passivation layer 61 is retained, and a wiring layer 140 is formed on the passivation layer 61 to electrically connect the conductive posts 13. Thereafter, a plurality of conductive components 17 such as solder bumps or solder balls can be formed on the wiring layer 140 to externally connect other electronic devices, and along the cutting path S as shown in Figure 1C is carried out a singulation process to obtain the semiconductor package 1.

[0009] However, in the existing method for manufacturing the semiconductor package 1, due to the mismatch of the coefficient of thermal expansion (CTE) between the encapsulation colloid 15 and the semiconductor chip 11, the situation of uneven thermal stress is likely to occur, resulting in warping of the encapsulation colloid 15 during the thermal cycle of the process, leading to delamination of the circuit structure 10.

[0010] Therefore, how to overcome the above problems of the prior art has actually become a difficult problem that the industry urgently needs to overcome at present. Summary of the Invention

[0011] In view of the above-mentioned various deficiencies of the prior art, the present application provides an electronic package, including: a coating layer having opposite first and second surfaces, wherein a plurality of recesses are formed on the first surface; a first electronic component embedded in the coating layer and exposed from a part of the plurality of recesses; and a plurality of conductive posts embedded in the coating layer and exposed from another part of the plurality of recesses.

[0012] In the foregoing electronic package, a separable block is formed in the recess. For example, the separable block includes a polyimide material or a poly-p-diazobenzene material.

[0013] The present application also provides a method for manufacturing an electronic package, including: disposing a plurality of conductive posts and at least one first electronic component on a carrier plate, wherein, a plurality of separable blocks are formed on end faces of the plurality of conductive posts and on the first electronic component; forming a coating layer on the carrier plate, and making the coating layer cover the first electronic component, the plurality of separable blocks and the plurality of conductive posts, wherein, the coating layer has opposite first and second surfaces, so that the plurality of separable blocks are exposed on the first surface of the coating layer, and the coating layer is bonded to the carrier plate with its second surface; and removing the plurality of separable blocks to form a plurality of recesses on the first surface of the coating layer, so that the plurality of conductive posts and the first electronic component are exposed from the plurality of recesses.

[0014] In the foregoing method, the separable block includes a polyimide material or a poly(p - phenylenedioxazole) material.

[0015] In the foregoing electronic package and its manufacturing method, it further includes forming a circuit portion on the first surface of the coating layer and in the plurality of recesses, so that the circuit portion is electrically connected to the plurality of conductive posts and the first electronic component. For example, the circuit portion includes a dielectric layer formed on the first surface and a circuit body embedded in the dielectric layer and extending into the plurality of recesses. Further, the circuit body is electrically connected to the conductive posts and the first electronic component. Alternatively, it may include forming a circuit structure on the circuit portion to electrically connect the circuit portion. Further, it also includes disposing a second electronic component on the circuit structure.

[0016] In the foregoing electronic package and its manufacturing method, a passivation layer is provided on the carrier plate to bond the second surface of the coating layer, the plurality of conductive posts and the first electronic component. For example, it may include removing the carrier plate. Further, it includes forming a wiring layer on the passivation layer, and the wiring layer is electrically connected to the plurality of conductive posts

[0017] As can be seen from the above, in the electronic package and its manufacturing method of the present application, mainly through the design that the first surface of the coating layer is formed with recesses, when the circuit portion of the subsequent process is formed on the first surface of the coating layer, the circuit portion will be stuck in the recesses, so that the contact area between the coating layer and the circuit portion can be increased. Therefore, compared with the prior art, in the method of the present application during thermal cycling, the delamination of the circuit portion can be avoided, thus improving the reliability of the electronic package. Description of the Drawings

[0018] Figures 1A to 1D It is a schematic cross - sectional view of a method for manufacturing an existing semiconductor package.

[0019] Figures 2A to 2F It is a schematic cross - sectional view of a method for manufacturing an electronic package of the present application.

[0020] Description of the Main Component Symbols

[0021] 1 Semiconductor package

[0022] 10, 20 Circuit structure

[0023] 100, 200 Insulating layer

[0024] 101, 201 Circuit layer

[0025] 11 Semiconductor chip

[0026] 111, 211 Protective film

[0027] 112, 212 Conductor

[0028] 13, 23 Conductive pillar

[0029] 140, 240 Wiring layer

[0030] 15 Encapsulation colloid

[0031] 17, 27 Conductive element

[0032] 18 Electronic component

[0033] 180, 280 Conductive bump

[0034] 19, 29 Underfill

[0035] 2 Electronic package

[0036] 202 Electrical contact pad

[0037] 21 First electronic component

[0038] 21a Active surface

[0039] 21b Non - active surface

[0040] 210 Electrode pad

[0041] 22 Bonding layer

[0042] 23a, 23b End face

[0043] 24 Wiring structure

[0044] 25 Coating layer

[0045] 25a First surface

[0046] 25b Second surface

[0047] 250 Recess

[0048] 26 Circuit part

[0049] 260 Dielectric layer

[0050] 261 Circuit body

[0051] 261a Conductive trace

[0052] 261b Conductive blind via

[0053] 270 Metal layer under bump

[0054] 28 Second electronic component

[0055] 6,9 Carrier plate

[0056] 60,90 Release layer

[0057] 61,91 Passivation layer

[0058] 62,92 Metal layer

[0059] 80 Separable block

[0060] 93 Conductive seed layer

[0061] S Cutting path. Detailed implementation manners

[0062] The following illustrates the implementation manners of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification.

[0063] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limited conditions under which the present application can be implemented. Therefore, they do not have any technical substance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present application can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present application. At the same time, the terms such as "upper", "first", "second", and "one" used in this specification are only for the convenience of clear narration and are not used to limit the scope under which the present application can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope under which the present application can be implemented.

[0064] Figures 2A to 2F It is a cross-sectional schematic view of the manufacturing method of the electronic package 2 of the present application.

[0065] As Figure 2A shown, a plurality of conductive posts 23 are formed on a carrier plate 9, and at least one first electronic component 21 is disposed on the carrier plate 9. Among them, a plurality of separable blocks 80 are formed on the end faces 23a of the plurality of conductive posts 23 and on the first electronic component 21.

[0066] The described carrier plate 9 is, for example, a plate made of a semiconductor material (such as silicon or glass). An isolation layer 90, a metal layer 92 such as titanium / copper, and a passivation layer 91 such as a dielectric material or a solder mask material are sequentially formed thereon by, for example, coating. And a conductive seed layer 93 such as titanium / copper is formed on the passivation layer 91 for the conductive posts 23 to be disposed on the passivation layer 91 by a patterning process.

[0067] The described separable block 80 can be composed of a water-soluble material, which can include materials such as polyimide (abbreviated as PI) or polybenzoxazole (abbreviated as PBO).

[0068] The described conductive posts 23 are made of a metal material such as copper or a solder material, but are not limited thereto.

[0069] The described first electronic component 21 is an active component, a passive component, or a combination of both. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0070] In this embodiment, the first electronic component 21 is a semiconductor chip, which has opposite working surfaces 21a and non-working surfaces 21b. And the first electronic component 21 is adhered to the passivation layer 91 with its non-working surface 21b through a bonding layer 22. The working surface 21a has a plurality of electrode pads 210 and a protective film 211 such as a passivation material, and a conductor 212 is bonded and electrically connected to the electrode pads 210 and disposed in the protective film 211. For example, the conductor 212 is a circular spherical shape such as a conductive line or a solder ball, or a columnar shape of a metal material such as a copper column or a solder bump, or a stud conductive member made by a wire bonding machine.

[0071] Furthermore, the separable block 80 is bonded to the top of the conductor 212 on the first electronic component 21.

[0072] As Figure 2B As shown, a coating layer 25 is formed on the passivation layer 91 of the carrier plate 9 to make the coating layer 25 cover the first electronic components 21, the protective film 211, and the conductive posts 23. Among them, the coating layer 25 has opposite first surfaces 25a and second surfaces 25b, so that the coating layer 25 is bonded to the passivation layer 91 of the carrier plate 9 with its second surface 25b, and the protective film 211 and the plurality of separable blocks 80 are exposed on the first surface 25a of the coating layer 25.

[0073] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI for short), dry film, encapsulation colloid or encapsulation material (molding compound) such as epoxy resin. For example, the process of the coating layer 25 can be formed on the passivation layer 91 by means of liquid encapsulation (liquid compound), spraying (injection), lamination or compression molding.

[0074] Furthermore, through a planarization process, the first surface 25a of the coating layer 25 can be made flush with the protective film 211 and the separable block 80, so that the separable block 80 is exposed on the first surface 25a of the coating layer 25. For example, in the planarization process, part of the material of the protective film 211, part of the material of the separable block 80 and part of the material of the coating layer 25 are removed by grinding.

[0075] As Figure 2C shown, the separable blocks 80 are removed by means such as etching, etc., to form a plurality of recesses 250 on the first surface 25a of the coating layer 25, so that the end faces 23a of the conductive posts 23 and the conductors 212 are respectively exposed in the recesses 250.

[0076] As Figure 2D shown, a circuit portion 26 is formed on the first surface 25a of the coating layer 25 and in the recesses 250, so that the circuit portion 26 is electrically connected to the conductive posts 23 and the conductors 212 on the first electronic component 21.

[0077] In this embodiment, the circuit portion 26 includes a dielectric layer 260 formed on the first surface 25a and a circuit body 261 disposed on the dielectric layer 260 (for example, embedded in the dielectric layer 260) and extending into the recesses 250. For example, the circuit body 261 has a plurality of conductive traces 261a that are combined with the first surface 25a and a plurality of conductive blind vias 261b that are electrically connected to the conductive traces 261a and are located in the recesses 250, so that the upper surface of the conductive traces 261a is flush with the upper surface of the dielectric layer 260, and the conductive traces 261a are exposed on the upper surface of the dielectric layer 260.

[0078] As Figure 2E shown, a circuit structure 20 is formed on the circuit portion 26, and the circuit structure 20 is electrically connected to the circuit body 261.

[0079] In this embodiment, the circuit structure 20 includes a plurality of insulating layers 200 and a plurality of circuit layers 201 disposed on the insulating layers 200, such as the redistribution layer (RDL) specifications, and the outermost insulating layer 200 can serve as a solder mask layer to expose the outermost circuit layer 201 to the solder mask layer for use as an electrical contact pad 202. Alternatively, the circuit structure 20 may also include only a single insulating layer 200 and a single circuit layer 201.

[0080] Furthermore, the material for forming the circuit layer 201 is copper, and the material for forming the insulating layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc., or a solder mask material such as green paint, ink, etc.

[0081] Such as Figure 2F As shown, at least one second electronic component 28 is disposed on the circuit structure 20, and the carrier plate 9 and the release layer 90 and the metal layer 92 thereon are removed to form a wiring structure 24 on the second surface 25a of the coating layer 25 for bonding the conductive element 27, and a singulation process is performed along the cutting path S as shown in Figure 2E to obtain the electronic package 2 of the present application.

[0082] The second electronic component 28 described above is, for example, an active component, a passive component, a package structure, or a combination thereof. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0083] In this embodiment, the second electronic component 28 is a semiconductor chip, which can be disposed on the electrical contact pad 202 of the circuit structure 20 in a flip-chip manner through a plurality of conductive bumps 280 such as solder bumps, copper bumps, or others and electrically connected to the circuit layer 201, and the conductive bumps 280 are coated with an underfill 29; alternatively, the second electronic component 28 can be electrically connected to the circuit layer 201 in a wire bonding manner through a plurality of wires; or, the second electronic component 28 can directly contact the circuit layer 201. It should be understood that there are many ways for the second electronic component 28 to be electrically connected to the circuit structure 20, and it is not limited to the above.

[0084] Also, an under bump metallurgy (UBM) 270 can be formed on the electrical contact pad 202 to facilitate the bonding of the conductive bump 280.

[0085] In addition, after removing the carrier plate 9 and the release layer 90 and the metal layer 92 thereon, the passivation layer 91 is retained, and then a wiring layer 240 is formed on the passivation layer 91, so that the wiring layer 240 and the passivation layer 91 serve as a wiring structure 24, and the wiring layer 240 is electrically connected to the conductive posts 23.

[0086] In this embodiment, the passivation layer 91 is formed with a plurality of openings by a laser method, so that the end faces 23b of the conductive posts 23 and part of the second surface 25b of the coating layer 25 are exposed from the openings for bonding the wiring layer 240. For example, the wiring layer 240 is an under bump metal (UBM) to bond a plurality of conductive elements 27 such as solder bumps or solder balls for external connection to an electronic device (not shown) such as a circuit board; or, a wiring layer (not shown) can be formed on the passivation layer 91 through an RDL process to bond the conductive element 27 or UBM. It should be understood that there are various types of embodiments of the wiring layer 240 and there is no particular limitation.

[0087] Therefore, the manufacturing method of the present application mainly forms a recess 250 on the first surface 25a of the coating layer 25 through the design of the separable block 80, so as to increase the contact area between the coating layer 25 and the circuit portion 26. For example, the circuit body 261 is embedded in the recess 250. Therefore, compared with the prior art, in the manufacturing method of the present application during a thermal cycle, even if the coating layer 25 warps, the circuit portion 26 will not peel off, thus effectively improving the reliability of the electronic package 2.

[0088] The present application also provides an electronic package 2, which includes: a coating layer 25, at least one first electronic component 21, and a plurality of conductive posts 23.

[0089] The coating layer 25 has opposite first and second surfaces 25a and 25b, wherein a plurality of recesses 250 are formed on the first surface 25a.

[0090] The first electronic component 21 is embedded in the coating layer 25 and exposed from part of the plurality of recesses 250.

[0091] The plurality of conductive posts 23 are embedded in the coating layer 25 and exposed from part of the plurality of recesses 250.

[0092] In one embodiment, a separable block 80 is formed in the recess 250. For example, the separable block 80 includes a polyimide material or a polybenzoxazole material.

[0093] In one embodiment, the electronic package 2 further includes a circuit portion 26 formed on the first surface 25a and corresponding to the circuit portions in the plurality of recesses 250, which electrically connects the plurality of conductive posts 23 and the first electronic component 21. For example, the circuit portion 26 includes a dielectric layer 260 formed on the first surface 25a and a circuit body 261 embedded in the dielectric layer 260 and extending into the plurality of recesses 250. Further, the circuit body 261 electrically connects the conductive post 23 and the first electronic component 21. Alternatively, the electronic package 2 further includes a circuit structure 20 formed on the circuit portion 26 to electrically connect the circuit portion 26, and may further include a second electronic component 28 disposed on the circuit structure 20.

[0094] In one embodiment, a passivation layer 91 is bonded to the second surface 25b of the coating layer 25. For example, the electronic package 2 further includes a wiring layer 240 formed on the passivation layer 91, and the wiring layer 240 electrically connects the plurality of conductive posts 23.

[0095] In summary, for the electronic package and its manufacturing method of the present application, through the design of the separable block, recesses are formed on the first surface of the coating layer for the circuit portion to be disposed on the first surface of the coating layer and extend into the recesses, increasing the contact area between the coating layer and the circuit portion. Therefore, compared with the prior art, in the manufacturing method of the present application during thermal cycling, even if the coating layer warps, the circuit portion will not delaminate, thus effectively improving the reliability of the electronic package.

[0096] The above embodiments are only used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of the claims of the present application shall be as listed in the claims.

Claims

1. An electronic package, characterized in that: include: A cladding layer having a first surface and a second surface opposite to each other, wherein a plurality of recesses are formed on the first surface; A first electronic component embedded in the coating layer and exposed in a portion of the plurality of recesses; and A plurality of conductive pillars are embedded in the cladding layer and exposed in a portion of the plurality of recesses.

2. The electronic package according to claim 1, wherein: A separable block is formed in the recess.

3. The electronic package as claimed in claim 2, characterized in that The separable block includes a polyimide material or a poly(p-oxadiazole)benzene material.

4. The electronic package according to claim 1, wherein: The electronic package also includes a circuit portion formed on the first surface and in the plurality of recesses, which electrically connects the plurality of conductive pillars and the first electronic element.

5. The electronic package as claimed in claim 4, characterized in that The circuit portion includes a dielectric layer formed on the first surface and a circuit body embedded in the dielectric layer and extending into the plurality of recesses.

6. The electronic package according to claim 5, characterized in that The circuit body is electrically connected to the plurality of conductive pillars and the first electronic element.

7. The electronic package according to claim 4, characterized in that: The electronic package also includes a circuit structure formed on the circuit portion, so that the circuit structure is electrically connected to the circuit portion.

8. The electronic package according to claim 7, wherein: The electronic package also includes a second electronic component arranged on the circuit structure.

9. The electronic package according to claim 1, wherein: A passivation layer is combined on the second surface of the cladding layer.

10. The electronic package according to claim 9, wherein: The electronic package also includes a wiring layer formed on the passivation layer, and the wiring layer is electrically connected to the plurality of conductive pillars.

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