Starting circuit

Abstract

A start-up circuit includes a first circuit branch coupled between an input node and an output node and a second circuit branch coupled between the input node and the output node. The first circuit generates a first current, and the second circuit branch absorbs current from the first node based on the first current. The third circuit branch is coupled between the input node and the output node and supplies current to the second node based on the voltage at the first node, thereby generating a feedback voltage at the second node. The first circuit branch increases the first current based on the feedback voltage, thereby increasing the current drawn from the first node by the second circuit branch, and increases the current supplied to the second node by the third circuit branch, thereby generating a start-up current at the output node.

Description

Technical Field

[0001] The present disclosure relates to the startup of integrated circuits, and more particularly to a circuit for performing the startup of an integrated circuit in a manner that is not affected by temperature, supply voltage, or variations between devices. Background Art

[0002] When an integrated circuit (IC) device is powered by a battery, it enters a startup phase. This period is characterized by providing the required bias points, voltages, and currents to various internal nodes. The goal of this startup phase is to prevent potential problems that may occur during the rise of the supply voltage, which may cause the circuit to enter an undesired operating state.

[0003] During the startup phase, leakage currents play an important role in charging the internal nodes of the IC. However, these currents can vary depending on process parameters, corner cases, and operating temperature. This variability can interfere with consistent and accurate bias establishment, leading to potential device reliability issues during startup. In addition, the leakage current models used in existing simulations may not be accurate. Measurement noise during device characterization may distort the model, affecting the simulation results and leading to an incorrect estimate of the leakage current. Therefore, a startup circuit topology that is not only leakage-dependent but also robust to these variations is necessary.

[0004] As Figure 1 shown, a first known startup circuit includes a resistor connected between an input voltage VIN (e.g., battery voltage) and a node Ng. The startup circuit also includes a Zener diode Dz, whose cathode is connected to the node Ng and whose anode is connected to ground. A power transistor T supplies power from the input voltage to a load circuit within the IC, and its gate is controlled by the voltage VZ at the node Ng. During startup, a startup current I_startup flows through the resistor R to form a voltage VZ at the node Ng.

[0005] The problem with this first known startup circuit is that it provides correct startup over the entire possible range of the supply voltage VIN. For some high-voltage applications, this range can be wide. Therefore, the resistor R needs to be small enough to provide sufficient startup current I_startup to establish the correct voltage VZ at an appropriate slope. At the same time, it should be large enough to limit the power dissipation when the supply voltage VIN is high. If the supply voltage VIN is large, the resistor R is physically large, consuming an undesired large area.

[0006] As Figure 2As shown, the second known startup circuit includes a diode, the cathode of which is connected to the input voltage VIN and the anode of which is connected to node Ng. The cathode of the Zener diode Dz is connected to node Ng and the anode is connected to ground. The gate of the power transistor T is controlled by the voltage VZ present at node Ng. During startup, the startup current I_startup flows through the diode D to form the voltage VZ at node Ng.

[0007] The problem with the second known startup circuit is that the leakage current flowing through the diode D is highly sensitive to process, voltage, and temperature variations. Therefore, it is challenging to determine the appropriate size of the diode D to allow for sufficient startup current I_startup at the process corners, especially considering the limitations of existing MOS diode models.

[0008] Therefore, further development is needed to provide a reliable startup function across process variations, regardless of the magnitude of the startup current. Thus, the goal of such development is to overcome the limitations imposed by process, corner, and temperature dependencies, as well as inaccuracies in leakage current simulation, without consuming excessive device area. Summary of the Utility Model

[0009] Disclosed herein is a startup circuit that includes a startup current circuit. The startup current circuit includes a first circuit branch coupled between an input node and an output node, the first circuit branch being configured to generate a first current, a second circuit branch coupled between the input node and the output node, the second circuit branch being configured to draw current from a first node based on the first current, and a third circuit branch coupled between the input node and the output node, the third circuit branch being configured to supply current to a second node based on the voltage at the first node, thereby generating a feedback voltage at the second node. The first circuit branch is configured to increase the first current based on the feedback voltage, thereby increasing the current drawn by the second circuit branch from the first node and increasing the current supplied by the third circuit branch to the second node, thereby generating a startup current at the output node.

[0010] The first circuit branch may include a diode-coupled transistor connected between the input node and a third node, a first mirror transistor connected between the third node and the output node and having a control terminal connected to the third node, and a feedback transistor connected between the input node and the third node and having a control terminal coupled to receive the feedback voltage.

[0011] The diode-coupled transistor and the first mirror transistor can be n-channel transistors, where the drain of the diode-coupled transistor is connected to the input node, its source is connected to the third node, and its gate is connected to the third node, and the drain of the first mirror transistor is connected to the third node, its source is connected to ground, and its gate is connected to the third node. The feedback transistor can be an n-channel transistor, whose drain is connected to the input node, its source is connected to the third node, and its gate is connected to the second node.

[0012] The diode-coupled transistor and the first mirror transistor can be n-channel transistors, where the drain of the diode-coupled transistor is connected to the input node, its source is connected to the third node, and its gate is connected to the third node, and the drain of the first mirror transistor is connected to the third node, its source is connected to ground, and its gate is connected to the third node. The feedback transistor can be a p-channel transistor, whose source is connected to the input node, its drain is connected to the third node, and its gate is connected to the second node.

[0013] The second circuit branch can include a second mirror transistor connected between the input node and the first node and having a control terminal connected to the first node, a sink transistor connected between the first node and the output node and having a control terminal connected to the first node, and a third mirror transistor connected between the first node and the output node through a resistor and having a control terminal connected to the third node. The second mirror transistor and the sink transistor can be p-channel transistors, where the source of the second mirror transistor is connected to the input node, its drain is connected to the first node, and its gate is connected to the first node, and the source of the sink transistor is connected to the first node, its drain is connected to ground, and its gate is connected to the first node. The third mirror transistor can be an n-channel transistor, whose drain is connected to the first node, its source is coupled to ground through a resistor, and its gate is connected to the third node.

[0014] The third circuit branch can include a fourth mirror transistor connected between the input node and the second node and having a control terminal connected to the first node, the fourth mirror transistor being in a current mirror relationship with the second mirror transistor, and a fifth mirror transistor connected between the second node and ground and having a control terminal connected to the third node, the fifth mirror transistor being in a current mirror relationship with the first mirror transistor.

[0015] The fourth mirror transistor can be a p-channel transistor, whose source is connected to the input node, its drain is connected to the second node, and its gate is connected to the first node, and the fifth mirror transistor can be an n-channel transistor, whose drain is connected to the second node, its source is connected to ground, and its gate is connected to the first node.

[0016] The power transistor can be connected between the input node and ground through a load, and the power transistor has a control terminal connected to the output node. The Zener diode can have a cathode connected to the output node and an anode connected to ground.

[0017] The mirror transistor can be connected between the input node and the control node, and the mirror transistor has a control terminal connected to the first node. The Zener diode can have a cathode connected to the control node and an anode connected to the output node, and the output node is connected to ground. The power transistor can be connected between the input node and ground through a load, and the power transistor has a control terminal connected to the control node.

[0018] This document also discloses a startup circuit including a startup current circuit. The startup current circuit includes: a diode-coupled transistor connected between the input node and the third node, a feedback transistor connected between the input node and the first node and having a control terminal coupled to receive a feedback voltage at the second node, a first current mirror having an input connected to the third node and an output connected to the second node, a second current mirror having an input connected to the first node and an output connected to the second node, a first absorption transistor connected between the first node and the output node through a resistor and having a control terminal connected to the control node of the first current mirror, and a second absorption transistor connected between the first node and the output node and having a control terminal connected to the first node.

[0019] The first current mirror can include a first n-channel transistor whose drain is connected to the third node, whose source is connected to the output node, and whose gate is connected to the third node; and a second n-channel transistor whose drain is connected to the second node, whose source is connected to the output node, and whose gate is connected to the third node.

[0020] The feedback transistor can be an n-channel transistor whose drain is connected to the input node, whose source is connected to the third node, and whose gate is connected to the second node.

[0021] The feedback transistor can be a p-channel transistor whose source is connected to the input node, whose drain is connected to the third node, and whose gate is connected to the second node.

[0022] The second current mirror can include a first p-channel transistor whose source is connected to the input node, whose drain is connected to the first node, and whose gate is connected to the first node; and a second p-channel transistor whose source is connected to the input node, whose drain is connected to the second node, and whose gate is connected to the first node.

[0023] The first absorption transistor can be an n-channel transistor whose drain is connected to the first node, whose source is connected to the output node through a resistor, and whose gate is connected to the control node of the first current mirror.

[0024] The second absorption transistor may be a p-channel transistor, whose source and gate are connected to the first node, and whose drain is connected to the output node. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a first prior art startup circuit.

[0026] Figure 2 is a schematic diagram of a first prior art startup circuit.

[0027] Figure 3 is a schematic diagram of the startup current circuit disclosed herein.

[0028] Figure 3A is a graph showing Figure 3 the voltage of the startup current circuit during operation.

[0029] Figure 4 is a schematic diagram of a first startup circuit incorporating the Figure 3 startup current circuit disclosed herein.

[0030] Figure 5 is a schematic diagram of a second startup circuit incorporating the Figure 3 startup current circuit disclosed herein.

[0031] Figure 6 is a schematic diagram of an alternative startup current circuit. DETAILED DESCRIPTION

[0032] The following disclosure enables those skilled in the art to make and use the subject matter described herein. Without departing from the spirit and scope of the present disclosure, the general principles outlined in the present disclosure may be applied to embodiments and applications other than those detailed above. It is not intended to limit the present disclosure to the illustrated embodiments, but rather to accord it the widest scope consistent with the principles and features disclosed or suggested herein.

[0033] Note that in the following description, unless otherwise specified, any resistor or resistance mentioned is a discrete device, rather than a simple electrical wire between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the wire between these two points, and such a resistor or resistance cannot be interpreted as a wire. Similarly, unless otherwise specified, any capacitor or capacitance mentioned is a discrete device and not a parasitic element unless otherwise specified. In addition, unless otherwise specified, any inductor or inductance mentioned is a discrete device and not a parasitic element unless otherwise specified.

[0034] Now refer to Figure 3 and 3ADescribe the startup current circuit 10. The startup current circuit 10 includes a high-voltage n-channel transistor M0 (e.g., a transistor capable of maintaining the power supply voltage VIN as its drain-to-source voltage, where VIN is on the order of dozens to hundreds of volts), and a high-voltage n-channel transistor M1. The drain of the high-voltage n-channel transistor M0 is connected to the input voltage node Nin, and its source and gate are connected to the node N0 (e.g., the transistor M0 is diode-coupled). The drain and gate of the high-voltage n-channel transistor M1 are connected to the node N0, and its source is connected to the node Nn (e.g., the transistor M1 is diode-coupled). The drain of the high-voltage n-channel transistor M2 is connected to the node Nin, its source is connected to the node N0, and its gate is connected to the node N2 to receive the feedback voltage VFBK therefrom. The n-channel transistors M0, M1, and M2 are matched (e.g., the same MOS type, the same size).

[0035] In addition, the source and gate of the high-voltage p-channel transistor M7 are connected to the node N1, and its drain is connected to the node Nn. The source of the high-voltage p-channel transistor M5 is connected to the node Nin, its drain and gate are connected to the node N1, while the source of the high-voltage p-channel transistor M6 is connected to the node Nin, and its drain and gate are connected to the node N2. The p-channel transistors M5, M6, and M7 are matched (e.g., the same MOS type, the same size).

[0036] The drain of the high-voltage n-channel transistor M3 is connected to the node N1, its source is coupled to the node Nn through a resistor Rr, and its gate is connected to the node N0. The drain of the high-voltage n-channel transistor M4 is connected to the node N2, its source is connected to the node Nn, and its gate is connected to the node N0.

[0037] When the power supply voltage VIN rises, as Figure 3A shown before time T2 in

[0038]

[0039] As a result of this inequality, the voltage at the node N0 rises, starting to compensate for the leakage current due to the matching of the n-channel transistors M0, M1, and M2 and Increase the gate-to-source VGS voltage of the n-channel transistor M1 in a manner of process or temperature change.

[0040] When the VGS voltage of the n-channel transistor M1 increases, the leakage current starts to flow through it, and this current is copied by the n-channel transistors M3 and M4 because they are in a current mirror arrangement with the n-channel transistor M1. Since the transistor M7 is p-channel, the leakage current absorbed by the n-channel transistor M3 from the node N1 is used to start turning on the transistor M7. Since the p-channel transistors M7 and M5 are matched, this means that the leakage current flowing through the p-channel transistor M5 from the power supply Nin is less than the leakage current flowing through the parallel combination of the p-channel transistor M7 and the n-channel transistor M3, which can be mathematically expressed as:

[0041]

[0042] As a result of this inequality, the voltage at the node N1 continues to drop, starting to increase the gate-to-source voltage of the p-channel transistor M5 and thus increasing the leakage current flowing through M5. Since the p-channel transistors M5 and M6 are in a current mirror relationship, this leakage current is then copied in the transistor M6. Note that the gate voltage of the p-channel transistor M6 (and thus its gate-to-source voltage VGS) is defined by the voltage at the node N1, which in turn is affected by the leakage current flowing through the parallel combination of the p-channel transistor M7 and the n-channel transistor M3.

[0043] Therefore, as Figure 3A shown, before time t1, the voltage VFBK at the node N2 starts to rise, closing the feedback loop with the n-channel transistor N2 and setting the gate-to-source voltage VGS across the n-channel transistor M2. This increase in the current flowing through the n-channel transistor M2 increases the voltage at the node N0 and thus increases the gate-to-source voltage VGS of the n-channel transistor M1. Increasing the VGS of the n-channel transistor M1 in turn increases the VGS of the n-channel transistors M3 and M4. At this point, the startup current circuit 10 thus enters the leakage-free region, where the current I flowing through the n-channel transistor M3 will be controlled by the following relationship:

[0044]

[0045] Here, α = 0.5 is the mirror ratio between the n-channel transistors M3 and M4, and ΔV gs M3 / M4 is the difference between the gate-to-source voltages VGS of the transistors M3 and M4. Therefore, the current I flowing through the n-channel transistor M3 does not depend on the input voltage VIN, but on the resistance of the resistor Rr and the dimensions of the n-channel transistors M3 and M4, asFigure 3A Shown after time T2.

[0046] The startup current circuit 10 can be modified, for example, as Figure 6 shown, where transistor M2 is a p-channel transistor that allows for effective startup performance even at lower supply voltages.

[0047] The design of the startup current circuit 10 helps to ensure that the startup current remains substantially unaffected by the supply voltage VIN, manufacturing process, and temperature. This reduces power consumption and area occupancy, thus providing a consistent startup function under various conditions. Additionally, the design of the startup current circuit 10 maximizes the efficiency of component usage as it employs high-voltage (HV) transistors M0 - M6 but uses low-voltage resistors Rr (e.g., resistors with a safe operating voltage range lower than VIN, such as 1.9V, 3.3V, or 5V). Considering that HV transistors typically occupy less space than HV resistors, this results in a reduction in area occupancy at the same power consumption. This reduces area consumption while maintaining power efficiency. Finally, another advantage in the design of the startup current circuit 10 is that it is independent of the absolute value of leakage current as the startup function relies on transistor matching, making it immune to variations in device modeling or substantial process changes. By focusing on transistor matching rather than leakage current values, the startup current circuit 10 exhibits a level of operating stability and consistency that exceeds prior art methods. Thus, in summary, the design of the startup current circuit 10 offers benefits in terms of energy efficiency, space efficiency, and operating stability.

[0048] Figure 4 and Figure 5 shows an example startup circuit using the startup current circuit 10. Figure 4 The startup circuit 20 corresponding to Figure 1 is the same as

[0049] Figure 5 except that the resistor R is replaced by the startup current circuit 10. Thus, here, the node Nn of the startup current circuit 10 is connected to the node Ng of the startup circuit 20, and the drain of the power transistor T is connected to the node Nin. The source of the power transistor T is coupled to ground through a load (e.g., an internal circuit), and the gate of the power transistor T is coupled to the node Ng. The cathode of the Zener diode Dz is connected to the node Ng, while the anode is connected to ground. This startup circuit 20 is suitable for applications with a relatively high input voltage VIN.

[0049] Figure 5 The startup circuit 30 includes a p-channel transistor M8 that is mirror - arranged with p-channel transistors M5 and M6 and replaces Figure 2A diode D, whose source is connected to the input node Nin, whose drain is connected to the node Ng, and whose gate is connected to the node N1 of the start-up current circuit 10. The cathode of the Zener diode Dz is connected to the node Ng, and its anode is connected to ground. The drain of the power transistor T is connected to the input node Nin, its source is coupled to ground through a load, and its gate is connected to the node Ng. The node Nn is connected to ground. This start-up circuit 30 is suitable for applications with a relatively low input voltage VIN.

[0050] Therefore, note that the start-up current circuit 10 can be used with start-up circuits having a wide input voltage range because of its strong versatility and can be integrated into any high-voltage design that requires low power and compact start-up current generation. This applicability extends to bandgap and linear voltage regulators, whether or not they are directly connected to the supply voltage. These components generally require start-up current to correctly establish the operating point and thus prevent them from stabilizing at any undesired stable point. Depending on application details such as power consumption and area occupancy, the start-up current can be adjusted by simply changing the resistance value.

[0051] In addition, the start-up current generated by the start-up current circuit 10 can be directly utilized or mirrored multiple times with different factors according to specific design requirements, providing a wide range of current values for different applications.

[0052] Finally, it is obvious that modifications and variations can be made to what is described and illustrated herein without departing from the scope of the present disclosure.

[0053] Although the present disclosure has been described with a limited number of embodiments, those skilled in the art who benefit from the present disclosure can conceive of other embodiments that do not deviate from the disclosed scope. In addition, those skilled in the art can conceive of embodiments representing various combinations of the embodiments disclosed herein manufactured in various ways.

Claims

1. A starting circuit, characterized in that: include: Starting current circuit, comprising: a first circuit branch coupled between the input node and the output node, the first circuit branch configured to generate a first current; a second circuit branch coupled between the input node and the output node, the second circuit branch configured to sink current from the first node based on the first current; and a third circuit branch coupled between the input node and the output node, the third circuit branch configured to supply current to a second node based on a voltage at the first node to generate a feedback voltage at the second node; The first circuit branch is configured to increase the first current based on the feedback voltage, thereby increasing the current absorbed by the second circuit branch from the first node and increasing the current supplied by the third circuit branch to the second node, thereby generating a startup current at the output node.

2. The startup circuit according to claim 1, wherein the first circuit branch comprises: a diode-coupled transistor connected between the input node and a third node; a first mirror transistor connected between the third node and the output node and having a control terminal connected to the third node; as well as A feedback transistor is connected between the input node and the third node and has a control terminal coupled to receive the feedback voltage.

3. The starting circuit according to claim 2, wherein the diode-coupled transistor and the first mirror transistor are n-channel transistors, the diode-coupled transistor having a drain connected to the input node, a source connected to the third node, and a gate connected to the third node, and the first mirror transistor having a drain connected to the third node, a source connected to ground, and a gate connected to the third node; and The feedback transistor is an n-channel transistor having a drain connected to the input node, a source connected to the third node, and a gate connected to the second node.

4. The starting circuit according to claim 2, wherein the diode-coupled transistor and the first mirror transistor are n-channel transistors, the diode-coupled transistor having a drain connected to the input node, a source connected to the third node, and a gate connected to the third node, and the first mirror transistor having a drain connected to the third node, a source connected to ground, and a gate connected to the third node; and The feedback transistor is a p-channel transistor having a source connected to the input node, a drain connected to the third node, and a gate connected to the second node.

5. The startup circuit according to claim 2, wherein the second circuit branch comprises: a second mirror transistor connected between the input node and the first node and having a control terminal connected to the first node; an absorption transistor connected between the first node and the output node and having a control terminal connected to the first node; as well as A third mirror transistor is connected between the first node and the output node through a resistor and has a control terminal connected to the third node.

6. The starting circuit according to claim 5, wherein the second mirror transistor and the sink transistor are p-channel transistors, the second mirror transistor having a source connected to the input node, a drain connected to the first node, and a gate connected to the first node, and the sink transistor having a source connected to the first node, a drain connected to ground, and a gate connected to the first node; and The third mirror transistor is an n-channel transistor, a drain of which is connected to the first node, a source of which is coupled to the ground through the resistor, and a gate of which is connected to the third node.

7. The startup circuit according to claim 5, wherein the third circuit branch comprises: a fourth mirror transistor connected between the input node and the second node and having a control terminal connected to the first node, the fourth mirror transistor being in a current mirroring relationship with the second mirror transistor; as well as A fifth mirror transistor is connected between the second node and ground and has a control terminal connected to the third node, the fifth mirror transistor being in a current mirroring relationship with the first mirror transistor.

8. The starting circuit according to claim 7, wherein the fourth mirror transistor is a p-channel transistor having its source connected to the input node, its drain connected to the second node, and its gate connected to the first node; and The fifth mirror transistor is an n-channel transistor having a drain connected to the second node, a source connected to the ground, and a gate connected to the first node.

9. The startup circuit according to claim 1, further comprising: a power transistor connected between the input node and ground via a load, the power transistor having a control terminal connected to the output node; as well as A Zener diode has its cathode connected to the output node and its anode connected to ground.

10. The startup circuit according to claim 1, further comprising: a mirror transistor connected between the input node and a control node, the mirror transistor having a control terminal connected to the first node; a Zener diode having a cathode connected to the control node and an anode connected to the output node, the output node being connected to ground; as well as A power transistor is connected between the input node and ground via a load, the power transistor having a control terminal connected to the control node.

11. A starting circuit, characterized in that: include: Starting current circuit, comprising: a diode-coupled transistor connected between the input node and a third node; a feedback transistor connected between the input node and the first node and having a control terminal coupled to receive a feedback voltage at a second node; a first current mirror having an input connected to the third node and an output connected to the second node; a second current mirror having an input connected to the first node and an output connected to the second node; a first sink transistor connected between the first node and an output node through a resistor and having a control terminal connected to a control node of the first current mirror; and A second absorption transistor is connected between the first node and the output node and has a control terminal connected to the first node.

12. The startup circuit according to claim 11, wherein the first current mirror comprises: a first n-channel transistor having a drain connected to the third node, a source connected to the output node, and a gate connected to the third node; and a second n-channel transistor having a drain connected to the second node, a source connected to the output node, and a gate connected to the third node.

13. The startup circuit of claim 11, wherein the feedback transistor is an n-channel transistor having a drain connected to the input node, a source connected to the third node, and a gate connected to the second node.

14. The startup circuit of claim 11, wherein the feedback transistor is a p-channel transistor having a source connected to the input node, a drain connected to the third node, and a gate connected to the second node.

15. The startup circuit according to claim 11, wherein the second current mirror comprises: a first p-channel transistor having a source connected to the input node, a drain connected to the first node, and a gate connected to the first node; and a second p-channel transistor having a source connected to the input node, a drain connected to the second node, and a gate connected to the first node.

16. The startup circuit of claim 11, wherein the first sink transistor is an n-channel transistor having a drain connected to the first node, a source connected to the output node through the resistor, and a gate connected to the control node of the first current mirror.

17. The startup circuit of claim 11, wherein the second sink transistor is a p-channel transistor having a source and a gate connected to the first node and a drain connected to the output node.

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