Display panel

Abstract

The utility model discloses a display panel which is characterized in that at least one of a pixel electrode in an opening area of a pixel in a first display area and a pixel electrode in an opening area of a pixel in a second display area is not overlapped with a gate insulation layer; according to the spliced display screen, the gate insulating layers in the pixels of the first display area and / or the second display area are removed, the problem of inter-sheet color difference existing between the two display panels of the spliced display screen can be solved, and the display effect of the spliced display screen is improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel. Background Art

[0002] A tiled display screen is a large-sized display device assembled by tiling multiple display panels. When preparing the display panels of the tiled display screen, there is a problem of inter-panel color difference between two adjacent display panels. Summary of the Utility Model

[0003] Embodiments of this application provide a display panel to improve the problem of inter-panel color difference between two adjacent display panels of a tiled display screen.

[0004] In a first aspect, embodiments of this application provide a display panel. The display panel includes a first display area and a second display area. The second display area surrounds the first display area and is located at the edge of the display panel. The display panel further includes a substrate and pixels disposed on the substrate. The pixels include thin-film transistors and pixel electrodes, and the pixel electrodes are electrically connected to the thin-film transistors.

[0005] The thin-film transistors include:

[0006] Gate electrodes;

[0007] Gate insulating layers covering the gate electrodes;

[0008] Active layers disposed on the surfaces of the gate insulating layers away from the substrates;

[0009] Source / drain electrodes disposed on the sides of the active layers away from the substrates;

[0010] In a top view of the display panel, at least one of the pixel electrodes in the opening areas of the pixels in the first display area and the pixel electrodes in the opening areas of the pixels in the second display area does not overlap with the gate insulating layer.

[0011] Further, in a top view of the display panel, the pixel electrodes in the opening areas of the pixels in the first display area do not overlap with the gate insulating layer, and the pixel electrodes in the opening areas of the pixels in the second display area do not overlap with the gate insulating layer.

[0012] Further, in a top view of the display panel, the pixel electrodes in the opening areas of the pixels in the first display area overlap with the gate insulating layer, and the pixel electrodes in the opening areas of the pixels in the second display area do not overlap with the gate insulating layer.

[0013] Further, the thickness of the gate insulating layer overlapping with the pixel electrode in the opening area of the pixel in the first display area is

[0014] Further, the display panel further includes a first passivation layer and a first organic planarization layer. The first passivation layer is located on a surface of the film layer where the source and drain electrodes are located, away from the substrate. The first organic planarization layer is located on a surface of the first passivation layer, away from the substrate. The sum of the thickness of the first passivation layer of the pixel in the first display area, the thickness of the first organic planarization layer of the pixel in the first display area, and the thickness of the gate insulating layer of the pixel in the first display area is equal to the sum of the thickness of the first passivation layer of the pixel in the second display area and the thickness of the first organic planarization layer of the pixel in the second display area.

[0015] Further, the distance from the gate insulating layer overlapping with the pixel electrode in the opening area of the pixel in the first display area to the first edge of the display panel is equal to the distance from the gate insulating layer overlapping with the pixel electrode in the opening area of the pixel in the first display area to the second edge of the display panel, where the first edge is parallel to the length direction of the display panel, and the second edge is parallel to the width direction of the display panel.

[0016] Further, the distance from the gate insulating layer overlapping with the pixel electrode in the opening area of the pixel in the first display area to the first edge of the display panel is not equal to the distance from the gate insulating layer overlapping with the pixel electrode in the opening area of the pixel in the first display area to the second edge of the display panel, where the first edge is parallel to the length direction of the display panel, and the second edge is parallel to the width direction of the display panel.

[0017] Further, in a top view of the display panel, the pixel electrode in the opening area of the pixel in the first display area does not overlap with the gate insulating layer, and the pixel electrode in the opening area of the pixel in the second display area overlaps with the gate insulating layer.

[0018] Further, the thickness of the gate insulating layer overlapping with the pixel electrode in the opening area of the pixel in the second display area is

[0019] Further, the display panel further includes a second passivation layer and a second organic planarization layer. The second passivation layer is located on a surface of the film layer where the source and drain electrodes are located, away from the substrate. The second organic planarization layer is located on a surface of the second passivation layer, away from the substrate. The sum of the thickness of the second passivation layer and the thickness of the second organic planarization layer of the pixel located in the first display area is equal to the sum of the thickness of the second passivation layer of the pixel located in the second display area, the thickness of the second organic planarization layer of the pixel located in the second display area, and the thickness of the gate insulating layer of the pixel located in the second display area.

[0020] Advantages of the present application:

[0021] The present application provides a display panel. By setting at least one of the pixel electrodes in the opening areas of the pixels located in the first display area and the pixel electrodes in the opening areas of the pixels located in the second display area not to overlap with the gate insulating layer, the gate insulating layer in the pixels located in the first display area and / or the second display area is removed, which can improve the problem of inter-panel color difference existing between the two display panels of the tiled display screen, thereby enhancing the display effect of the tiled display screen. Description of the Drawings

[0022] Figure 1 is a schematic diagram of the first display panel of the present application;

[0023] Figure 2 is Figure 1 a schematic diagram of the pixel in the first display area or the second display area of the display panel shown;

[0024] Figure 3 is Figure 2 a cross-sectional view of the pixel at the A-A' position of the display panel shown;

[0025] Figure 4 is a schematic diagram of the second display panel of the present application;

[0026] Figure 5 is Figure 4 a schematic diagram of the pixel in the second display area of the display panel shown;

[0027] Figure 6 is Figure 5 a cross-sectional view of the pixel at the B-B' position of the display panel shown;

[0028] Figure 7 is a schematic diagram of the third display panel of the present application;

[0029] Figure 8 is Figure 7Schematic diagram of pixels in the second display area of the display panel shown;

[0030] Figure 9 is Figure 8 Cross-sectional view of the C-C' position of the pixels of the display panel shown.

[0031] 100 - First display area, 200 - Second display area, 300 - Substrate; 400 - Pixel, 410 - Thin-film transistor, 411 - Gate, 412 - Gate insulating layer, 413 - Active layer, 414 - Source / drain; 420 - Pixel electrode; 430 - First passivation layer, 440 - First organic planarization layer, 450 - Second passivation layer, 460 - Second organic planarization layer, 470 - Third passivation layer, 480 - Third organic planarization layer, 490 - Opening area. Detailed implementation manner

[0032] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The technical solutions described below are only used to explain and illustrate the idea of the present application, and should not be regarded as a limitation on the protection scope of the present application.

[0033] In addition, terms such as "first", "second" and similar words do not represent any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0034] The first embodiment of the present application provides a display panel. Referring to Figures 1-3 , the display panel includes a first display area 100 and a second display area 200. The second display area 200 surrounds the first display area 100, and the second display area 200 is located at the edge of the display panel. The display panel further includes a substrate 300 and pixels 400 disposed on the substrate 300. The pixels 400 include thin-film transistors 410 and pixel electrodes 420. The pixel electrodes 420 are electrically connected to the thin-film transistors 410; the thin-film transistors 410 include gates 411, gate insulating layers 412, active layers 413 and source / drains 414; the gate insulating layers 412 cover the gates 411; the active layers 413 are disposed on the surface of the gate insulating layers 412 on the side away from the substrate 300; the source / drains 414 are disposed on the side of the active layers 413 away from the substrate 300; in the top view of the display panel, the pixel electrodes 420 in the opening areas 490 of the pixels 400 located in the first display area 100 do not overlap with the gate insulating layers 412, and the pixel electrodes 420 in the opening areas 490 of the pixels 400 located in the second display area 200 do not overlap with the gate insulating layers 412.

[0035] By setting the pixel electrode 420 within the opening region 490 of the pixel 400 located in the first display area 100 not to overlap with the gate insulating layer 412, and the pixel electrode 420 within the opening region 490 of the pixel 400 located in the second display area 200 not to overlap with the gate insulating layer 412, the gate insulating layer 412 within the pixel 400 in the first display area 100 and the second display area 200 is removed, avoiding the problem of red or green deviation of the pixel 400 of the display panel caused by the film thickness fluctuation of the gate insulating layer 412 in the pixel 400 of the first display area 100 and the second display area 200 of the display panel, reducing the risk of the uniformity of the color dots in the pixel 400 area of the display panel of the tiled display screen being reduced due to the uneven film thickness of the gate insulating layer 412 of the display panel, thereby improving the problem of inter-panel color difference existing between the two display panels of the tiled display screen and enhancing the display effect of the tiled display screen.

[0036] In this embodiment, referring to Figure 3 , the display panel further includes a third passivation layer 470 and a third organic planarization layer 480. The third passivation layer 470 is located on a surface of the film layer where the source-drain electrodes 414 are located, away from the substrate 300, and the third organic planarization layer 480 is located on a surface of the third passivation layer 470, away from the substrate 300; in the top view of the display panel, the third passivation layer 470 of the pixel 400 located in the first display area 100 does not overlap with the gate insulating layer 412, the third passivation layer 470 of the pixel 400 located in the second display area 200 does not overlap with the gate insulating layer 412, the third organic planarization layer 480 of the pixel 400 located in the first display area 100 does not overlap with the gate insulating layer 412, and the third organic planarization layer 480 of the pixel 400 located in the second display area 200 does not overlap with the gate insulating layer 412.

[0037] In this embodiment, the pixel includes an opening region 490 and a thin-film transistor device region, wherein the thin-film transistor 410 is located in the thin-film transistor device region.

[0038] The second embodiment of the present application provides a second type of display panel. Referring to Figures 4-6, the display panel includes a first display area 100 and a second display area 200. The second display area 200 surrounds the first display area 100, and the second display area 200 is located at the edge of the display panel. The display panel further includes a substrate 300 and pixels 400 disposed on the substrate 300. The pixels 400 include thin film transistors 410 and pixel electrodes 420. The pixel electrodes 420 are electrically connected to the thin film transistors 410. The thin film transistors 410 include gates 411, gate insulating layers 412, active layers 413, and source / drain electrodes 414. The gate insulating layers 412 cover the gates 411. The active layers 413 are disposed on the surfaces of the gate insulating layers 412 away from the substrate 300. The source / drain electrodes 414 are disposed on the sides of the active layers 413 away from the substrate 300. In a top view of the display panel, the pixel electrodes 420 within the opening regions 490 of the pixels 400 located in the first display area 100 overlap with the gate insulating layers 412, and the pixel electrodes 420 within the opening regions 490 of the pixels 400 located in the second display area 200 do not overlap with the gate insulating layers 412.

[0039] By setting that the pixel electrodes 420 within the opening regions 490 of the pixels 400 located in the first display area 100 overlap with the gate insulating layers 412, and the pixel electrodes 420 within the opening regions 490 of the pixels 400 located in the second display area 200 do not overlap with the gate insulating layers 412, the gate insulating layers 412 within the pixels 400 located in the second display area 200 are removed, improving the problem that the second display area 200 is greener than the first display area 100 due to mechanical interference at the edge of the tiled display screen, thereby improving the problem of inter-panel color difference between the two display panels of the tiled display screen and enhancing the display effect of the tiled display screen.

[0040] In this embodiment, the pixel includes an opening region 490 and a thin film transistor device region, wherein the thin film transistor 410 is located in the thin film transistor device region.

[0041] In this embodiment, the thickness of the gate insulating layer 412 overlapping with the pixel electrode 420 within the opening region 490 of the pixel 400 in the first display area 100 is By setting the thickness of the gate insulating layer 412 overlapping with the pixel electrode 420 within the opening region 490 of the pixel 400 in the first display area 100 to be the color dot difference between the first display area 100 and the second display area 200 can be compensated, thereby improving the problem of greenish edges of the display panel.

[0042] In this embodiment, referring to Figure 6, the display panel further includes a first passivation layer 430 and a first organic planarization layer 440. The first passivation layer 430 is located on a surface of the film layer where the source and drain electrodes 414 are located, away from the substrate 300. The first organic planarization layer 440 is located on a surface of the passivation layer away from the substrate 300. The sum of the thickness of the first passivation layer 430 of the pixel 400 located in the first display area 100, the thickness of the first organic planarization layer 440 of the pixel 400 located in the first display area 100, and the thickness of the gate insulating layer 412 of the pixel 400 located in the first display area 100 is equal to the sum of the thickness of the first passivation layer 430 of the pixel 400 located in the second display area 200 and the thickness of the first organic planarization layer 440 of the pixel 400 located in the second display area 200.

[0043] In a top view of the display panel, the first passivation layer 430 of the pixel 400 located in the second display area 200 does not overlap with the gate insulating layer 412.

[0044] In a top view of the display panel, the first organic planarization layer 440 of the pixel 400 located in the second display area 200 does not overlap with the gate insulating layer 412.

[0045] In this embodiment, referring to Figure 4 , the distance from the gate insulating layer 412 overlapping with the pixel electrode 420 in the opening area 490 of the pixel 400 located in the first display area 100 to the first edge of the display panel is equal to the distance from the gate insulating layer 412 overlapping with the pixel electrode 420 in the opening area 490 of the pixel 400 located in the first display area 100 to the second edge of the display panel, where the first edge is parallel to the length direction of the display panel, and the second edge is parallel to the width direction of the display panel.

[0046] In this embodiment, referring to Figure 4 , the distance from the gate insulating layer 412 overlapping with the pixel electrode 420 in the opening area 490 of the pixel 400 located in the first display area 100 to the first edge of the display panel is not equal to the distance from the gate insulating layer 412 overlapping with the pixel electrode 420 in the opening area 490 of the pixel 400 located in the first display area 100 to the second edge of the display panel, where the first edge is parallel to the length direction of the display panel, and the second edge is parallel to the width direction of the display panel.

[0047] The third embodiment of the present application provides a third display panel, referring to Figures 7-9, the display panel includes a first display area 100 and a second display area 200. The second display area 200 surrounds the first display area 100, and the second display area 200 is located at the edge of the display panel. The display panel further includes a substrate 300 and pixels 400 disposed on the substrate 300. The pixels 400 include thin film transistors 410 and pixel electrodes 420, and the pixel electrodes 420 are electrically connected to the thin film transistors 410; the thin film transistors 410 include gates 411, gate insulating layers 412, active layers 413, and source / drain electrodes 414; the gate insulating layers 412 cover the gates 411; the active layers 413 are disposed on the surface of the gate insulating layers 412 on the side away from the substrate 300; the source / drain electrodes 414 are disposed on the side of the active layers 413 away from the substrate 300; in a top view of the display panel, the pixel electrodes 420 in the opening areas 490 of the pixels 400 located in the first display area 100 do not overlap with the gate insulating layers 412, and the pixel electrodes 420 in the opening areas 490 of the pixels 400 located in the second display area 200 overlap with the gate insulating layers 412.

[0048] By setting that the pixel electrodes 420 in the opening areas 490 of the pixels 400 located in the first display area 100 do not overlap with the gate insulating layers 412, and the pixel electrodes 420 in the opening areas 490 of the pixels 400 located in the second display area 200 overlap with the gate insulating layers 412, the gate insulating layers 412 in the pixels 400 located in the first display area 100 are removed, which can improve the problem of the brightness difference between the first display area 100 and the second display area 200 caused by abnormal light emission of the light beads in the first display area 100 of the display screen, thereby improving the problem of the color difference between the splicing display screens and enhancing the display effect of the splicing display screens.

[0049] In this embodiment, the pixel includes an opening area 490 and a thin film transistor device area, wherein the thin film transistor 410 is located in the thin film transistor device area.

[0050] In this embodiment, the thickness of the gate insulating layer 412 overlapping with the pixel electrode 420 in the opening area 490 of the pixel 400 in the second display area 200 is

[0051] In this embodiment, referring to Figure 9, the display panel further includes a second passivation layer 450 and a second organic planarization layer 460. The second passivation layer 450 is located on a surface of the film layer where the source and drain electrodes 414 are located, away from the substrate 300. The second organic planarization layer 460 is located on a surface of the passivation layer away from the substrate 300. The sum of the thickness of the second passivation layer 450 and the thickness of the second organic planarization layer 460 of the pixel 400 located in the first display area 100 is equal to the sum of the thickness of the second passivation layer 450 of the pixel 400 located in the second display area 200, the thickness of the second organic planarization layer 460 of the pixel 400 located in the second display area 200, and the thickness of the gate insulating layer 412 of the pixel 400 located in the second display area 200.

[0052] In a top view of the display panel, the second passivation layer 450 of the pixel 400 located in the first display area 100 does not overlap with the gate insulating layer 412.

[0053] In a top view of the display panel, the second organic planarization layer 460 of the pixel 400 located in the first display area 100 does not overlap with the gate insulating layer 412.

[0054] The fourth embodiment of the present application provides a tiled display screen, and the tiled display screen includes the display panel described above.

[0055] The technical solution of the present application is specifically as follows:

[0056] The tiled display screen is a large-sized display device assembled by tiling multiple display panels. When preparing the display panel of the tiled display screen, the gate insulating layer in the display area of the display panel of the tiled display screen is prone to the problem of uneven film thickness. When the film thickness of the gate insulating layer 412 changes, the color difference changes periodically from greenish to reddish.

[0057] The display panel of the traditional tiled display screen ensures the color point uniformity through the RGB dithering and color demura methods. Among them, the principle of RGB dithering is to reduce the brightness of a certain color to achieve different color point specifications to meet the single demand of different color point specifications. Color demura is a technology to remove the defect of uneven chromaticity to compensate for the uneven chromaticity of the display panel. The above solutions are generally based on the color point standard of 9 evenly distributed points on the display panel. For a large-sized display panel, it is impossible to ensure the color point uniformity of each pixel 400 area of the display panel of the entire tiled display screen. Therefore, how to improve the color point uniformity of the pixel 400 area of the display panel of the tiled display screen and improve the problem of inter-panel color difference between the two display panels of the tiled display screen is an urgent problem to be solved at present.

[0058] Therefore, the technical solution of the present application provides a first display panel. By setting the pixel electrode 420 in the opening area 490 of the pixel 400 located in the first display area 100 not to overlap with the gate insulating layer 412, and the pixel electrode 420 in the opening area 490 of the pixel 400 located in the second display area 200 not to overlap with the gate insulating layer 412, the gate insulating layer 412 in the pixel 400 of the first display area 100 and the second display area 200 is removed, avoiding the problem of red or green deviation of the pixel 400 of the display panel caused by the film thickness fluctuation of the gate insulating layer 412 in the pixel 400 of the first display area 100 and the second display area 200 of the display panel, reducing the risk of reducing the uniformity of color dots in the pixel 400 area of the display panel of the tiled display screen due to the uneven film thickness of the gate insulating layer 412 of the display panel, thereby improving the problem of inter-panel color difference between the two display panels of the tiled display screen.

[0059] At the same time, the technical solution of the present application provides a second display panel. By setting the pixel electrode 420 in the opening area 490 of the pixel 400 located in the first display area 100 to overlap with the gate insulating layer 412, and the pixel electrode 420 in the opening area 490 of the pixel 400 located in the second display area 200 not to overlap with the gate insulating layer 412, the gate insulating layer 412 in the pixel 400 of the second display area 200 is removed, enabling the color dot difference between the first display area 100 and the second display area 200 to be compensated, and improving the green deviation phenomenon of the second display area 200 of the display panel relative to the first display area 100 caused by mechanical interference at the edge of the lamp bead module of the display panel of the tiled display screen, thereby improving the problem of inter-panel color difference between the two display panels of the tiled display screen; at the same time, compared with the traditional method of using RGB dithering and color demura, the production cost of the display panel can be reduced.

[0060] The above has made a detailed description of the specific implementation manners of the present application. The above-described embodiments disclosed in the present application are only the preferred embodiments of the present application. For those of ordinary skill in the art, many deformations and improvements can be made without departing from the concept of the present application. These deformations and improvements all fall within the protection scope defined by the claims of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a first display area and a second display area, the second display area surrounds the first display area, and the second display area is located at an edge of the display panel, the display panel also includes a substrate and a pixel disposed on the substrate, the pixel includes a thin film transistor and a pixel electrode, and the pixel electrode is electrically connected to the thin film transistor; The thin film transistor comprises: Gate; a gate insulating layer, wherein the gate insulating layer covers the gate; an active layer, the active layer being disposed on a surface of the gate insulating layer away from the substrate; Source and drain electrodes, the source and drain electrodes are arranged on a side of the active layer away from the substrate; In the top view of the display panel, at least one of the pixel electrode in the opening area of ​​the pixel in the first display area and the pixel electrode in the opening area of ​​the pixel in the second display area does not overlap with the gate insulating layer.

2. The display panel according to claim 1, characterized in that: In the top view of the display panel, the pixel electrode in the opening area of ​​the pixel in the first display area does not overlap with the gate insulating layer, and the pixel electrode in the opening area of ​​the pixel in the second display area does not overlap with the gate insulating layer.

3. The display panel according to claim 1, characterized in that: In the top view of the display panel, the pixel electrode in the opening area of ​​the pixel in the first display area overlaps with the gate insulating layer, and the pixel electrode in the opening area of ​​the pixel in the second display area does not overlap with the gate insulating layer.

4. The display panel according to claim 3, characterized in that: The thickness of the gate insulating layer overlapping the pixel electrode in the opening area of ​​the pixel in the first display area is 5. The display panel according to claim 3, characterized in that: The display panel also includes a first passivation layer and a first organic planarization layer, the first passivation layer is located on a surface of the film layer where the source and drain electrodes are located away from the substrate, the first organic planarization layer is located on a surface of the first passivation layer away from the substrate, and the sum of the thickness of the first passivation layer of the pixel located in the first display area, the thickness of the first organic planarization layer of the pixel located in the first display area, and the thickness of the gate insulation layer of the pixel located in the first display area is equal to the sum of the thickness of the first passivation layer of the pixel located in the second display area and the thickness of the first organic planarization layer of the pixel located in the second display area.

6. The display panel according to claim 3, characterized in that: The distance from the gate insulating layer overlapping with the pixel electrode in the opening area of ​​the pixel located in the first display area to the first edge of the display panel is equal to the distance from the gate insulating layer overlapping with the pixel electrode in the opening area of ​​the pixel located in the first display area to the second edge of the display panel, wherein the first edge is parallel to the length direction of the display panel and the second edge is parallel to the width direction of the display panel.

7. The display panel according to claim 3, characterized in that: A distance from the gate insulating layer overlapping with the pixel electrode in the opening area of ​​the pixel located in the first display area to a first edge of the display panel is not equal to a distance from the gate insulating layer overlapping with the pixel electrode in the opening area of ​​the pixel located in the first display area to a second edge of the display panel, wherein the first edge is parallel to the length direction of the display panel, and the second edge is parallel to the width direction of the display panel.

8. The display panel according to claim 1, characterized in that: In the top view of the display panel, the pixel electrode in the opening area of ​​the pixel in the first display area does not overlap with the gate insulating layer, and the pixel electrode in the opening area of ​​the pixel in the second display area overlaps with the gate insulating layer.

9. The display panel according to claim 8, characterized in that: The thickness of the gate insulating layer overlapping the pixel electrode in the opening area of ​​the pixel in the second display area is 10. The display panel according to claim 8, characterized in that: The display panel also includes a second passivation layer and a second organic planar layer, the second passivation layer is located on a surface of the film layer where the source and drain electrodes are located away from the substrate, the second organic planar layer is located on a surface of the second passivation layer away from the substrate, and the sum of the thickness of the second passivation layer of the pixel located in the first display area and the thickness of the second organic planar layer of the pixel located in the first display area is equal to the sum of the thickness of the second passivation layer of the pixel located in the second display area, the thickness of the second organic planar layer of the pixel located in the second display area, and the thickness of the gate insulating layer of the pixel located in the second display area.

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