Test circuit and system compatible with avalanche test and double-pulse test
By designing a test circuit that is compatible with avalanche test and double pulse test, and using the conversion switch SW2 to change the circuit structure, the problem of requiring two test boards in the existing technology is solved, and efficient and low-cost testing is achieved.
Patent Information
- Application Number
- CN202422086354.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-08-27
AI Technical Summary
The prior art requires the design and manufacture of two test boards for avalanche testing and double pulse testing, which increases the cost and complexity of testing.
Design a test circuit that is compatible with avalanche test and double pulse test. The circuit structure is changed by switching switch SW2, without changing the test board, and testing with different parameters is achieved.
Reduces the complexity and cost of testing, improves testing efficiency and accuracy, and simplifies the testing process.
Smart Images
Figure CN223065435U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the field of electronic circuits, and in particular relates to a test circuit and system compatible with avalanche test and double pulse test. Background Art
[0002] As important power devices, the parameters of MOSFET / IGBT can be divided into static parameters and dynamic parameters. The static parameters mainly refer to the inherent parameters that are independent of their working conditions. The relevant parameters mainly include: gate turn-on voltage, gate breakdown voltage, collector-emitter breakdown voltage, collector-emitter leakage current, parasitic capacitance, input capacitance, transfer capacitance, output capacitance, etc.; the dynamic parameters refer to the relevant parameters during the switching process, and these parameters will change with the change of switching conditions such as voltage, working current, drive voltage, drive resistance, etc. The relevant parameters mainly include: gate charge, turn-on delay time, rise time, turn-off delay time, fall time, turn-on loss, turn-off loss, reverse recovery current, reverse recovery time, and reverse recovery energy, etc.
[0003] In order to evaluate the dynamic parameters of power devices, the commonly used measurement method is double pulse test. The double pulse test is to control the on and off of the device under test through two pulses, and then test some parameter indicators during the on and off process.
[0004] In order to test the maximum energy that a power device can withstand in a single avalanche state, the prior art conducts avalanche tests on the device. Avalanche test usually refers to EAS, that is, single pulse avalanche energy, which defines the maximum energy that the device can withstand in a single avalanche state.
[0005] In order to implement double pulse test and avalanche test to ensure that the power device meets the design requirements, the prior art conducts double pulse test and avalanche test independently, and two different test boards need to be designed and manufactured, which increases the cost and test complexity. Summary of the Utility Model
[0006] To solve the technical problems existing in the prior art, the purpose of the present utility model here is to provide a test circuit compatible with avalanche test and double pulse test. This circuit can realize avalanche test and double pulse test, without replacing the test board, can effectively reduce the test cost and complexity, and improve the test efficiency.
[0007] The provided test circuit is configured to include an inductor L, a diode D1, and a switch SW2. One end of the inductor L is used as the first connection end of the circuit for connecting the power supply VCC, and the other end is used as the second connection end of the circuit for connecting the device under test; the diode D1 and the switch SW2 are connected in series and then connected in parallel with the inductor L.
[0008] In some embodiments, the present circuit further includes a switching device Q3. The first end of the switching device Q3 is connected to the first connection end, and the second end serves as the third connection end of the circuit for driving signal access; the third end is for power supply VCC access.
[0009] In some embodiments, the switching device Q3 and the device under test share a driving signal.
[0010] In some embodiments, the present test circuit further includes a light-emitting diode and a current-limiting resistor R.
[0011] In some embodiments, the present test circuit further includes a change-over switch SW1 connected in series with the inductor L.
[0012] In some embodiments, the present test circuit further includes a filter capacitor C.
[0013] In some embodiments, the diode D1 is the body diode of a power device.
[0014] In some embodiments, the device under test is a MOSFET.
[0015] The present utility model further provides a test system compatible with avalanche testing and double-pulse testing. The system includes a test circuit and a probe for obtaining parameters of the device under test, and the test circuit is the test circuit provided by the present utility model.
[0016] In some embodiments, the probe includes a differential probe for obtaining the inter-electrode voltage and a current probe for obtaining the pole current.
[0017] The beneficial effects of the present utility model include:
[0018] 1) The present circuit is configured with a change-over switch. By changing the circuit structure through the change-over switch for double-pulse testing and avalanche testing, there is no need to replace the test board, reducing the complexity of the test; and by changing the circuit structure through the change-over switch, double-pulse testing and avalanche testing can be achieved, meeting the purpose of testing different parameters and improving the test efficiency.
[0019] 2) The present circuit is configured with a light-emitting diode for failure indication when the device under test fails due to a short circuit, improving the reliability of the test.
[0020] 3) The present circuit is configured with a switching device Q3 as an auxiliary test device, and the switching device Q3 and the device under test share the same driving signal, improving the accuracy of the test data. Description of the Drawings
[0021] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required or involved in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. Without creative efforts, other drawings can be obtained based on these drawings:
[0022] Figure 1 The circuit schematic diagram of the test circuit provided by the present utility model;
[0023] Figures 2-5 The circuit schematic diagram when this test circuit is used for double-pulse testing;
[0024] Figure 6 The circuit schematic diagram when this test circuit is used for avalanche testing;
[0025] Figure 7 The waveform diagram when this test circuit is used for avalanche testing;
[0026] In the figure, the direction indicated by the arrow of the line with an arrow is the current direction;
[0027] Figure 7 Among them: IAS: The maximum current passing through during the turn-on time of the device under test, Tp: The pulse high-level time of the device under test (i.e., the turn-on time of the device under test or the energy storage time for the inductor), Tav: The energy release time of the inductor; VDD: The power input voltage, that is Figures 1-6 The VCC in, BVDSS: The back electromotive force generated by the inductor energy release, the sum of the two superimposed on the input voltage; I D(t) The time function of the drain current of the device under test; V DS(t) The time function of the drain-source voltage of the device under test. Specific embodiments
[0028] This part describes the present utility model more comprehensively with reference to the drawings, and illustrative embodiments of the present utility model are shown in the drawings. However, the present utility model can be embodied in many different forms and should not be construed as limited to the embodiments described herein. On the contrary, these embodiments are provided so that this disclosure is complete and full, and the scope of the present utility model is fully conveyed to those skilled in the art.
[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. It will be further understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless specifically defined herein.
[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this utility model will be more complete and comprehensive, and the concept of the example embodiments will be fully conveyed to those skilled in the art.
[0031] Embodiment 1
[0032] Please refer to Figure 1 , the test circuit provided in this embodiment is configured to include an inductor L, a diode D1, and a switch SW2. One end of the inductor L serves as the first connection end of the circuit for connecting to the power supply VCC, and the other end serves as the second connection end of the circuit for connecting to the device under test; the diode D1 and the switch SW2 are connected in series and then connected in parallel with the inductor L.
[0033] Here, taking the device under test as an N-type MOSFET as an example to illustrate the principle of this circuit being used for double-pulse testing and avalanche testing. When this test circuit is used for double-pulse testing, the switch SW2 is turned on, and it is connected according to the Figure 2 shown connection relationship, where Q2 is the device under test; the drive signal is a double-pulse signal, and the double-pulse signal controls the on and off of Q2 through high and low levels. The differential probe is used to capture the VDS and VGS of the device Q2 under test respectively, and the current probe captures the position of the current flowing out of the source of the device Q2 under test. The parameters captured by the probe are the parameters of the test switching time of the Q2 device, and the switching time parameters of Q2 can be obtained by cooperating with an oscilloscope.
[0034] The specific process of double-pulse testing is as follows:
[0035] In the first stage, as Figure 3 shown, at time T0, the drive signal is at a high level, and the device under test Q2 is turned on. At this time, the loop is as shown by the arrowed line in the figure. Since the current in the inductor L cannot change suddenly, the captured Is rises linearly.
[0036] In the second stage, as Figure 4 shown, at time T1, the drive signal is at a low level, and the device under test Q2 is turned off. At this time, the loop is as shown by the arrowed line in the figure. Since the current in the inductor L is consumed by the diode D1 as a freewheeling loop to dissipate the energy in the inductor, the captured Is drops linearly at this time.
[0037] In the third stage, as Figure 5 shown, at time T2, the second pulse is at a high level again, and the device under test Q2 is turned on. At this time, the diode D1 enters reverse recovery, and the reverse recovery current will pass through the device under test Q2. The captured Is at this time is the reverse recovery current.
[0038] When this test circuit is used for avalanche testing, the switch SW2 is turned off, and it is connected according to the Figure 6Connect according to the shown connection relationship, where Q2 is the device under test; the drive signal is a single-pulse waveform. The single pulse controls the conduction and cutoff of the device Q2 through high and low levels. When the single pulse is at a high level, the device Q2 conducts, and the power supply in the circuit charges the inductor L. When the single pulse is at a low level, the device Q2 cuts off, and the energy stored in the inductor discharges at this time. The energy impacts the device under test Q2 until avalanche breakdown; control the time of the high level of the control pulse, the magnitude of the current, and the avalanche energy to impact the device under test Q2. The differential probe respectively captures VDS and VGS of the device under test Q2, and the current probe captures the position of the current flowing out of the source of the device, for the avalanche test of the device Q2. With the cooperation of an oscilloscope, the relevant parameters of Q2 can be obtained.
[0039] The avalanche test drive signal is a single-pulse signal, and the magnitude of the current is controlled by controlling the time of the high level of the single pulse; when the drive signal is at a high level, the device under test conducts, and the power supply VCC charges the inductor. When the drive signal is at a low level, the device under test cuts off, and at this time, the energy released by the inductor impacts the device under test, as Figure 7 The gray interval of Iav is the magnitude of the energy released by the inductor. The following is the calculation formula for avalanche energy, which is the integral of the voltage multiplied by the current over time during the time period when the inductor releases energy:
[0040]
[0041] In the formula, u represents the voltage across the inductor, i represents the current on the inductor, and t represents the time when the inductor releases energy.
[0042] Embodiment 2
[0043] Please refer to again Figure 1 , the test circuit in this embodiment includes a switching device Q3, an inductor L, a diode D1, and a changeover switch SW2. The third terminal of the switching device Q3 is used as the first connection terminal of the circuit for connecting the power supply VCC; the second terminal is used as the third connection terminal of the circuit for connecting the control signal; the third terminal is connected to one end of the inductor L, and the other end of the inductor L is used as the second connection terminal of the circuit for connecting the device under test; the diode D1 and the changeover switch SW2 are connected in series and then connected in parallel with the inductor L.
[0044] When the switching device Q3 is used for double-pulse testing and avalanche testing in this test circuit, when the device under test Q2 conducts, the switching device Q3 also conducts; when the device under test Q2 cuts off, the switching device Q3 also cuts off. The conduction and cutoff of the switching device Q3 connect and disconnect the power supply VCC.
[0045] Here, taking the device under test as an N-type MOSFET as an example to illustrate the principle of this circuit being used for double-pulse testing and avalanche testing. When this test circuit is used for double-pulse testing, the changeover switch SW2 is turned on, according to Figure 2Connect according to the shown connection relationship, where Q2 is the device under test; the drive signal is a double-pulse signal, and the double-pulse signal controls the turn-on and turn-off of Q2 and Q3 through high and low levels. Use differential probes to respectively capture VDS and VGS of the Q2 device under test, and use a current probe to capture the position of the current flowing out of the source of the Q2 device under test. The parameters captured by the probes are the parameters for testing the switching time of the Q2 device.
[0046] The specific process of the double-pulse test is as follows:
[0047] In the first stage, as Figure 3 shown, at time T0, the drive signal is at a high level, and the device under test Q2 and the switching device Q3 are turned on. At this time, the loop is as shown by the arrowed line in the figure. Since the current in the inductor L cannot change suddenly, the captured Is rises linearly.
[0048] In the second stage, as Figure 4 shown, at time T1, the drive signal is at a low level, and the device under test Q2 and the switching device Q3 are turned off. At this time, the loop is as shown by the arrowed line in the figure. Since the current in the inductor L is consumed by the diode D1 as a freewheeling loop to dissipate the energy in the inductor, the captured Is drops linearly at this time.
[0049] In the third stage, as Figure 5 shown, at time T2, the second pulse is at a high level again, and the device under test Q2 and the switching device Q3 are turned on. At this time, the diode D1 enters reverse recovery, and the reverse recovery current will pass through the device under test Q2. At this time, the captured Is rises linearly and has a reverse recovery current (the Is current spike).
[0050] When this test circuit is used for avalanche testing, the switch SW2 is disconnected and connected according to the Figure 6 shown connection relationship, where Q2 is the device under test; the drive signal is a single-pulse waveform, and the single pulse controls the turn-on and turn-off of devices Q2 and Q3 through high and low levels. When the single pulse is at a high level, devices Q2 and Q3 are turned on, and the power supply in the circuit charges the inductor L. When the single pulse is at a low level, devices SQ2 and Q3 are turned off, and the energy stored in the inductor is discharged at this time. The energy impacts the device under test Q2 until avalanche breakdown; according to I = Ut / L (where U is the VDS of the device under test Q2, t is the time of the high level of the pulse, and L is the size of the inductor), controlling the time of the high level of the pulse can control the magnitude of the current and the avalanche energy impacting the Q2 device under test. Differential probes respectively capture VDS and VGS of the Q2 device under test, and a current probe captures the position of the current flowing out of the source of the device, for the avalanche test of the Q2 device.
[0051] The principle of using the test circuit of this embodiment for avalanche testing is the same as that of Embodiment 1 and will not be elaborated here.
[0052] In this test circuit, Q2 and Q3 share a driving signal. When Q3 conducts, the test circuit is powered on, and at the same time, Q2 also conducts. When both Q2 and Q3 are turned off, the test circuit loop is disconnected. In this state, only the inductor L stores electrical energy, and the energy stored in the inductor discharges at this time. The energy impacts the device under test Q2 until avalanche breakdown. This ensures that the current of the avalanche test device completely comes from the energy on the inductor, making the test data more accurate.
[0053] Add Q3 as an auxiliary device to cut off the intervention of the power supply VCC. During the avalanche test, ensure that the energy impacting the Q2 device after Q2 and Q3 are turned off only comes from the inductor L, so that the test can be more accurate.
[0054] Embodiment III
[0055] The test circuit provided in this embodiment includes all the technical features of the test circuit provided in Embodiment I, and also adds a light-emitting diode (LED) and a resistor R. The cathode of the light-emitting diode is connected to one end of the inductor L as one end of the first connection terminal of the circuit, and the anode is connected to one end of the resistor R. The other end of the resistor R is used as the fourth connection terminal of the circuit for low-power supply access.
[0056] Embodiment IV
[0057] The test circuit provided in this embodiment includes all the technical features of the test circuit provided in Embodiment II, and also adds a light-emitting diode (LED) and a resistor R. The cathode of the light-emitting diode D2 is connected to the end where the inductor L is connected to the third terminal of the switching device Q3, and the anode is connected to one end of the resistor R. The other end of the resistor R is used as the fourth connection terminal of the circuit for low-power supply access.
[0058] During the double-pulse test, there are reverse recovery losses and an excessive rate of voltage change (dV / dt), which can easily cause the device under test to short-circuit and fail. Specifically:
[0059] Reverse recovery losses: During the high-speed switching process of a power device, it will go through a process from conduction to cutoff. During this process, a large current will flow through the body diode (upper transistor) of the power device. This current rapidly drops from a high level to a low level in a very short time, which is called the reverse recovery process. The reverse recovery losses generated during this process may cause the power device to heat up. If the heat dissipation is poor, it may cause the device (upper transistor) to fail. After the upper transistor fails and shorts, this test circuit becomes a direct connection.
[0060] Excessive rate of voltage change (dV / dt): When the MOSFET is turned off, if the rate of voltage change (dV / dt) is too high, that is, the slope of the voltage rise is too steep, it will cause the charging current flowing through the parasitic capacitance Cds to flow through the base resistance, turning on the parasitic bipolar transistor, which may cause a short circuit and result in the failure of the MOSFET. dV / dt is the amount of voltage change per unit time. The steeper the slope of the rise of VDS, the more likely the dV / dt failure problem of the MOSFET will occur.
[0061] During the avalanche test, since the device needs to withstand the maximum energy, when the energy exceeds the range that the device can withstand, it will cause the device to short-circuit and fail.
[0062] In Embodiment 3 and Embodiment 4, the resistor R is a current-limiting resistor, connected in series with the light-emitting diode D2 to prevent the excessive energy of the inductor L from damaging the light-emitting diode. After the device under test Q2 fails due to a short circuit, the inductor L releases energy and forms a loop with the light-emitting diode to consume energy while the light-emitting diode (LED) lights up. Therefore, it can be determined whether the device under test is abnormally failed by observing whether the light-emitting diode D2 lights up.
[0063] During the double-pulse or avalanche test, if there is voltage oscillation or a sudden large current breaks down the device under test Q2, the energy released by the inductor forms a consumption loop with the light-emitting diode and the current-limiting resistor to prevent damage to the drive short circuit. At the same time, the light-emitting diode conducts current and emits light to determine whether the Q2 device is abnormal.
[0064] This test circuit includes all the technical features of the test circuits provided in Embodiment 1, Embodiment 2, Embodiment 3, and Embodiment 4, and is further configured to include a changeover switch SW1 connected in series with the inductor L. The changeover switch SW1 is in a normally closed state, regardless of whether this test circuit is used for a double-pulse test or an avalanche test. It is only disconnected when it is necessary to cut off the inductor L.
[0065] This test circuit includes all the technical features of the test circuits provided in Embodiment 1, Embodiment 2, Embodiment 3, and Embodiment 4, and is further configured to include a capacitor C for filtering.
[0066] The diode D1 in this test circuit is the body diode of the power device Q1. When this test circuit is not configured with the auxiliary device Q3, the first end of the power device is connected to the changeover switch SW2, the third end is connected to the inductor L as one end of the first connection end of the circuit, and the second end is shorted to the third end. When this test circuit is configured with Q3, the third end of the power device Q1 is connected to the first end of the switching device Q3, the second end is shorted to the third end, and the first end is connected to the changeover switch SW2. The GS terminal of the power device Q1 is shorted to turn off the MOSFET, and only its parasitic body diode is used to release energy for the inductor and continue the current.
[0067] Alternatively, the diode D1 in this test circuit is a conventional diode that provides freewheeling for the energy release of the inductor.
[0068] The "first terminal", "second terminal", and "third terminal" described in this article vary depending on the configured device. For example, if configured as a MOS transistor, the "first terminal", "second terminal", and "third terminal" correspond to the S pole, G pole, and D pole respectively; if configured as an IGBT, the "first terminal", "second terminal", and "third terminal" correspond to the E pole, G pole, and C pole respectively; if configured as a bipolar transistor, the "first terminal", "second terminal", and "third terminal" correspond to the E pole, B pole, and C pole respectively.
[0069] This test circuit can be used to perform double-pulse tests and avalanche tests on MOSFETs or IGBTs.
[0070] This test circuit:
[0071] 1. Simplify the test process: This test circuit integrates the circuits for double-pulse tests and avalanche tests, avoiding the traditional problem of needing to design and manufacture two different test boards, greatly simplifying the test process and reducing the complexity of the test.
[0072] 2. Improve test efficiency: By connecting switches (transfer switches SW1 and SW2) in series at the upper transistor (diode) and inductor in the double-pulse test circuit, different parameters can be tested by closing different switches, improving the test efficiency.
[0073] 3. Improve test accuracy and reliability: The current-limiting resistor and light-emitting diode can be used to detect whether the device fails during avalanche tests. If the light-emitting diode lights up, the device has a short-circuit failure, improving the test accuracy and reliability.
[0074] 4. Reduce costs: This test circuit integrates the two test circuits, avoiding the design and manufacture of two different test boards, thereby reducing costs.
[0075] 5. It can test various performances of power devices with a simple structure composed of fewer components, has good compatibility, and low costs.
[0076] The present disclosure has been described by the above related embodiments. However, the above embodiments are only examples for implementing the present disclosure. It must be noted that the disclosed embodiments do not limit the scope of the present disclosure. On the contrary, changes and modifications made without departing from the spirit and scope of the present disclosure fall within the patent protection scope of the present disclosure.
Claims
1. A test circuit compatible with avalanche test and double-pulse test, characterized in that The circuit is configured to include an inductor L, a diode D1, and a switching switch SW2. One end of the inductor L serves as the first connection end of the circuit for connecting to the power supply VCC, and the other end serves as the second connection end of the circuit for connecting to the device under test; the diode D1 is connected in series with the switching switch SW2 and then connected in parallel with the inductor L.
2. The test circuit compatible with avalanche test and double pulse test according to claim 1, characterized in that, It further includes a switching device Q3. The first end of the switching device Q3 is connected to the first connection end, the second end serves as the third connection end of the circuit for connecting to the drive signal; the third end is for connecting to the power supply VCC.
3. The test circuit compatible with avalanche test and double-pulse test according to claim 2, characterized in that The switching device Q3 and the device under test share a drive signal.
4. The test circuit compatible with avalanche test and double-pulse test according to any one of claims 1-3, characterized in that, It further includes a light-emitting diode and a current-limiting resistor R.
5. The test circuit compatible with avalanche test and double pulse test according to any one of claims 1-3, characterized in that, It further includes a switching switch SW1 connected in series with the inductor L.
6. The test circuit compatible with avalanche test and double-pulse test according to any one of claims 1-3, characterized in that, It further includes a filter capacitor C.
7. The test circuit compatible with avalanche test and double-pulse test according to any one of claims 1-3, characterized in that The diode D1 is a diode of a power device.
8. The test circuit compatible with avalanche test and double-pulse test according to claim 1, characterized in that, The device under test is a MOSFET.
9. A test system compatible with avalanche testing and double-pulse testing, characterized in that, The system includes a test circuit and a probe for obtaining parameters of the device under test, and the test circuit is the test circuit according to any one of claims 1-8.
10. The test system compatible with avalanche test and double pulse test according to claim 9, characterized in that, The probe includes a differential probe for obtaining the inter-pole voltage and a current probe for obtaining the pole current.