Power-down-free anti-false-triggering CMOS (complementary metal oxide semiconductor) clearing circuit

Abstract

The utility model relates to a circuit for eliminating a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) without power-off and false triggering prevention. Comprising a key and a delay control circuit which are used for outputting reset signals, a CMOS reset circuit used for clearing a CMOS, and a mainboard power supply control circuit used for controlling power supply of a mainboard power supply circuit, and the key and delay control circuit is respectively connected with the CMOS reset circuit and the mainboard power supply control circuit. According to the utility model, the light touch key is introduced, CMOS data can be cleared only through the key, disassembly operation is avoided, delay control is added, the problem of key false triggering is avoided, in addition, the system is powered on again according to the time sequence requirement through the mainboard power supply control circuit, the system is restarted according to the normal power-on time sequence, and the power-on efficiency is improved. The problem that after the CMOS is cleared in an electrified mode, starting cannot be achieved due to the fact that a time sequence is damaged, and power failure is needed for recovery is solved.

Description

Technical Field

[0001] The utility model relates to a circuit for clearing CMOS without power-down and anti-mis-triggering. Background Art

[0002] In the field of computers, CMOS usually refers to a component for storing basic startup information of a computer. It is a volatile storage structure, and data will be lost when power is off, and it needs to rely on an RTC battery to provide continuous power supply.

[0003] Due to some improper operations, the data stored in CMOS may be accidentally lost or damaged, resulting in abnormal operation of the computer or even inability to start. In this case, the data can be restored to the factory default state by clearing the CMOS function.

[0004] Most existing X86 hosts clear CMOS by removing the RTC battery after disassembling the machine. This method has complex operations. The operator needs to have certain knowledge and skills related to electronic circuits, and there is a risk of damaging the machine due to improper operation.

[0005] Some other hosts achieve CMOS clearing by pulling down the CMOS reset signal RTCRST#. This method also requires disassembly operation, and pulling down the RTCRST# signal when the host is powered on destroys the timing relationship between this signal and the ALWAYS power supply, which may cause the host to fail to boot normally and can only be restored after power-off. Summary of the Utility Model

[0006] The purpose of the utility model is to overcome the problems of power-down risk and key mis-triggering in the existing technology for clearing CMOS, and provide a circuit for clearing CMOS without power-down and anti-mis-triggering.

[0007] To achieve the above purpose, the technical solution of the utility model is: a circuit for clearing CMOS without power-down and anti-mis-triggering, including a key and a delay control circuit for outputting a reset signal, a CMOS reset circuit for clearing CMOS data, and a main board power control circuit for controlling the power supply of the main board power circuit; the key and the delay control circuit are respectively connected to the CMOS reset circuit and the main board power control circuit.

[0008] In an embodiment of the utility model, the key and the delay control circuit include a delay control circuit and a tactile key for controlling the conduction of the delay control circuit.

[0009] In an embodiment of the utility model, the delay control circuit includes a delay and protection circuit and a switch and isolation circuit that are connected to each other.

[0010] In an embodiment of the present utility model, the key and delay control circuit includes a tactile key BTN1, a resistor R1, a resistor R2, a capacitor C1, a TVS diode D2, an N-channel MOS transistor Q1, and a common-cathode Schottky diode D1; wherein,

[0011] One switch pin of the tactile key BTN1 is connected to the resistor R1, and the other switch pin is connected to the G pole of the N-channel MOS transistor Q1;

[0012] The end of the resistor R1 far from the tactile key BTN1 is connected to the RTC power supply +VRTC;

[0013] One end of the capacitor C1 is connected to the G pole of the N-channel MOS transistor Q1, and the other end is grounded;

[0014] One end of the resistor R2 is connected to the G pole of the N-channel MOS transistor Q1, and the other end is grounded;

[0015] One end of the TVS diode D2 is connected to the G pole of the N-channel MOS transistor Q1, and the other end is grounded;

[0016] The S pole of the N-channel MOS transistor Q1 is grounded, and the D pole of the N-channel MOS transistor Q1 is connected to the cathode of the common-cathode Schottky diode D1;

[0017] One anode of the common-cathode Schottky diode D1 is connected to the CMOS reset circuit, and the other anode is connected to the main board power control circuit;

[0018] The resistor R1, the resistor R2, the capacitor C1, and the TVS diode D2 form a delay and protection circuit, and the N-channel MOS transistor Q1 and the common-cathode Schottky diode D1 form a switch and isolation circuit. The delay and protection circuit and the switch and isolation circuit form a delay control circuit.

[0019] In an embodiment of the present utility model, the CMOS reset circuit includes a PCH bridge chip connected to the key and delay control circuit. After receiving the output signal of the key and delay control circuit, the PCH bridge chip resets the CMOS circuit inside the PCH bridge chip and clears the CMOS data.

[0020] In an embodiment of the present utility model, the CMOS reset circuit includes a resistor R4, a capacitor C2, and a PCH CMOS circuit; wherein,

[0021] One end of the resistor R4 is connected to the key and delay control circuit, and the other end is connected to the RTC power supply +VRTC;

[0022] One end of the capacitor C2 is connected to the key and delay control circuit, and the other end is grounded;

[0023] The PCH CMOS circuit is connected to the key and the delay control circuit.

[0024] In an embodiment of the present invention, the main board power control circuit includes a resistor R3, a resistor R5, a resistor R6, a capacitor C3, a Schottky diode D3, and a main board power circuit; wherein,

[0025] One end of the resistor R3 is connected to the connection between the key and the delay control circuit, and the other end is connected to the main board input power supply +VDC;

[0026] One end of the resistor R5 is connected to the connection between the key and the delay control circuit, and the other end is connected to the capacitor C3;

[0027] The connection point of the capacitor C3 and the resistor R5 is denoted as the first node, and the other end of the capacitor C3 is grounded;

[0028] The cathode of the Schottky diode D3 is connected to the connection between the key and the delay control circuit, and the anode is connected to the first node;

[0029] One end of the resistor R6 is connected to the first node, and the other end is grounded;

[0030] The first node is connected to the main board power circuit.

[0031] Compared with the prior art, the present invention has at least the following beneficial effects:

[0032] 1. Since a touch key is introduced, the CMOS data can be cleared only by pressing the key, avoiding the disassembly operation.

[0033] 2. Since the delay control is added, the problem of accidental key triggering is avoided.

[0034] 3. Through the main board power control circuit, the system is powered on again according to the timing requirements, so that the system restarts according to the normal power-on timing, solving the problem that the system cannot start due to the destruction of the timing after clearing the CMOS with power on and needs to be powered off to recover. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic circuit diagram of the key and delay control circuit provided in the embodiment of the present invention.

[0036] Figure 2 is a schematic circuit diagram of the CMOS reset circuit provided in the embodiment of the present invention.

[0037] Figure 3 is a schematic circuit diagram of a main board power control circuit provided in the embodiment of the present invention.

[0038] Figure 4It is a system block diagram for clearing CMOS provided in the embodiments of the present utility model.

[0039] Reference numerals: 1 - momentary switch, 2 - delay and protection circuit, 3 - switch and isolation circuit. Detailed implementation manners

[0040] As Figure 4 shown, the present utility model provides a circuit for clearing CMOS that prevents power-down and accidental triggering, including a key and a delay control circuit for outputting a reset signal, a CMOS reset circuit for clearing CMOS data, and a main board power control circuit for controlling the power supply of the main board power circuit; the key and the delay control circuit are respectively connected to the CMOS reset circuit and the main board power control circuit.

[0041] The key and the delay control circuit output a reset signal to the CMOS reset circuit and the main board power control circuit.

[0042] After receiving the reset signal output by the key and the delay control circuit, the CMOS reset circuit sends it to the PCH bridge chip to reset the CMOS circuit inside the bridge chip and clear the CMOS.

[0043] After receiving the reset signal output by the key and the delay control circuit, the main board power control circuit outputs it to the main board power circuit after processing such as delay and voltage division, and controls all power supplies to power on in the normal time sequence.

[0044] The following further describes the present utility model in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0045] The working principle of the circuit in the embodiments of the present utility model is as follows:

[0046] Referring to Figure 1 , by default, the momentary switch BTN1 is in the off state. Due to the weak pull-down effect of the pull-down resistor R2, the G pole of the N-channel MOS transistor Q1 is at a low level, and Q1 is not conducting. At this time, the signals RTCRST# and UVP# are both at a high level due to the pull-up, and the system is in a normal working state.

[0047] When the momentary switch BTN1 is pressed, the 1st and 2nd pins of BTN1 are conducting, and the RTC battery voltage +VRTC charges the capacitor C1 through the resistor R1, and the G pole voltage of Q1 increases slowly. R1 and C1 form an RC delay. The resistance value of R1, the capacitance value of C1, and the turn-on voltage threshold of Q1 determine the delay time, which specifically satisfies the following formula:

[0048] T1 = R1 * C1 * ln[+VRTC / (+VRTC - Vth)]

[0049] Wherein, T1 is the delay time, R1 is the resistance value, C1 is the capacitance value, +VRTC is the RTC battery voltage value, and Vth is the turn-on voltage threshold of the N-channel MOS transistor Q1.

[0050] The value of R1 cannot be too small, otherwise it will increase the current consumption of the RTC battery and affect the battery life. Generally, the value of R1 is 1MΩ and the value of C1 is 2.2uF, so a delay of about 2s can be obtained, which is suitable for practical applications.

[0051] When the G-pole voltage of Q1 increases to be greater than the turn-on voltage of the N-channel MOS transistor, the drain and source of Q1 are gradually turned on, and the drain is pulled low. This low level is output to the signals RTCRST# and UVP# respectively through the common-cathode diode D1.

[0052] The function of the common-cathode diode D1 is to utilize its one-way conduction characteristic to isolate the RTCRST# and UVP# signals and avoid mutual interference between the two.

[0053] Refer to Figure 2 , the input low level of RTCRST# is given to the CMOS reset input pin of the platform PCH chip to achieve CMOS reset and data clearing.

[0054] On the one hand, the resistor R4 provides a pull-up for the signal RTCRST# to maintain the high level in the default state; on the other hand, it also forms an RC delay together with the capacitor C2 to ensure that the rising edge slope of the signal RTCRST# meets the timing requirements, specifically satisfying the following formula:

[0055] T2 = R4 * C2 * ln[+VRTC / (+VRTC - Vih)]

[0056] Wherein, T2 is the rising delay time of RTCRST#, R4 is the resistance value, C2 is the capacitance value, +VRTC is the RTC battery voltage value, and Vih is the minimum high level value of the signal RTCRST#. Generally, it is required that T2 is greater than 10ms.

[0057] Refer to Figure 3 , in the default state, one end PWR_EN of the capacitor C3 connected to the resistor R5 is at a high level, and the main board power supply outputs normally. The high level value of PWR_EN depends on the main board input voltage +VDC and the resistors R3, R5, and R6. Specifically, it satisfies the following formula:

[0058] V1 = +VDC * (R6 / (R3 + R5 + R6))

[0059] Where V1 is the steady - state high - level voltage of PWR_EN, +VDC is the main - board input voltage, and R3, R5, and R6 are resistance values.

[0060] When the touch button BTN1 is pressed, the input low - level UVP# causes the high - level voltage on the capacitor C3 to quickly discharge through the Schottky diode D3. PWR_EN changes from high level to low level, the ALWAYS power supply of the main board stops output, and other power supplies associated with the ALWAYS power supply also stop output, and the system powers down.

[0061] Immediately afterwards, when the touch button is released, the button BTN1 disconnects, and the resistor R1 and the capacitor C1 are disconnected. The voltage on C1 discharges to the ground through the resistor R2, and the voltage gradually decreases. The discharge time satisfies the following formula:

[0062] T3 = R2 * C1 * ln(V2 / Vt)

[0063] Where T3 is the discharge time, R2 is the resistance value, C1 is the capacitance value, V2 is the initial voltage on the capacitor C1, and Vt is the voltage on C1 after discharging for T3 time.

[0064] The value of R2 cannot be too low compared with R1, otherwise the G - pole voltage of Q1 cannot reach the turn - on voltage due to the voltage division of R2; on the other hand, the value of R2 cannot be too large, otherwise the discharge time will be too long, which is not conducive to restoring to the stable state. Generally, R2 is about 5 times that of R1. If R1 is 1MΩ, then R2 taking 4.7MΩ is appropriate. In addition, D2 is a TVS tube, which plays a role in anti - electrostatic interference.

[0065] When the G - pole voltage of Q1 drops below the turn - on voltage of the N - channel MOS tube Q1, Q1 changes from the conducting state to the cut - off state. +VRTC charges the capacitor C2 through the resistor R4, and RTCRST# gradually becomes high level, and the CMOS reset is completed. The values of the resistor R4 and the capacitor C2 determine the time for RTCRST# to change from low level to effective high level (generally required to be greater than 10ms). The resistor R4 generally takes 30.1kΩ, and the capacitor C2 taking 1uF can meet the requirements.

[0066] On the other hand, the main - board power supply +VDC charges the capacitor C3 through the resistors R3 and R5, and PWR_EN gradually becomes high level. After a delay time, the system powers on again. During this process, the values of the resistors R3, R5, and the capacitor C3, as well as the high - level effective voltage of PWR_EN, determine the system power - on delay time, which specifically satisfies the following formula:

[0067] T4=(R3 + R5)*C3*ln[V1 / (V1 - Vhen)]

[0068] Where T4 is the delay time of PWR_EN from low level to effective high level, R3 and R5 are resistance values, C3 is a capacitance value, V1 is the steady-state high-level voltage of PWR_EN, and Vhen is the effective high-level voltage of PWR_EN.

[0069] According to the timing requirements of the X86 platform, the delay time T4 must be more than 10 ms longer than T2 to ensure normal power-on of the mainboard. Otherwise, there will be a situation where it cannot start after clearing the CMOS while powered on, and it needs to be powered off again to recover. However, this time cannot be too long, otherwise it will cause too long startup time and affect the user experience. It is advisable to control it at about 1 s normally.

[0070] In summary, the resistance and capacitance parameters can be selected as shown in Table 1 below (assuming +VDC = 19V):

[0071] Table 1

[0072] R1 R2 R3 R4 R5 R6 C1 C2 C3 1 MΩ 4.7 MΩ 10 kΩ 30.1 kΩ 1 MΩ 200 kΩ 2.2 μF 1 μF 1 μF

[0073] In actual application, the resistance and capacitance parameters can be adjusted according to the actual situation.

[0074] Expansion of the technical solution of the present utility model.

[0075] The present utility model can be used in personal office computers, cloud desktop terminals, servers, etc. that have a CMOS clearing function button and require normal CMOS clearing even when powered on and at the same time need to have an anti-misoperation function. Those skilled in the art of this technology should understand that the specific embodiments we described are illustrative and not used to limit the scope of the technical solution. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of this technical solution should be covered within the scope protected by the claims of the present utility model.

[0076] The above are the preferred embodiments of the present utility model. All changes made in accordance with the technical solution of the present utility model and whose functional effects do not exceed the scope of the technical solution of the present utility model belong to the protection scope of the present utility model.

Claims

1. A circuit for clearing CMOS that prevents mis-triggering without powering down, characterized in that, It includes a button and a delay control circuit for outputting a reset signal, a CMOS reset circuit for clearing CMOS data, and a main board power control circuit for controlling the power supply of the main board power circuit; the button and the delay control circuit are respectively connected to the CMOS reset circuit and the main board power control circuit.

2. The CMOS clearing circuit that prevents mis-triggering without power-down according to claim 1, wherein The button and the delay control circuit include a delay control circuit and a tactile button for controlling the conduction of the delay control circuit.

3. The circuit for clearing CMOS that prevents mis-triggering without power-down according to claim 2, wherein The delay control circuit includes a delay and protection circuit and a switch and isolation circuit connected to each other.

4. A circuit for clearing CMOS that prevents mis-triggering without powering down according to any one of claims 1-3, characterized in that, The button and the delay control circuit include a tactile button BTN1, a resistor R1, a resistor R2, a capacitor C1, a TVS diode D2, an N-channel MOS transistor Q1, and a common-cathode Schottky diode D1; among them, One switch pin of the tactile button BTN1 is connected to the resistor R1, and the other switch pin is connected to the G pole of the N-channel MOS transistor Q1; One end of the resistor R1 away from the tactile button BTN1 is connected to the RTC power supply +VRTC; One end of the capacitor C1 is connected to the G pole of the N-channel MOS transistor Q1, and the other end is grounded; One end of the resistor R2 is connected to the G pole of the N-channel MOS transistor Q1, and the other end is grounded; One end of the TVS diode D2 is connected to the G pole of the N-channel MOS transistor Q1, and the other end is grounded; The S pole of the N-channel MOS transistor Q1 is grounded, and the D pole of the N-channel MOS transistor Q1 is connected to the cathode of the common-cathode Schottky diode D1; One anode of the common-cathode Schottky diode D1 is connected to the CMOS reset circuit, and the other anode is connected to the main board power control circuit; The resistor R1, the resistor R2, the capacitor C1, and the TVS diode D2 form a delay and protection circuit, the N-channel MOS transistor Q1 and the common-cathode Schottky diode D1 form a switch and isolation circuit, and the delay and protection circuit and the switch and isolation circuit form a delay control circuit.

5. The circuit for clearing CMOS that prevents mis-triggering without powering down according to claim 1, characterized in that, The CMOS reset circuit includes a PCH bridge chip connected to the button and the delay control circuit. After receiving the output signal of the button and the delay control circuit, the PCH bridge chip resets the CMOS circuit inside the PCH bridge chip to clear the CMOS data.

6. The circuit for clearing CMOS that prevents power-down and accidental triggering according to claim 1 or 5, characterized in that, The CMOS reset circuit includes a resistor R4, a capacitor C2, and a PCH CMOS circuit; among them, One end of the resistor R4 is connected to the button and the delay control circuit, and the other end is connected to the RTC power supply +VRTC; One end of the capacitor C2 is connected to the button and the delay control circuit, and the other end is grounded; The PCH CMOS circuit is connected to the button and the delay control circuit.

7. The circuit for clearing CMOS that prevents mis-triggering without power-down according to claim 1, characterized in that, The main board power control circuit includes a resistor R3, a resistor R5, a resistor R6, a capacitor C3, a Schottky diode D3, and a main board power circuit; among them, One end of the resistor R3 is connected to the button and the delay control circuit, and the other end is connected to the main board input power supply +VDC; One end of the resistor R5 is connected to the button and the delay control circuit, and the other end is connected to the capacitor C3; The connection point of the capacitor C3 and the resistor R5 is denoted as the first node, and the other end of the capacitor C3 is grounded; The cathode of the Schottky diode D3 is connected to the connection between the button and the delay control circuit, and the anode is connected to the first node; One end of the resistor R6 is connected to the first node, and the other end is grounded; The first node is connected to the main board power supply circuit.

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