ACDC switching power supply circuit

Abstract

According to the ACDC switching power supply circuit, the control module is usually a control chip, the control chip of the ACDC switching power supply circuit supplies power through a built-in JFET, the higher the bus voltage is, the higher the power on the JFET is, and therefore, under the condition that the bus voltage is higher (the bus voltage is higher than VMUV), the power supply at the wave crest of the bus is reduced, heating can be reduced, and the service life of the circuit is prolonged. And the phenomenon that the chip does not work due to a temperature protection mechanism triggered by heating of the JFET is avoided.

Description

Technical Field

[0001] This application relates to the field of AC-DC technology, and more particularly, to an AC-DC switching power supply circuit. Background Art

[0002] In AC-DC applications, after the mains power passes through a rectifier bridge, a DC signal VM (bus voltage) is output. The power supply method of the switching power supply chip generally includes directly supplying power from the bus through a current-limiting resistor, or supplying power from the output, or supplying power from the bus through a JFET. In the scheme of directly supplying power from the bus through a current-limiting resistor, the current-limiting resistor will consume a certain amount of power, resulting in energy waste and reduced system efficiency. In addition, as the load changes, the bus voltage may fluctuate, affecting the power supply stability of the chip. In the scheme of supplying power from the output, it is required that the output voltage must be higher than the voltage required by the chip, and in some cases, such as during the startup phase or load mutation, stable power supply may not be guaranteed. In the scheme of supplying power from the bus through a JFET, as a voltage-controlled device, the JFET can precisely control the current passing through the chip, which helps to protect the chip from excessive current impact. At the same time, the JFET is built into the chip, reducing the use of external components and simplifying the circuit design. However, the built-in JFET is prone to heat generation under large loads or high-temperature environments, resulting in an increase in the internal temperature of the chip, which may trigger the temperature protection mechanism and cause the chip to malfunction. In addition, the heat generation of the JFET may also affect the performance and lifespan of other components inside the chip. Summary of the Utility Model

[0003] The purpose of the embodiments of this application is to provide an AC-DC switching power supply circuit to solve the problem that the internal temperature of the switching power supply chip increases when using a built-in JFET for power supply, which may trigger the temperature protection mechanism and cause the chip to malfunction.

[0004] An AC-DC switching power supply circuit provided by the embodiments of this application includes a power supply capacitor, a control module, and a MOS transistor. The control module is used to control the on and off of the MOS transistor.

[0005] The power supply terminal of the control module is connected to the bus voltage. The control module is configured to: when in a steady-state working state and the bus voltage is higher than VM_UV, first stop supplying power to the JFET and supply power from the power supply capacitor until the voltage of the power supply capacitor drops from VDD_OK to VDD_FORCE, and then supply pulsed power to the JFET, and use the pulsed current output by the JFET to intermittently charge the power supply capacitor to stabilize the voltage of the power supply capacitor at VDD_FORCE.

[0006] In the above technical solution, the control module is usually a control chip. The control chip of the ACDC switching power supply circuit is powered by an internal JFET. The higher the bus voltage, the greater the power on the JFET. Therefore, in this embodiment, when the bus voltage is relatively high (the bus voltage is higher than VM_UV), reducing the power supply at the bus peak can reduce heat generation and avoid the chip from not working due to the temperature protection mechanism being triggered by the JFET heating up.

[0007] In some alternative embodiments, the control module is further configured to: when in the steady-state operating state and the bus voltage is lower than VM_UV, first fully power the JFET, use the maximum charging current output by the JFET to charge the power supply capacitor until the voltage of the power supply capacitor reaches VDD_OK, and then pulse-power the JFET, use the pulsed current output by the JFET to intermittently charge the power supply capacitor, so that the voltage of the power supply capacitor is stabilized at VDD_OK; where VDD_OK is greater than VDD_FORCE.

[0008] In the above technical solution, when the bus voltage is relatively low (the bus voltage is lower than VM_UV), first use the maximum charging current output by the JFET to quickly charge the power supply capacitor to make the voltage of the power supply capacitor reach the maximum value VDD_OK as soon as possible. Here, since the bus voltage is low, even if the JFET is fully powered, it will not cause serious heating. Then, the JFET outputs a pulsed current to intermittently charge the power supply capacitor to stabilize the voltage of the power supply capacitor at VDD_OK.

[0009] In some alternative embodiments, the control module is further configured to: during the startup process, use the JFET to output a first current to charge the power supply capacitor until the voltage of the power supply capacitor reaches VDD_OK, end the startup process, and enter the steady-state operating state; where the first current is less than the maximum charging current.

[0010] In the above technical solution, during the startup process, regardless of how the bus voltage changes, first use the JFET to output a relatively low first current to slowly charge the power supply capacitor. Since the value of the first current is low, it will not cause serious heating until the voltage of the power supply capacitor reaches VDD_OK, end the startup process, and enter the steady-state operating state;

[0011] Wherein, if the bus voltage is greater than VM_UV when entering the steady-state operating state, first control the JFET not to output current, and the power supply capacitor supplies power, so that the voltage of the power supply capacitor drops from VDD_OK to VDD_FORCE, and then control the JFET to pulse-power, and the JFET outputs a pulsed current to intermittently charge the power supply capacitor to stabilize the voltage of the power supply capacitor at VDD_FORCE;

[0012] If the bus voltage is less than VM_UV when entering the steady-state operating condition, the JFET outputs a pulsed current to intermittently charge the power supply capacitor, so that the voltage of the power supply capacitor is stabilized at VDD_OK.

[0013] In some alternative embodiments, the control module includes a JFET, a power supply control logic module, a VDD monitoring module, an LDO module, and a bus monitoring module;

[0014] The drain of the JFET is connected to the bus voltage, the source of the JFET is connected to the first end of the power supply control logic module, the gate of the JFET is grounded, the second end of the power supply control logic module is connected to the input end of the LDO module, and the output end of the LDO module supplies power to the internal modules of the chip; the second end of the power supply control logic module is also connected to the VDD monitoring module, and the second end of the power supply control logic module is also connected to the power supply capacitor.

[0015] In some alternative embodiments, in the steady-state operating condition, when the bus monitoring module monitors that the bus voltage is greater than VM_UV, the bus monitoring module sends a first signal to the power supply control logic module; the VDD monitoring module is used to send a fourth signal to the power supply control logic module when monitoring that the voltage of the power supply capacitor drops to VDD_FORCE;

[0016] The power supply control logic module is used to control the JFET to stop power supply and be powered by the power supply capacitor according to the received first signal in the steady-state operating condition until receiving the fourth signal sent by the VDD monitoring module, and then control the JFET to output a pulsed current to intermittently charge the power supply capacitor, so that the voltage of the power supply capacitor is stabilized at VDD_FORCE.

[0017] In some alternative embodiments, in the steady-state operating condition, when the bus monitoring module monitors that the bus voltage is less than VM_UV, the bus monitoring module sends a second signal to the power supply control logic module; the VDD monitoring module is used to send a third signal to the power supply control logic module when monitoring that the voltage of the power supply capacitor reaches VDD_OK;

[0018] The power supply control logic module is used to first control the JFET to output the maximum charging current to charge the power supply capacitor according to the received second signal in the steady-state operating condition until receiving the third signal sent by the VDD monitoring module, and then control the JFET to output a pulsed current to intermittently charge the power supply capacitor, so that the voltage of the power supply capacitor is stabilized at VDD_OK.

[0019] In some alternative embodiments, during the startup process, the VDD monitoring module is used to send a third signal to the power supply control logic module when monitoring that the voltage of the power supply capacitor reaches VDD_OK;

[0020] The power supply control logic module is used to control the JFET to output a first current to charge the power supply capacitor during the startup process until it receives the third signal sent by the VDD monitoring module, ending the startup process and entering the steady-state working state.

[0021] A control method for power supply control of a control module in an ACDC switching power supply circuit provided by an embodiment of the present application. The power supply terminal of the control module is connected to the bus voltage; the VDD terminal of the control module is connected to the first end of the power supply capacitor, and the power supply capacitor voltage supplies power to the internal modules of the chip after passing through the LDO module;

[0022] The method is applied to the control module, and the method includes: in the steady-state working state and when the bus voltage is higher than VM_UV, first stop supplying power to the JFET, and supply power by the power supply capacitor until the power supply capacitor voltage drops from VDD_OK to VDD_FORCE, and then pulse supply power to the JFET, and use the pulsed current to intermittently charge the power supply capacitor to make the power supply capacitor voltage stable at VDD_FORCE.

[0023] In some optional embodiments, it further includes:

[0024] In the steady-state working state and when the bus voltage is lower than VM_UV, first supply full power to the JFET, and use the maximum charging current to charge the power supply capacitor until the power supply capacitor voltage reaches VDD_OK, and then pulse supply power to the JFET, and use the pulsed current output by the JFET to intermittently charge the power supply capacitor to make the power supply capacitor voltage stable at VDD_OK.

[0025] In some optional embodiments, before the steady-state working state, it further includes:

[0026] During the startup process, use the JFET to output a first current to charge the power supply capacitor until the power supply capacitor voltage reaches VDD_OK, ending the startup process and entering the steady-state working state; wherein, the first current is less than the maximum charging current. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, so they should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0028] Figure 1 A structural diagram of an ACDC switching power supply circuit provided by the first embodiment of the present application;

[0029] Figure 2 A structural schematic diagram of the control module provided by the embodiment of the present application;

[0030] Figure 3 A circuit structure diagram of an AC-DC switching power supply provided for the second embodiment of the present application;

[0031] Figure 4 A circuit structure diagram of an AC-DC switching power supply provided for the third embodiment of the present application;

[0032] Figure 5 A waveform diagram of the supply capacitor voltage and charging current provided for the embodiment of the present application. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0034] Please refer to Figure 1 , Figure 1 A circuit structure diagram of an AC-DC switching power supply provided for the first embodiment of the present application, including a supply capacitor C3, a control module, and a MOS transistor M1. The control module is used to control the on and off of the MOS transistor M1. Among them, the power supply terminal of the control module is connected to the bus voltage. The control module is used for: when in a steady-state working state and the bus voltage is higher than VM_UV, first stop supplying power to the JFET, and supply power by the supply capacitor C3 until the supply capacitor voltage drops from VDD_OK to VDD_FORCE, then supply pulsed power to the JFET, and use the pulsed current output by the JFET to intermittently charge the supply capacitor C3 to make the voltage of the supply capacitor C3 stable at VDD_FORCE.

[0035] In the embodiment of the present application, the control module is usually a control chip. The control chip of the AC-DC switching power supply is powered by an internal JFET. The higher the bus voltage, the greater the power on the JFET. Therefore, in this embodiment, when the bus voltage is relatively high (the bus voltage is higher than VM_UV), reducing the power supply at the bus voltage peak can reduce heat generation and avoid chip non-operation caused by the temperature protection mechanism being triggered due to JFET heat generation.

[0036] In some optional implementation manners, the control module is further used for: when in a steady-state working state and the bus voltage is lower than VM_UV, first supply full power to the JFET, use the maximum charging current output by the JFET to charge the supply capacitor C3 until the voltage of the supply capacitor C3 reaches VDD_OK, then supply pulsed power to the JFET, and use the pulsed current output by the JFET to intermittently charge the supply capacitor C3 to make the voltage of the supply capacitor C3 stable at VDD_OK; where VDD_OK is greater than VDD_FORCE.

[0037] In the embodiment of the present application, when the bus voltage is low (the bus voltage is lower than VM_UV), first use the JFET to output the maximum charging current to quickly charge the power supply capacitor C3, so that the voltage of the power supply capacitor C3 reaches the maximum value VDD_OK as soon as possible. Here, since the bus voltage is low, even if the JFET supplies power fully, it will not cause serious heating. After that, the JFET outputs a pulsed current to intermittently charge the power supply capacitor C3, so that the voltage of the power supply capacitor C3 is stabilized at VDD_OK.

[0038] In some alternative embodiments, the control module is further configured to: during the startup process, use the JFET to output a first current to charge the power supply capacitor C3 until the voltage of the power supply capacitor C3 reaches VDD_OK, end the startup process, and enter the steady-state working state; wherein, the first current is less than the maximum charging current.

[0039] In the embodiment of the present application, during the startup process, regardless of how the bus voltage changes, first use the JFET to output a lower first current to slowly charge the power supply capacitor C3. Since the value of the first current is low, it will not cause serious heating until the voltage of the power supply capacitor C3 reaches VDD_OK, end the startup process, and enter the steady-state working state;

[0040] Wherein, if the bus voltage is greater than VM_UV when entering the steady-state working state, first control the JFET not to output current, and the power supply capacitor C3 supplies power, so that the voltage of the power supply capacitor C3 drops from VDD_OK to VDD_FORCE, and then control the JFET to supply power in pulses. The JFET outputs a pulsed current to intermittently charge the power supply capacitor C3, so that the voltage of the power supply capacitor C3 is stabilized at VDD_FORCE;

[0041] If the bus voltage is less than VM_UV when entering the steady-state working state, use the JFET to output a pulsed current to intermittently charge the power supply capacitor C3, so that the voltage of the power supply capacitor C3 is stabilized at VDD_OK.

[0042] Specifically, please refer to Figure 2 , Figure 2 which is the structural schematic diagram of the control module provided by the embodiment of the present application. The control module specifically includes a JFET, a power supply control logic module, a VDD monitoring module, an LDO module, and a bus monitoring module.

[0043] The drain of the JFET is connected to the bus voltage, the source of the JFET is connected to the first end of the power supply control logic module, the gate of the JFET is grounded, the second end of the power supply control logic module is connected to the input end of the LDO module, and the output end of the LDO module supplies power to the internal modules of the chip; the second end of the power supply control logic module is also connected to the VDD monitoring module, and the second end of the power supply control logic module is also connected to the power supply capacitor C3.

[0044] In some alternative embodiments, in the steady-state operating condition, when the bus voltage monitoring module monitors that the bus voltage is greater than VM_UV, the bus voltage monitoring module sends a first signal to the power supply control logic module; when the VDD monitoring module monitors that the voltage of the power supply capacitor drops to VDD_FORCE, it sends a fourth signal to the power supply control logic module.

[0045] The power supply control logic module is configured to, in the steady-state operating condition, according to the received first signal, control the JFET to stop power supply and be powered by the power supply capacitor until it receives the fourth signal sent by the VDD monitoring module, and then control the JFET to output a pulsed current to intermittently charge the power supply capacitor C3 so that the voltage of the power supply capacitor C3 is stabilized at VDD_FORCE.

[0046] In some alternative embodiments, in the steady-state operating condition, when the bus voltage monitoring module monitors that the bus voltage is less than VM_UV, the bus voltage monitoring module sends a second signal to the power supply control logic module; when the VDD monitoring module monitors that the voltage of the power supply capacitor C3 reaches VDD_OK, it sends a third signal to the power supply control logic module.

[0047] The power supply control logic module is configured to, in the steady-state operating condition, according to the received second signal, first control the JFET to output a maximum charging current to charge the power supply capacitor C3 until it receives the third signal sent by the VDD monitoring module, and then control the JFET to output a pulsed current to intermittently charge the power supply capacitor C3 so that the voltage of the power supply capacitor C3 is stabilized at VDD_OK.

[0048] In some alternative embodiments, during the startup process, when the VDD monitoring module monitors that the voltage of the power supply capacitor C3 reaches VDD_OK, it sends a third signal to the power supply control logic module.

[0049] The power supply control logic module is configured to, during the startup process, control the JFET to output a first current to charge the power supply capacitor C3 until it receives the third signal sent by the VDD monitoring module, at which point the startup process ends and it enters the steady-state operating condition.

[0050] The circuit of this embodiment is an ACDC switching power supply with a flyback architecture. The ACDC switching power supply with a flyback architecture further includes a rectifier bridge and a transformer. Among them, the AC voltage is rectified and output by the rectifier bridge. The positive output terminal of the rectifier bridge is connected to the first terminal of capacitor C1. The second terminal of capacitor C1 is grounded. The first terminal of capacitor C1 is connected to the HV terminal (power supply terminal) of the control module. The first terminal of capacitor C1 is also connected to the second terminal of the primary winding LP of the transformer. The first terminal of the primary winding LP of the transformer is connected to the first terminal of diode D1. The second terminal of diode D1 is connected to the first terminal of capacitor C1 after passing through resistor R5. The second terminal of diode D1 is also connected to the first terminal of capacitor C1 after passing through capacitor C2. The first terminal of the primary winding LP of the transformer is also connected to the ZCD terminal of the control module. The first terminal of the primary winding LP of the transformer is also connected to the drain of MOS transistor M1. The source of MOS transistor M1 is grounded after passing through resistor R4. The gate of MOS transistor M1 is connected to the DRV terminal of the control module. The source of MOS transistor M1 is connected to the CS terminal of the control module. The first terminal of the secondary winding of the transformer is connected to the first terminal of diode D2. The second terminal of diode D2 is connected to capacitor C4 and then grounded. The second terminal of diode D2 is also connected to resistor R6 and then grounded.

[0051] It should be clear that the control module of this embodiment can be applied to other types of ACDC switching power supplies, such as the ACDC switching power supply with a BUCK architecture and the ACDC switching power supply with a Boost architecture provided in the following embodiments:

[0052] Please refer to Figure 3 , Figure 3 which is a circuit structure diagram of an ACDC switching power supply provided in the second embodiment of this application.

[0053] The circuit of this embodiment is an ACDC switching power supply with a BUCK architecture. The ACDC switching power supply with a BUCK architecture further includes a rectifier bridge and an inductor L1. Among them, the AC voltage is rectified and output by the rectifier bridge. The positive output terminal of the rectifier bridge is connected to the first terminal of capacitor C1. The second terminal of capacitor C1 is grounded. The first terminal of capacitor C1 is connected to the HV terminal (power supply terminal) of the control module. The first terminal of capacitor C1 is also connected to the drain of MOS transistor M1. The source of MOS transistor M1 is connected to the first terminal of resistor R5. The DRV terminal of the control module is connected to the gate of MOS transistor M1. The second terminal of resistor R5 is connected to the first terminal of inductor L1. The second terminal of inductor L1 is connected to capacitor C2 and then grounded. The second terminal of inductor L1 is also connected to resistor R6 and then grounded. The first terminal of resistor R5 is also connected to the CS terminal of the control module. The CS terminal of the control module is connected to the second terminal of diode D1. The first terminal of diode D1 is grounded. The VDD terminal of the control module is connected to the power supply capacitor C3. The TADJ terminal of the control module is connected to the first terminal of inductor L1 after passing through R7.

[0054] Please refer toFigure 4 , Figure 4 This is a structural diagram of an ACDC switching power supply circuit provided by the third embodiment of the present application.

[0055] The circuit of this embodiment is an ACDC switching power supply with a Boost architecture. The ACDC switching power supply with a Boost architecture further includes a rectifier bridge and an inductor L1. Among them, the AC voltage is rectified and output by the rectifier bridge. The positive output terminal of the rectifier bridge is connected to the first terminal of a capacitor C1. The second terminal of the capacitor C1 is grounded. The first terminal of the capacitor C1 is connected to the HV terminal (power supply terminal) of the control module. The first terminal of the capacitor C1 is also connected to the second terminal of the inductor L1. The first terminal of the inductor L1 is connected to the drain of a MOS transistor M1. The gate of the MOS transistor M1 is connected to the DRV terminal of the control module. The source of the MOS transistor M1 is grounded after passing through a resistor R4. The first terminal of the inductor L1 is also connected to the first terminal of a diode D1. The second terminal of the diode D1 is connected to a capacitor C2 and then grounded. The second terminal of the diode D1 is connected to the first terminal of a resistor R2. The second terminal of the resistor R2 is connected to the first terminal of a resistor R3. The second terminal of the resistor R3 is grounded; the second terminal of the resistor R2 is connected to the FB terminal of the control module. The CS terminal of the control module is connected to the source of the MOS transistor M1. The VDD terminal of the control module is grounded after passing through a power supply capacitor C3. The COMP terminal of the control module is grounded after passing through a capacitor C6. The COMP of the control module is grounded through a resistor R1 and a capacitor C5.

[0056] A method for controlling the power supply of the control module of an ACDC switching power supply circuit provided by an embodiment of the present application. The power supply terminal of the control module is connected to the bus voltage; the VDD terminal of the control module is connected to the first terminal of a power supply capacitor C3. The voltage of the power supply capacitor C3 supplies power to the internal modules of the chip after passing through an LDO module;

[0057] The method is applied to the control module. The method includes: in the steady-state operating state and when the bus voltage is higher than VM_UV, first stop supplying power to the JFET, and supply power by the power supply capacitor C3 until the voltage of the power supply capacitor drops from VDD_OK to VDD_FORCE, and then supply pulsed power to the JFET, and intermittently charge the power supply capacitor C3 with the pulsed current to make the voltage of the power supply capacitor C3 stable at VDD_FORCE.

[0058] In some optional embodiments, it further includes:

[0059] In the steady-state operating state and when the bus voltage is lower than VM_UV, first supply full power to the JFET, and charge the power supply capacitor C3 with the maximum charging current until the voltage of the power supply capacitor C3 reaches VDD_OK, and then supply pulsed power to the JFET, and intermittently charge the power supply capacitor C3 with the pulsed current output by the JFET to make the voltage of the power supply capacitor C3 stable at VDD_OK.

[0060] In some alternative embodiments, before the steady-state operating condition, it further includes:

[0061] During the startup process, a first current is output by the JFET to charge the power supply capacitor C3 until the voltage of the power supply capacitor C3 reaches VDD_OK, and the startup process ends and enters the steady-state operating condition; wherein, the first current is less than the maximum charging current.

[0062] For the specific process, please refer to Figure 5 , Figure 5 which is the waveform diagram of the bus voltage VM, the voltage VDD of the power supply capacitor C3, and the charging current IHV provided by the embodiments of the present application. The time period from T0 to T1 is the startup process. During the startup process, a relatively low first current is output by the JFET to slowly charge the power supply capacitor C3 until at time T1, the voltage VDD of the power supply capacitor C3 reaches the maximum value VDD_OK, and the startup process ends and enters the steady-state operating condition. At time T1, when the bus voltage VM is greater than VM_UV, first control the JFET not to output current, and the power supply capacitor C3 supplies power, causing the voltage VDD of the power supply capacitor C3 to start to decrease from VDD_OK until at time T2, the voltage VDD of the power supply capacitor C3 drops to VDD_FORCE. At this time, control the JFET to output a pulsed current to intermittently charge the power supply capacitor C3, so that the voltage VDD of the power supply capacitor C3 is stabilized at VDD_FORCE. After time T3, the bus voltage VM starts to be less than VM_UV. At this time, control the JFET to output the maximum current value I2 to charge the power supply capacitor C3, and the voltage VDD of the power supply capacitor C3 starts to rise from VDD_FORCE. At time T4, the voltage VDD of the power supply capacitor C3 rises to the maximum value VDD_OK, and control the JFET to output a pulsed current to intermittently charge the power supply capacitor C3, so that the voltage VDD of the power supply capacitor C3 is stabilized at VDD_OK. After time T5, the bus voltage VM starts to be greater than VM_UV. At this time, control the JFET not to output current, and the voltage VDD of the power supply capacitor C3 starts to decrease from VDD_FORCE. At time T6, the voltage VDD of the power supply capacitor C3 drops to VDD_FORCE. At this time, control the JFET to output a pulsed current to intermittently charge the power supply capacitor C3, so that the voltage VDD of the power supply capacitor C3 is stabilized at VDD_FORCE until time T7. The waveforms of the subsequent supply voltage VDD and the charging current IHV in the steady-state operating condition are to continuously repeat the waveforms of T3 - T7.

[0063] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some communication interfaces. The indirect coupling or communication connection of the devices or units can be in electrical, mechanical or other forms.

[0064] In addition, the units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0065] Furthermore, in each embodiment of the present application, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0066] In this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0067] The above are only the embodiments of the present application and are not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An AC-DC switching power supply circuit, characterized in that, It includes a power supply capacitor, a control module and a MOS transistor, and the control module is used to control the on / off of the MOS transistor; The power supply terminal of the control module is connected to the bus voltage, and the control module is configured to: when in the steady-state working state and the bus voltage is higher than VM_UV, first stop power supply to the JFET, supply power by the power supply capacitor until the voltage of the power supply capacitor drops from VDD_OK to VDD_FORCE, then supply pulsed power to the JFET, and use the pulsed current output by the JFET to intermittently charge the power supply capacitor to make the voltage of the power supply capacitor stable at VDD_FORCE.

2. The circuit according to claim 1, characterized in that, The control module is further configured to: when in the steady-state working state and the bus voltage is lower than VM_UV, first supply full power to the JFET, use the maximum charging current output by the JFET to charge the power supply capacitor until the voltage of the power supply capacitor reaches VDD_OK, then supply pulsed power to the JFET, and use the pulsed current output by the JFET to intermittently charge the power supply capacitor to make the voltage of the power supply capacitor stable at VDD_OK; where VDD_OK is greater than VDD_FORCE.

3. The circuit according to claim 2, wherein The control module is further configured to: during the startup process, use the JFET to output a first current to charge the power supply capacitor until the voltage of the power supply capacitor reaches VDD_OK, end the startup process, and enter the steady-state working state; where the first current is less than the maximum charging current.

4. The circuit according to any one of claims 1-3, characterized in that, The control module includes the JFET, a power supply control logic module, a VDD monitoring module, an LDO module and a bus monitoring module; The drain of the JFET is connected to the bus voltage, the source of the JFET is connected to the first end of the power supply control logic module, the gate of the JFET is grounded, the second end of the power supply control logic module is connected to the input end of the LDO module, and the output end of the LDO module supplies power to the internal modules of the chip; the second end of the power supply control logic module is also connected to the VDD monitoring module, and the second end of the power supply control logic module is also connected to the power supply capacitor.

5. The circuit according to claim 4, wherein In the steady-state working state, when the bus monitoring module monitors that the bus voltage is greater than VM_UV, the bus monitoring module sends a first signal to the power supply control logic module; the VDD monitoring module is used to send a fourth signal to the power supply control logic module when it monitors that the voltage of the power supply capacitor drops to VDD_FORCE; The power supply control logic module is used to, in the steady-state working state, according to the received first signal, control the JFET to stop power supply, supply power by the power supply capacitor until it receives the fourth signal sent by the VDD monitoring module, and control the JFET to output a pulsed current to intermittently charge the power supply capacitor to make the voltage of the power supply capacitor stable at VDD_FORCE.

6. The circuit according to claim 4, wherein In the steady-state working state, when the bus monitoring module monitors that the bus voltage is less than VM_UV, the bus monitoring module sends a second signal to the power supply control logic module; the VDD monitoring module is used to send a third signal to the power supply control logic module when it monitors that the voltage of the power supply capacitor reaches VDD_OK; The power supply control logic module is used to, in the steady-state operating condition, according to the received second signal, first control the JFET to output the maximum charging current to charge the power supply capacitor until receiving the third signal sent by the VDD monitoring module, and then control the JFET to output a pulsed current to charge the power supply capacitor intermittently, so that the voltage of the power supply capacitor is stabilized at VDD_OK.

7. The circuit according to claim 4, wherein During the startup process, the VDD monitoring module is used to monitor when the voltage of the power supply capacitor reaches VDD_OK, and send the third signal to the power supply control logic module; The power supply control logic module is used to, during the startup process, control the JFET to output the first current to charge the power supply capacitor until receiving the third signal sent by the VDD monitoring module, end the startup process, and enter the steady-state operating condition.

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