Motor driving circuit, chip and system
By introducing cache register cascade and signal coverage mechanisms into the motor drive circuit, the problem of incoherence of control signals during motor drive is solved, and more efficient motor control and processor load reduction is achieved.
Patent Information
- Application Number
- CN202422169286.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-04
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-09-04
AI Technical Summary
In the prior art, the control signal and motor feedback during the motor driving process are incoherent, and the processor data processing needs are high, resulting in incoherent control and high processor requirements.
The combination of the receiving module, the first cache register, the second cache register, the third cache register and the bridge arm drive module is adopted. Through the cascading cache and coverage mechanism of the control signal, the signals are ensured to be configured in sequence, the number of data cache stages is increased, and the processor processing frequency is reduced.
Improves the consistency of the motor driving process, reduces data loss, and reduces the processor's data processing requirements.
Smart Images
Figure CN223067028U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuits, and particularly relates to a motor drive circuit, a chip and a system. Background Art
[0002] At present, in order to drive a motor, a dedicated drive chip is usually provided to receive a control signal sent by a processor and convert the control signal into a drive signal for controlling a bridge arm. The processor controls the bridge arm sequentially based on the received control signal. However, through actual measurement, it is found that this method may cause the control signal not to correspond to the motor feedback, resulting in an inconsistent control process of the motor, and the processor needs to process a large amount of data, which requires a high requirement for the processor. Summary of the Utility Model
[0003] The purpose of the embodiments of the utility model is to provide a motor drive circuit, a chip and a system to solve the above problems. The embodiments of the utility model achieve the above purpose through the following technical solutions.
[0004] The embodiments of the utility model provide a motor drive circuit, including: a receiving module for receiving a control signal for controlling a motor; a third buffer register, a second buffer register, and a first buffer register connected in sequence, the third buffer register, the second buffer register, and the first buffer register are respectively connected to the receiving module, the first buffer register configures a first control signal and generates a drive signal, the second buffer register caches a second control signal, the third buffer register caches a third control signal, and after the first buffer register configures the first control signal, the second control signal is filled into the first buffer register; a bridge arm and a bridge arm drive module respectively connected to the first buffer register and the bridge arm, the bridge arm is used to connect to the motor, and during the process that the bridge arm drive module controls a power switch in the bridge arm through the drive signal, the third buffer register covers the third control signal with the newly received control signal.
[0005] In some embodiments, the motor drive circuit further includes a fourth buffer register connected between the first buffer register and the second buffer register, the fourth buffer register is connected to the receiving module, the fourth buffer register caches the control signal sent by the receiving module or the control signal filled by the second buffer register, and fills the cached control signal into the first buffer register.
[0006] In some embodiments, the number of the fourth buffer registers is multiple, and the multiple fourth buffer registers are connected in series in sequence and are respectively connected to the receiving module.
[0007] In some embodiments, the motor drive circuit also includes: an enable module connected to the first cache register, which obtains an enable result representing the enable status from the drive signal; a detection module connected to the feedback end, which detects the electrical signal at the feedback end to generate a detection result; and an abort module, which is respectively connected to the enable module, the detection module, and the bridge arm, and sends an abort signal to the bridge arm when the detection result is abnormal and / or the enable result is prohibited.
[0008] In some embodiments, the number of power switches in the bridge arm is an even number, and the power switches are controlled by the suspension module and the bridge arm driving module.
[0009] In some embodiments, the bridge arm is used to connect to the first motor and the second motor, and the bridge arm driving module includes a configuration unit and a bridge arm driving unit connected in sequence, the configuration unit is connected to the first cache register, and the bridge arm driving unit is connected to the bridge arm, and the configuration unit controls the bridge arm driving unit to drive the bridge arm in time according to the driving signal.
[0010] In some embodiments, the bridge arm includes a first bridge arm and a second bridge arm respectively connected to the bridge arm driving unit, the first bridge arm is used to connect to the first motor, and the second bridge arm is used to connect to the second motor. The bridge arm driving module also includes a switching switch respectively connected to the configuration unit and the bridge arm driving unit, and the switching switch is controlled by the configuration unit to control the bridge arm driving unit to connect to the first bridge arm or the second bridge arm.
[0011] In some embodiments, in the motor driving circuit, the first motor and the second motor are of the same motor type.
[0012] An embodiment of the utility model further provides a motor driving chip, comprising the motor driving circuit provided by any of the above embodiments.
[0013] An embodiment of the utility model further provides a motor drive system, comprising a processor, a motor and the motor drive chip provided in the above embodiment.
[0014] The motor drive chip provided in this embodiment includes a receiving module, a first buffer register, a second buffer register, a third buffer register, a bridge arm drive module, and a bridge arm. By setting the receiving module, the first buffer register, the second buffer register, the third buffer register, the bridge arm drive module, and the connection relationship, it is realized that only the first buffer register needs to configure the control signal in the first buffer register, the second buffer register, and the third buffer register. At the same time, the control signal will always be configured by the first buffer register in sequence. The control signal in the third buffer register will be determined whether to be overwritten based on whether the receiving module receives a new control signal and the configuration of the control signal in the first buffer register. The buffer register set in this way can add two levels of data caching during the motor drive process, reduce data loss, improve the coherence of the motor control process, and reduce the frequency of data processing by the processor, thereby reducing the requirement for data processing by the processor. Description of the Drawings
[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0016] Figure 1 is a circuit structure diagram of a motor drive circuit provided in this embodiment;
[0017] Figure 2 is another circuit structure diagram of a motor drive circuit provided in this embodiment;
[0018] Figure 3 is yet another circuit structure diagram of a motor drive circuit provided in this embodiment;
[0019] Figure 4 is yet another circuit structure diagram of a motor drive circuit provided in this embodiment;
[0020] Figure 5 is a circuit structure diagram of a bridge arm in a motor drive circuit provided in this embodiment;
[0021] Figure 6 is a circuit structure diagram of a motor drive circuit provided in this embodiment. Detailed Embodiments
[0022] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0023] As Figure 1 shown, this embodiment provides a motor drive circuit, which includes: a receiving module 11 for receiving a control signal for controlling a motor 17; a third buffer register 12, a second buffer register 13, and a first buffer register 14 connected in sequence. The third buffer register 12, the second buffer register 13, and the first buffer register 14 are respectively connected to the receiving module 11. The first buffer register 14 configures a first control signal and generates a drive signal. The second buffer register 13 caches a second control signal, and the third buffer register 12 caches a third control signal. After the first buffer register 14 configures the first control signal, the second control signal is filled into the first buffer register 14; a bridge arm 16 and a bridge arm drive module 15 respectively connected to the first buffer register 14 and the bridge arm 16. The bridge arm 16 is used to connect to the motor 17. During the process that the bridge arm drive module 15 controls the power switch in the bridge arm 16 through the drive signal, the third buffer register 12 overwrites the third control signal with the newly received control signal.
[0024] In this embodiment, the receiving module 11 can directly or indirectly obtain a control signal for controlling the motor 17. The receiving module 11 can be connected to a processor to receive the control signal sent by the processor. The communication method between the receiving module 11 and the processor can be a two-way two-wire synchronous serial bus, a full-duplex synchronous serial bus, etc. Here, the communication method between the receiving module 11 and the processor is not specifically limited.
[0025] In this embodiment, the processor sequentially sends a first control signal, a second control signal, and a third control signal to the receiving module 11. During the process that the first buffer register 14 caches and configures the first control signal, the second buffer register 13 caches the second control signal, and the third buffer register 12 caches the third control signal. After the first buffer register 14 finishes configuring the first control signal, the second control signal in the second buffer register 13 is filled into the first buffer register 14, and the third control signal in the third buffer register 12 is filled into the second buffer register 13. After the first buffer register 14 finishes configuring the second control signal, the third control signal in the second buffer register 13 is filled into the first buffer register 14.
[0026] Among them, when the first buffer register 14 buffers the first control signal, the first control signal can be configured according to the pre-set correspondence between the control signal and the driving signal to generate a first driving signal. During the process that the first buffer register 14 buffers the first control signal, if the receiving module 11 receives a new control signal, the new control signal will be buffered by the third buffer register 12, and the third control signal originally buffered by the third buffer register 12 will be overwritten. When the first buffer register 14 buffers the second control signal, the second control signal can be configured according to the pre-set correspondence between the control signal and the driving signal to generate a second driving signal, and so on, and driving signals are generated in sequence to the leg driving module 15.
[0027] In this embodiment, when there is no buffered control signal in the first buffer register 14, the second buffer register 13, and the third buffer register 12, the first buffer register 14, the second buffer register 13, and the third buffer register 12 can respectively receive the control signals sent from the receiving module 11. When there are control signals in both the first buffer register 14 and the second buffer register 13, the receiving module 11 only sends control signals to the third buffer register 12. At this time, the third buffer register 12 can directly buffer the control signals currently sent by the receiving module 11 or overwrite the control signals originally buffered by the control signals sent by the receiving module 11. After the first buffer register 14 configures the currently buffered control signal, the control signal buffered in the second buffer register 13 is filled into the first buffer register 14, and the control signal buffered in the third buffer register 12 is filled into the second buffer register 13.
[0028] In this embodiment, the first buffer register 14 can generate a driving signal through the control signal, and the leg driving module 15 converts the driving signal into a signal for controlling each power switch in the leg 16. As Figure 5 shown, the gates of the power tube switches in the leg 16 can be used as the controlled ends of the leg 16 and are controlled by the leg driving module 15.
[0029] In this embodiment, by setting the receiving module 11, the first buffer register 14, the second buffer register 13, the third buffer register 12, the leg driving module 15 and the connection relationship, it is realized that only the first buffer register 14 needs to configure the control signal in the first buffer register 14, the second buffer register 13 and the third buffer register 12. At the same time, the control signals in the first buffer register 14 and the second buffer register 13 will always be configured by the first buffer register 14 in sequence. Whether the control signal in the third buffer register 12 is overwritten is determined based on whether the receiving module 11 receives a new control signal and the configuration of the control signal in the first buffer register 14. The buffer register set in this way can add two levels of data caching during the driving process of the motor 17, reduce data loss, improve the coherence of the process of controlling the motor 17, and reduce the frequency of data processing by the processor, thereby reducing the requirement for data processing by the processor.
[0030] In order to more clearly understand the working modes of the first buffer register 14, the second buffer register 13, and the third buffer register 12 in this embodiment, an example is given for illustration, as Figure 6 shown in the circuit structure. The first buffer register 14 includes a register U1 and a logic gate U2. The second buffer register 13 includes a register U3, a logic gate U4, and a clock control unit 131. The third buffer register 12 includes a register U5. The register U1 can receive the control signal sent by the register U2 or the receiving module 11. The register U3 can receive the control signal sent by the register U5 or the receiving module 11. The register U5 can receive the control signal sent by the receiving module 11. Specifically, the clock input terminals CLK of the register U1, the register U2, and the register U3 are connected to the clock control unit 131. The output terminal Q1 of the register U1 is connected to the leg driving module 15. The data input terminal D1 of the register U1 is connected to the output terminal of the logic gate U2. The input terminals of the logic gate U2 are respectively connected to the output terminal Q2 of the register U3 and the receiving module 11. The data input terminal D2 of the register U3 is connected to the output terminal of the logic gate U4. The input terminals of the logic gate U4 are respectively connected to the output terminal Q3 of the register U5 and the receiving module 11. The data input terminal D3 of the register U5 is connected to the receiving module 11. Among them, when one or several of the register U1, the register U2, and the register U3 receive or output data, the clock control unit 131 will provide a clock signal to the corresponding register. As Figure 6 shown, the logic gates U2 and U4 can be AND logic gates. The corresponding functions can be realized by matching the logic gates U2 and U4 with the register U1, the register U2, the register U3, and the clock control unit 131. The specific structures of the logic gates U2 and U4 are not specifically limited here.
[0031] In some embodiments, such asFigure 2 As shown, the motor drive circuit may further include a fourth buffer register 18 connected between the first buffer register 14 and the second buffer register 13. The fourth buffer register 18 is connected to the receiving module 11. The fourth buffer register 18 caches the control signal sent by the receiving module 11 or the control signal filled in by the second buffer register 13, and fills the cached control signal into the first buffer register 14. The circuit structure of the fourth buffer register 18 may be the same as that of the second buffer register 13.
[0032] During the process of the first buffer register 14 caching and configuring the first control signal, the fourth buffer register 18, the second buffer register 13, and the third buffer register 12 may respectively receive the control signals sent by the receiving module 11 in sequence. After the first buffer register 14 finishes configuring the first control signal, the control signal cached in the fourth buffer register 18 is filled into the first buffer register 14, the control signal in the second buffer register 13 is filled into the fourth buffer register 18, the control signal in the third buffer register 12 is filled into the second buffer register 13, and the third buffer register 12 caches the new control signal sent by the receiving module 11.
[0033] During the process of the first buffer register 14 caching and configuring the first control signal, if the fourth buffer register 18, the second buffer register 13, and the third buffer register 12 all cache control signals, the new control signal sent by the receiving module 11 at this time will overwrite the control signal in the third buffer register 12.
[0034] Thus, the buffer register set in this way can add three - level data caching during the driving process of the motor 17, improve the coherence of the motor 17 control process, reduce the frequency of the processor processing data, and lower the requirement for the processor data processing.
[0035] In some embodiments, the number of the fourth buffer registers 18 may be multiple. The multiple fourth buffer registers 18 are connected in series in sequence and are respectively connected to the receiving module 11. Among them, the circuit structures of the multiple fourth buffer registers 18 may be the same as the circuit structure of the second buffer register 13. It should be noted that the third buffer register 12, the second buffer register 13, the multiple fourth buffer registers 18, and the first buffer register 14 can respectively cache the control signals sent by the receiving module 11, and finally generate a driving signal under the configuration of the first buffer register 14. After the first buffer register 14 configures the control signal, the control signal in the second buffer register 13 will be filled into one of the multiple fourth buffer registers 18 directly connected to the second buffer register 13. One of the multiple fourth buffer registers 18 connected to the first buffer register 14 will fill the control signal it caches into the first buffer register 14, and so on. During the process of the first buffer register 14 caching the first control signal, if the receiving module 11 receives a new control signal, the new control signal will be cached by the third buffer register 12, and the control signal originally cached by the third buffer register 12 will be overwritten.
[0036] In some embodiments, as Figure 3 shown, the motor drive circuit may further include: an enable module 19 connected to the first buffer register 14 to obtain an enable result representing the enable situation from the driving signal; a detection module 20 connected to the feedback terminal to detect the electrical signal at the feedback terminal to generate a detection result; and an abort module 21 connected to the enable module 19, the detection module 20, and the bridge arm 16 respectively, and sending an abort signal to the bridge arm 16 when the detection result is abnormal and / or the enable result is disabled.
[0037] In this embodiment, the feedback terminal can be used to represent the electrical parameters of each node in the circuit. The electrical parameters can be voltage, current, etc. There is no specific limitation on the specific parameters obtained from the feedback terminal here. The detection module 20 can detect the electrical parameters of the feedback terminal to confirm whether an abnormality occurs in the circuit, and then generate an electrical signal representing whether it is abnormal. This electrical signal can be regarded as the detection result. The first buffer register 14 can generate a driving signal corresponding to the control signal, and the enable module 19 can confirm whether there is a situation of disabling the enable according to the driving signal.
[0038] Therefore, in this embodiment, whether an abnormal signal is sent based on the built-in abnormal detection circuit of the motor drive circuit itself, or when the motor drive circuit receives a signal sent by an external processor representing disabling the enable, an abort signal can be sent to the bridge arm 16 through the abort module 21, so that the drains of the power switches in the bridge arm 16 are in a high-impedance state, and then the motor drive circuit is in an abort state, rather than the way of cancellation in the prior art, reducing the energy consumption of the motor 17 and its drive circuit.
[0039] In some embodiments, the number of power switches in the leg 16 is an even number, and the power switches are controlled by the abort module 21 and the leg drive module 15. Among them, the leg 16 may include one or more H-bridge circuits, and each H-bridge circuit includes two P-type power switches and two N-type power switches. After the abort module 21 sends an abort signal to the leg 16, the two P-type power switches and the two N-type power switches in the H-bridge are all in the off state, thereby making the drain terminals of the two P-type power switches and the drain terminals of the two N-type power switches in a high-impedance state, and the motor 17 corresponding to the H-bridge stops rotating.
[0040] In some embodiments, as Figure 4 shown, the number of motors 17 may be 2, which can be regarded as the first motor 171 and the second motor 172. The leg 16 can be used to connect to the first motor 171 and the second motor 172. The leg drive module 15 may include a configuration unit 151 and a leg drive unit 152 connected in sequence. The configuration unit 151 is connected to the first buffer register 14, and the leg drive unit 152 is connected to the leg 16. The configuration unit 151 controls the leg drive unit 152 to drive the leg 16 in a time-sharing manner according to the drive signal.
[0041] In this embodiment, the configuration unit 151 may determine the target motor to be driven based on the drive signal output by the first buffer register 14. Specifically, the drive signal may have a preset format, and this preset format corresponds to the target motor. The configuration unit 151 can obtain the matching target motor from the drive signal according to this preset format. The leg drive unit 152 can control the leg 16 to drive the first motor 171 or the second motor 172 according to the target motor and the drive signal determined by the configuration unit 151.
[0042] Specifically, taking the first motor 171 and the second motor 172 as DC motors 17 as an example, the leg drive unit 152 can control the leg 16 to drive the first motor 171 at a certain moment and control the leg 16 to drive the second motor 172 at another moment. It can also realize the multiplexing of the leg drive unit 152 by switching the connection relationship between the leg drive unit 152 and the leg 16, reduce the number of leg 16 drive channels to be set, and reduce the chip area. In addition, by switching the connection relationship between the leg 16 and the first motor 171 and the second motor 172, the common multiplexing of the leg drive unit 152 and the leg 16 can be realized. At this time, the area occupied by the power switches required in the leg 16 in the layout can be effectively reduced.
[0043] In some embodiments, the types of the first motor 171 and the second motor 172 may also be different, as Figure 5 shown, taking the H-bridge driving the motor 17 as an example,Figure 5 (a) The dual H-bridge in the bridge arm 16 as shown can be used to drive the first motor 171. Figure 5 (b) The single H-bridge in the bridge arm 16 as shown can be used to drive the second motor 172. When the target motor is the first motor 171, the connection relationship between the bridge arm 16 and the first motor 171 is as Figure 5 (a) shown. When the target motor is the second motor 172, the connection relationship between the bridge arm 16 and the second motor 172 is as Figure 5 (b) shown. Thus, the power switches P1, P2, N1, and N2 in the dual H-bridge are reused, or the power switches P3, P4, N3, and N4 in the dual H-bridge are reused.
[0044] In some embodiments, as Figure 4 shown, the bridge arm 16 may include a first bridge arm 161 and a second bridge arm 162 respectively connected to the bridge arm driving unit 152. The first bridge arm 161 is used to connect to the first motor 171, and the second bridge arm 162 is used to connect to the second motor 172. The bridge arm driving module 15 further includes a switching switch 153 respectively connected to the configuration unit 151 and the bridge arm driving unit 152. The switching switch 153 is controlled by the configuration unit 151 to control the connection between the bridge arm driving unit 152 and the first bridge arm 161 or the second bridge arm 162. Among them, the switching switch 153 can be controlled by the bridge arm driving unit 152. When the target unit is the first motor 171, it controls the bridge arm driving unit 152 to connect to the first bridge arm 161. When the target unit is the second motor 172, it controls the bridge arm driving unit 152 to connect to the second bridge arm 162. At this time, the driving logics required for the first bridge arm 161 and the second bridge arm 162 are the same, especially applicable to the case where the motor types of the first motor 171 and the second motor 172 are the same, greatly reducing the design difficulty of the driving circuit of the bridge arm 16. At the same time, the circuit structure is greatly simplified, reducing the driving power consumption.
[0045] In some embodiments, the motor types of the first motor 171 and the second motor 172 may be the same.
[0046] The embodiment of the present utility model further provides a motor driving chip, and the motor driving chip includes the motor driving circuit provided in any of the above embodiments.
[0047] Since the circuit structure and working mode of the motor driving circuit in the motor driving chip in this embodiment are the same as those of the motor driving circuit in the previous embodiment, they will not be elaborated here.
[0048] The embodiment of the present utility model further provides a motor drive system, which includes a processor, a motor 17, and the motor drive chip provided in the above embodiment. Among them, the processor is connected to the receiving module 11 in the motor drive circuit and sends a control signal to the receiving module 11, and the motor 17 is connected to the bridge arm 16 in the motor drive circuit.
[0049] Since the circuit structure and working mode of the motor drive circuit in the motor drive system in this embodiment are the same as those of the motor drive circuit in the above embodiment, they will not be elaborated here.
[0050] The above embodiments are only used to illustrate the technical solutions of the present utility model, rather than to limit it; although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present utility model, and should all be included in the protection scope of the present utility model.
Claims
1. A motor drive circuit, characterized in that, Comprising: A receiving module for receiving a control signal for controlling a motor; A third buffer register, a second buffer register, and a first buffer register connected in sequence. The third buffer register, the second buffer register, and the first buffer register are respectively connected to the receiving module. The first buffer register configures a first control signal and generates a driving signal. The second buffer register caches a second control signal, and the third buffer register caches a third control signal. After the first buffer register configures the first control signal, the second control signal is filled into the first buffer register; A bridge arm and a bridge arm driving module respectively connected to the first buffer register and the bridge arm. The bridge arm is used to connect to a motor. During the process that the bridge arm driving module controls a power switch in the bridge arm through the driving signal, the third buffer register overwrites the third control signal with a newly received control signal.
2. The motor drive circuit according to claim 1, characterized in that It further includes a fourth buffer register connected between the first buffer register and the second buffer register. The fourth buffer register is connected to the receiving module. The fourth buffer register caches the control signal sent by the receiving module or the control signal filled by the second buffer register, and fills the cached control signal into the first buffer register.
3. The motor drive circuit according to claim 2, wherein The number of the fourth buffer registers is multiple, and the multiple fourth buffer registers are connected in series in sequence and are respectively connected to the receiving module.
4. The motor drive circuit according to claim 1, wherein It further includes: An enabling module connected to the first buffer register, which obtains an enabling result representing the enabling situation from the driving signal; A detection module connected to a feedback terminal, which detects an electrical signal of the feedback terminal to generate a detection result; An abort module respectively connected to the enabling module, the detection module, and the bridge arm, and sends an abort signal to the bridge arm when the detection result is abnormal and / or the enabling result is prohibited.
5. The motor drive circuit according to claim 4, wherein, The number of the power switches in the bridge arm is an even number, and the power switches are controlled by the abort module and the bridge arm driving module.
6. The motor drive circuit according to any one of claims 1 to 5, characterized in that The bridge arm is used to connect to a first motor and a second motor. The bridge arm driving module includes a configuration unit and a bridge arm driving unit connected in sequence. The configuration unit is connected to the first buffer register, and the bridge arm driving unit is connected to the bridge arm. The configuration unit controls the bridge arm driving unit to drive the bridge arm in a time-sharing manner according to the driving signal.
7. The motor drive circuit according to claim 6, wherein, The bridge arm includes a first bridge arm and a second bridge arm respectively connected to the bridge arm driving unit. The first bridge arm is used to connect to the first motor, and the second bridge arm is used to connect to the second motor. The bridge arm driving module further includes a switching switch respectively connected to the configuration unit and the bridge arm driving unit. The switching switch is controlled by the configuration unit to connect the bridge arm driving unit to the first bridge arm or the second bridge arm.
8. The motor drive circuit according to claim 7, wherein The motor types of the first motor and the second motor are the same.
9. A motor drive chip, characterized in that, Including the motor driving circuit according to any one of claims 1 to 8.
10. A motor drive system, characterized in that, Including a processor, a motor, and the motor driving chip according to claim 9.