Narrow pulse generating device and pulse laser light source
Through the combination of controller, RC circuit, digital-to-analog converter, comparator and logic gate circuit, the problem of high cost of narrow pulse signals is solved, and low-cost narrow pulse signals are achieved to meet the driving needs of the laser.
Patent Information
- Application Number
- CN202422222719.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-09-10
AI Technical Summary
In the prior art, narrow pulse signals are usually generated by FPGAs, resulting in high costs and waste of resources, making it difficult to generate narrow pulse signals at a lower cost.
A narrow pulse generation device composed of a controller, RC circuit, digital-to-analog converter, comparator and logic gate circuit is used to delay the rising and falling edges of the pulse signal through the RC circuit, and the comparator performs comparison, and the logic gate circuit performs XOR operation, converting the wide pulse signal into a narrow pulse signal.
It realizes the generation of narrow pulse signals at a lower cost, avoids the use of expensive ultra-high speed controllers, and meets the frequency and pulse width requirements of narrow pulse signals.
Smart Images
Figure CN223079550U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of fiber optic sensing, and particularly to a narrow pulse generating device and a pulsed laser light source. Background Art
[0002] In the field of fiber optic sensing, narrow pulse laser light sources (with pulse widths generally adjustable from 1 nS to 10 nS and pulse frequencies adjustable from 100 Khz to 1 Mhz) are required in devices such as lidar, laser rangefinders, optical time domain reflectometers, and distributed fiber optic temperature measuring instruments. The smaller the pulse width, the smaller the resolution and the higher the measurement accuracy. The driving of a narrow pulse laser light source first requires a narrow pulse signal, and the pulse width is consistent with the pulse source signal.
[0003] According to conventional designs, narrow pulse signals are usually generated by a Field-Programmable Gate Array (FPGA for short). However, the smaller the pulse width, the higher the operating speed and cost required for the FPGA. For example, for a pulse width of 1 nS, the clock frequency of the FPGA needs to reach above 1 G, which will significantly increase the cost and cause a great waste of resources.
[0004] In view of this, overcoming the defects of the existing technology is an urgent problem to be solved in this technical field. Summary of the Utility Model
[0005] The technical problem to be solved by the utility model is how to generate narrow pulse signals at a lower cost.
[0006] The utility model adopts the following technical solutions:
[0007] In a first aspect, a narrow pulse generating device is provided, including: a controller, an RC circuit, a digital-to-analog converter, a comparator, and a logic gate circuit; the output end of the controller is connected to the input end of the RC circuit; the output end of the RC circuit is connected to the positive input end of the comparator, and the output end of the digital-to-analog converter is connected to the negative input end of the comparator;
[0008] The output end of the comparator is connected to one input end of the logic gate circuit, and the output end of the controller is also connected to the other input end of the logic gate circuit;
[0009] The controller is used to output a first pulse signal, the digital-to-analog converter is used to output a reference level, and the RC circuit is used to delay the rising edge and falling edge of the first pulse signal to obtain a second pulse signal;
[0010] The comparator is configured to compare the reference level with the second pulse signal and output a third pulse signal according to the comparison result; the logic gate circuit is configured to perform an exclusive-OR operation on the third pulse signal and the first pulse signal to output a narrow pulse signal.
[0011] Preferably, the logic gate circuit includes a first logic circuit; the output terminal of the comparator is connected to one input terminal of the first logic circuit, and the other input terminal of the first logic circuit is connected to the output terminal of the controller;
[0012] Wherein, the first logic circuit is an exclusive-OR gate circuit.
[0013] Preferably, the logic gate circuit further includes a second logic circuit, and the output terminal of the first logic circuit is connected to one input terminal of the second logic circuit; the other input terminal of the second logic circuit is connected to the output terminal of the controller;
[0014] Wherein, the second logic circuit is an AND gate circuit.
[0015] Preferably, the comparator includes an operational amplifier, the positive input terminal of the operational amplifier is connected to the output terminal of the RC circuit, and the negative input terminal of the operational amplifier is connected to the output terminal of the digital-to-analog converter; the output terminal of the operational amplifier is connected to one input terminal of the logic gate circuit.
[0016] Preferably, the RC circuit includes a resistor and a capacitor, one end of the resistor is connected to the output terminal of the controller, the other end of the resistor is respectively connected to one end of the capacitor and the positive input terminal of the operational amplifier, and the other end of the capacitor is grounded.
[0017] Preferably, the frequency of the narrow pulse signal is equal to the frequency of the first pulse signal.
[0018] Preferably, the magnitude of the reference level depends on the pulse width of the narrow pulse signal.
[0019] Preferably, the pulse width of the narrow pulse signal is 0.8 nS - 10 nS.
[0020] In a second aspect, a pulsed laser light source is provided, which includes the narrow pulse generating device, a switching tube and a laser as described in the first aspect; the output terminal of the logic gate circuit is connected to the control terminal of the switching tube, the positive electrode of the laser is connected to a positive voltage, the negative electrode of the laser is connected to one end of the switching tube, and the other end of the switching tube is grounded.
[0021] Preferably, the switching tube is a triode. The base of the triode is connected to the output terminal in the logic gate circuit. The collector of the triode is connected to the negative electrode of the laser, and the emitter of the triode is grounded.
[0022] Compared with the prior art, the beneficial effects of the present utility model are as follows:
[0023] The present utility model uses a conventional low-speed controller, a common digital-to-analog converter, and a conventional logic gate circuit to convert a wide pulse signal into a narrow pulse signal, avoiding the use of expensive ultra-high-speed controllers, and being able to generate narrow pulse signals at a relatively low cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0025] Figure 1 is a schematic structural diagram of a narrow pulse generating device provided by an embodiment of the present utility model;
[0026] Figure 2 is a schematic comparison diagram of pulse signal waveforms provided by an embodiment of the present utility model;
[0027] Figure 3 is a more specific schematic structural diagram of a narrow pulse generating device provided by an embodiment of the present utility model;
[0028] Figure 4 is a schematic comparison diagram of several more specific pulse signal waveforms provided by an embodiment of the present utility model;
[0029] Figure 5 is a schematic circuit diagram of a narrow pulse generating device provided by an embodiment of the present utility model;
[0030] Figure 6 is a schematic structural diagram of a pulsed laser light source provided by an embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0031] In order to make the purpose, technical solutions and advantages of the present utility model more clear, the following further details the present utility model in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.
[0032] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted in an open - inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples", etc., are intended to indicate that specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above - mentioned terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner. That is, although they may be carried in the embodiments or examples of the above - mentioned terms due to reasons such as the order and position of appearance, it is not limited that they can be carried by one embodiment or example in a combined manner.
[0033] In the description of the present utility model, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more. In addition, for example, in the description, for the same type of nouns, the method of adding "A" and "B" at the end is used to describe them as two independent individuals. In this case, the features defined with "A" and "B" are only used for the purpose of distinguishing similar individuals and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.
[0034] When describing some embodiments, expressions such as "coupled", "coupled to", and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Another example is that when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. However, the term "connected" or "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other, such as "optical path coupling", "wireless connection", etc. The embodiments disclosed herein are not necessarily limited to the content of the present utility model.
[0035] In addition, the technical features involved in the various embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.
[0036] Embodiment 1:
[0037] The driving of a laser light source requires a narrow pulse signal. In the prior art, the narrow pulse signal is usually obtained from an FPGA. The "narrow" in the narrow pulse signal is relative to the pulse width of the original pulse square wave signal. The smaller the pulse width, the higher the operating speed required for the FPGA, resulting in an increase in power consumption and possibly affecting the stability of the system.
[0038] To solve the above problems, an embodiment of the present utility model provides a narrow pulse generating device, as Figure 1 shown, including: a controller, an RC circuit, a digital-to-analog converter, a comparator, and a logic gate circuit; the output end of the controller is connected to the input end of the RC circuit; the output end of the RC circuit is connected to the positive input end of the comparator, and the output end of the digital-to-analog converter is connected to the negative input end of the comparator; the output end of the comparator is connected to one input end of the logic gate circuit, and the output end of the controller is also connected to the other input end of the logic gate circuit; the controller is used to output a first pulse signal, the digital-to-analog converter is used to output a reference level, and the RC circuit is used to delay the rising edge and falling edge of the first pulse signal to obtain a second pulse signal; the comparator is used to compare the reference level and the second pulse signal and output a third pulse signal according to the comparison result; the logic gate circuit is used to perform an exclusive OR operation on the third pulse signal and the first pulse signal to output a narrow pulse signal.
[0039] Among them, the first pulse signal is the original pulse square wave signal. The main purpose of this embodiment is to obtain a narrow pulse signal with a pulse width smaller than that of the first pulse signal according to the first pulse signal, and drive the laser with the narrow pulse signal.
[0040] Specifically, adjust the reference level output by the digital-to-analog converter and / or the slow-down time of the rising edge and falling edge of the second pulse signal output by the RC circuit according to the pulse width of the narrow pulse signal, so as to output the corresponding third pulse signal. Then, after inputting the third pulse signal and the first pulse signal into the logic gate circuit for processing, a narrow pulse signal with the corresponding pulse width can be obtained.
[0041] Since adjusting the RC circuit requires adjusting the resistance value or capacitance value, which is relatively troublesome and is greatly affected by unstable factors (other devices in the circuit) in the circuit, this embodiment directly selects to control the amplitude of the reference level output by the digital-to-analog converter to adjust the pulse width of the obtained narrow pulse signal. That is, on the premise that the second pulse signal remains unchanged, the smaller the amplitude of the reference level, the smaller the pulse width of the narrow pulse signal. The generation of the narrow pulse signal will be described in more detail below.
[0042] In one embodiment, asFigure 2 As shown, when the voltage of the second pulse signal is greater than the voltage of the reference level, the comparator outputs a high level; when the voltage of the second pulse signal is less than the voltage of the reference level, the comparator outputs a low level, so as to obtain the third pulse signal.
[0043] Among them, in Figure 2 , the waveform of the first pulse signal is represented as waveform 1, the waveform of the reference level is represented as waveform 2, the waveform of the second pulse signal is represented as waveform 3, and the waveform of the third pulse signal is waveform 4. T1 is the pulse width of the first pulse signal, which is the same hereinafter and will not be elaborated in this embodiment.
[0044] Under the action of the comparator, the third pulse signal is delayed by T4 relative to the first pulse signal at the rising edge of the signal; taking the first cycle as an example, the first intersection point of the waveform of the reference level and the waveform of the second pulse signal is point A. On the premise that the second pulse signal remains unchanged, when the amplitude V2 of the reference level becomes smaller, point A moves to the left, and at this time T4 becomes smaller; when the amplitude V2 of the reference level becomes larger, point A moves to the right, and at this time T4 becomes larger; after obtaining the third pulse signal, the third pulse signal and the first pulse signal are processed through a logic gate circuit to obtain a narrow pulse signal.
[0045] In one embodiment, as Figure 3 shown, the logic gate circuit includes a first logic circuit; the output end of the comparator is connected to one input end of the first logic circuit, and the other input end of the first logic circuit is connected to the output end of the controller; among them, the first logic circuit is an exclusive OR gate circuit. When the first pulse signal and the third pulse signal are both high level or both low level, the first logic circuit outputs a low level; when the levels of the first pulse signal and the third pulse signal are different, the first logic circuit outputs a high level to obtain a fourth pulse signal. The pulse width of the fourth pulse signal is a narrow pulse width compared with the first pulse signal, and the fourth pulse signal is a kind of narrow pulse signal.
[0046] In one embodiment, assuming that the delay time of the RC circuit is fixed, the magnitude of the reference level depends on the pulse width of the narrow pulse signal, and the pulse width of the fourth pulse signal can be adjusted by adjusting the amplitude of the reference level to adjust the pulse width of the narrow pulse signal.
[0047] The frequency of the narrow pulse signal obtained in the foregoing manner is different from the frequency of the first pulse signal. In order to obtain a narrow pulse signal with the same frequency as the first pulse signal, in one embodiment, as Figure 3As shown, the logic gate circuit further includes a second logic circuit. The output terminal of the first logic circuit is connected to an input terminal of the second logic circuit; the other input terminal of the second logic circuit is connected to the output terminal of the controller; wherein, the second logic circuit is an AND gate circuit. When both the first pulse signal and the fourth pulse signal are at a high level, the second logic circuit outputs a high level; when both the first pulse signal and the fourth pulse signal are at a low level or have different levels, the second logic circuit outputs a low level to obtain a narrow pulse signal with the same frequency as the first pulse signal. That is, under the action of the second logic circuit, the frequency of the narrow pulse signal evolved from the fourth pulse signal is equal to the frequency of the first pulse signal.
[0048] Wherein, as Figure 3 and Figure 4 shown, waveform 5 represents the waveform of the fourth pulse signal, and waveform 6 represents the narrow pulse signal. The main purpose of the first logic circuit is to obtain a pulse signal with a narrow pulse width (i.e., the fourth pulse signal) based on the third pulse signal and the first pulse signal. At this time, the pulse width of the fourth pulse signal has become smaller, but its frequency cannot match that of the first pulse signal. Therefore, in order to obtain a narrow pulse signal that matches the frequency of the first pulse signal, the second logic circuit is added to the logic gate circuit. The second logic circuit is used to adjust the frequency of the fourth pulse signal so that the frequency of the fourth pulse signal is consistent with the frequency of the first pulse signal.
[0049] As Figure 4 shown, the third pulse signal and the first pulse signal are input into the exclusive-OR gate circuit. After an exclusive-OR operation (when the input signals are both 1 or both 0, the output signal is 0; when the input signals are different, the output is 1), the fourth pulse signal is output. The smaller the delay T4 of the third pulse signal relative to the first pulse signal at the rising edge of the signal, the smaller the pulse width T5 of the fourth pulse signal; then the fourth pulse signal and the first pulse signal are input into the AND gate circuit. After an AND operation (when the input signals are both 1, the output is 1, otherwise it is 0), the narrow pulse signal is output. The pulse width T6 of the narrow pulse signal matches the pulse width T5 of the fourth pulse signal. When the pulse width T5 of the fourth pulse signal is smaller, T6 is smaller. By adjusting the magnitude of the reference level V2, the pulse width of the narrow pulse signal can be changed. The entire adjustment process is that the smaller V2 is, the smaller T4 is, and the smaller T5 and T6 are, thereby realizing the adjustment of the pulse width and frequency of the narrow pulse signal.
[0050] In one embodiment, the pulse width of the narrow pulse signal is 0.8 nS - 10 nS. That is, by adjusting the amplitude of the reference level, the pulse width of the obtained narrow pulse signal can reach 0.8 nS, 10 nS, or any pulse width value between 0.8 nS and 10 nS. Specifically, the pulse width of the narrow pulse signal can be determined according to the actual usage requirements (i.e., the time to control the laser to turn on and off), and more specifically, no further description will be given in this embodiment.
[0051] In one embodiment, the functions of the exclusive - OR gate and the AND gate can also be implemented by combining other types of logic gates. Specifically, no further description will be given in this embodiment.
[0052] Through the above - mentioned structure and adjustment method, the first pulse signal with a wide pulse width generated by an ordinary controller is converted into a narrow pulse signal. The pulse frequency remains unchanged and the pulse width is adjustable. The minimum pulse width can be less than 1 nS, which can meet the actual requirements.
[0053] Next, the structure of the narrow - pulse generating device will be specifically described according to the actual circuit schematic diagram. The following description will be combined with specific circuit examples to elaborate on the solution content. As those skilled in the art, the circuits in the corresponding drawings should not be regarded as the only implementation manner of the technical solution of the present invention. Instead, the core inventive concept of the present invention should be condensed from them, and the circuit structures within a reasonable range extended based on this should be regarded as within the protection scope of the present invention.
[0054] In one embodiment, as Figure 5 shown, the comparator includes an operational amplifier. The positive input terminal of the operational amplifier is connected to the output terminal of the RC circuit, and the negative input terminal of the operational amplifier is connected to the output terminal of the digital - to - analog converter; the output terminal of the operational amplifier is connected to one input terminal of the logic - gate circuit.
[0055] Among them, the operational amplifier is labeled as U2. The principle of implementing the comparator through the operational amplifier U2 is based on the characteristics of the operational amplifier: high open - loop gain, high input impedance, and low output impedance. Ideally, the operational amplifier U2 adjusts the output voltage according to the magnitude of the voltage difference between the input terminals. If the voltage of the non - inverting input terminal is higher than that of the inverting input terminal, the operational amplifier U2 outputs a high level; if the voltage of the inverting input terminal is higher than that of the non - inverting input terminal, the operational amplifier U2 outputs a low level. When the two input signals are equal, the voltage difference between the non - inverting input terminal and the inverting input terminal is zero, and the output of the operational amplifier U2 remains unchanged. When the two input signals are not equal, the voltage difference causes the output voltage of the operational amplifier U2 to quickly change to a high level or a low level.
[0056] In one embodiment, as Figure 5As shown, the RC circuit includes a resistor and a capacitor. One end of the resistor is connected to the output end of the controller, and the other end of the resistor is respectively connected to one end of the capacitor and the positive input end of the operational amplifier. The other end of the capacitor is grounded.
[0057] Among them, the resistor is resistor R3, and the capacitor is capacitor C5. Adjusting the parameters of the RC circuit can change the slowdown time of the rising edge and falling edge of the first pulse signal, thereby obtaining the second pulse signal. This is because the charge and discharge characteristics of the RC circuit affect the signal change rate. When the first pulse signal is received, capacitor C5 starts to charge or discharge. During the charging process, the process of capacitor C5 charging from 0 voltage to the voltage equal to both ends of resistor R3 is an exponential growth process. During the discharging process, the process of capacitor C5 discharging from the maximum voltage to 0 voltage is also an exponential decay process. The time constant τ of the RC circuit is determined by the values of resistor R3 and capacitor C5, τ = R3 * C5. The time constant τ represents the charging and discharging speed of capacitor C5. The larger the time constant, the slower the charging and discharging speed of capacitor C5, and the longer the slowdown time of the rising edge and falling edge.
[0058] At the rising edge of the first pulse signal, capacitor C5 starts to charge from 0 voltage, and its voltage increases with time. Since the charging process is exponential growth, it takes about 4τ for the output voltage of the RC circuit to rise to about 99.99% of the final value. This time is the slowdown time of the rising edge.
[0059] At the falling edge of the first pulse signal, capacitor C5 starts to discharge, and its voltage decreases with time. Similarly, since the discharging process is exponential decay, it also takes about 4τ for the output voltage of the RC circuit to drop to about 99.99% of the final value. This time is the slowdown time of the falling edge.
[0060] By adjusting the resistance value of resistor R3 and the capacitance value of capacitor C5, the size of the time constant τ can be changed, thereby changing the slowdown time of the rising edge and falling edge. If a faster rising edge and falling edge are desired, the value of τ can be reduced, that is, the values of resistor R3 or capacitor C5 are reduced; if a slower rising edge and falling edge are desired, the value of τ can be increased, that is, the values of resistor R3 or capacitor C5 are increased. However, based on the convenience of adjustment, generally, the parameters of the RC circuit are not directly adjusted, but the amplitude of the reference level of the output of the digital-to-analog converter is adjusted (see the above for details), and no specific description will be given here.
[0061] In one embodiment, referring to Figure 5 , in Figure 5Among them, U1 is an exclusive-OR gate, and the model of the exclusive-OR gate is 74LVC1G32; U3 is an AND gate, and the model of the AND gate is SN74LVC1G08IDCKRQ1. The model of the digital-to-analog converter is TPC116S4, and its output terminal VOUTA is connected to the inverting input terminal of the operational amplifier U2. For other structures in the narrow pulse generating device, refer to Figure 5 , and no further description will be given in this embodiment.
[0062] In this embodiment, a conventional low-speed controller, an ordinary digital-to-analog converter, and a conventional logic gate circuit are used to convert a wide pulse signal into a narrow pulse signal, avoiding the use of expensive ultra-high-speed controllers, and being able to generate narrow pulse signals at a relatively low cost.
[0063] Embodiment 2:
[0064] In Embodiment 1, a narrow pulse generating device was proposed. In this embodiment, a pulsed laser light source will be proposed, such as Figure 6 shown, including the narrow pulse generating device, a switching tube, and a laser described in Embodiment 1; the output terminal of the logic gate circuit is connected to the control terminal of the switching tube, the positive electrode LD+ of the laser is connected to a positive voltage, the negative electrode LD- of the laser is connected to one end of the switching tube, and the other end of the switching tube is grounded.
[0065] In one embodiment, referring to Figure 6 , the switching tube is a triode Q1, the base of the triode Q1 is connected to the output terminal of the AND gate circuit in the logic gate circuit, the collector of the triode Q1 is connected to the negative electrode of the laser, and the emitter of the triode Q1 is grounded.
[0066] In one embodiment, the switching tube can also be a field effect transistor or a switching chip, and no specific limitation is made here.
[0067] Among them, the narrow pulse generating device is used to generate a narrow pulse signal, and the narrow pulse signal is used to drive the conduction or cut-off of the triode, thereby adjusting the emission or turning off of the laser. For the specific structure of the narrow pulse generating device and the generation process of the narrow pulse signal, refer to Embodiment 1, and no further description will be given in this embodiment.
[0068] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A narrow pulse generating device, characterized in that, Comprising: A controller, an RC circuit, a digital-to-analog converter, a comparator, and a logic gate circuit; the output end of the controller is connected to the input end of the RC circuit; The output end of the RC circuit is connected to the positive input end of the comparator, and the output end of the digital-to-analog converter is connected to the negative input end of the comparator; The output end of the comparator is connected to one input end of the logic gate circuit, and the output end of the controller is also connected to the other input end of the logic gate circuit; The controller is used to output a first pulse signal, the digital-to-analog converter is used to output a reference level, and the RC circuit is used to delay the rising edge and falling edge of the first pulse signal to obtain a second pulse signal; The comparator is used to compare the reference level and the second pulse signal and output a third pulse signal according to the comparison result; The logic gate circuit is used to perform an exclusive-OR operation on the third pulse signal and the first pulse signal to output a narrow pulse signal.
2. The narrow pulse generating device according to claim 1, wherein The logic gate circuit includes a first logic circuit; the output end of the comparator is connected to one input end of the first logic circuit, and the other input end of the first logic circuit is connected to the output end of the controller; Wherein, the first logic circuit is an exclusive-OR gate circuit.
3. The narrow pulse generating device according to claim 2, characterized in that, The logic gate circuit further includes a second logic circuit, and the output end of the first logic circuit is connected to one input end of the second logic circuit; the other input end of the second logic circuit is connected to the output end of the controller; Wherein, the second logic circuit is an AND gate circuit.
4. The narrow pulse generating device according to any one of claims 1-3, characterized in that, The comparator includes an operational amplifier, the positive input end of the operational amplifier is connected to the output end of the RC circuit, and the negative input end of the operational amplifier is connected to the output end of the digital-to-analog converter; the output end of the operational amplifier is connected to one input end of the logic gate circuit.
5. The narrow pulse generating device according to claim 4, characterized in that, The RC circuit includes a resistor and a capacitor, one end of the resistor is connected to the output end of the controller, the other end of the resistor is respectively connected to one end of the capacitor and the positive input end of the operational amplifier, and the other end of the capacitor is grounded.
6. The narrow pulse generating device according to any one of claims 1-3, characterized in that, The frequency of the narrow pulse signal is equal to the frequency of the first pulse signal.
7. The narrow pulse generating device according to any one of claims 1-3, characterized in that, The magnitude of the reference level depends on the pulse width of the narrow pulse signal.
8. The narrow pulse generating device according to any one of claims 1-3, characterized in that The pulse width of the narrow pulse signal is 0.8 nS - 10 nS.
9. A pulsed laser light source, characterized in that, Comprising the narrow pulse generating device according to any one of claims 1 - 8, a switching tube, and a laser; the output end of the logic gate circuit is connected to the control end of the switching tube, the positive electrode of the laser is connected to a positive voltage, the negative electrode of the laser is connected to one end of the switching tube, and the other end of the switching tube is grounded.
10. The pulsed laser light source according to claim 9, wherein The switching tube is a triode, the base of the triode is connected to the output end in the logic gate circuit, the collector of the triode is connected to the negative electrode of the laser, and the emitter of the triode is grounded.