Integrated circuit

Abstract

The utility model provides an integrated circuit which comprises a first grid electrode, a second grid electrode, a third grid electrode, a fourth grid electrode, a first input pin and a first conductor. The first gate and the third gate are located on the first level. The second gate and the fourth gate are on the second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. A first input pin extends in the second direction, is on the first metal layer over the front side of the substrate, is coupled to the first gate, and is configured to receive a first input signal. The first input pin is electrically coupled to the third gate via the first gate, the second gate or the fourth gate. A first conductor extends in a first direction, is located on the second metal layer below the backside of the substrate, and is coupled to the second gate and the fourth gate.

Description

Technical Field

[0001] The utility model relates to an integrated circuit. Background Art

[0002] The semiconductor integrated circuit (IC) industry has produced a variety of digital devices to solve problems in many different fields. Some of these digital devices (such as memory macros) are configured to store data. As ICs have become smaller and more complex, the resistance of the wires within these digital devices has also changed, thereby affecting the operating voltage of these digital devices and the overall IC performance. Summary of the Utility Model

[0003] The utility model provides an integrated circuit, comprising: a first gate located on a first level; a second gate located on a second level below the first level and coupled to the first gate; a third gate located on the first level and separated from the first gate in a first direction; a fourth gate located on the second level, separated from the second gate in the first direction and coupled to the third gate; a first input pin extending in a second direction different from the first direction, on a first metal layer above the front side of the substrate, coupled to at least the first gate and configured to receive a first input signal; and a first conductor extending in the first direction, on a second metal layer below the back side of the substrate opposite to the front side of the substrate, and the first conductor is coupled to at least the second gate and the fourth gate, wherein the first input pin is electrically coupled to the third gate through at least the first gate, the second gate or the fourth gate.

[0004] In some embodiments, the present utility model provides an integrated circuit, comprising: a first transistor stack located on a substrate, the first transistor stack comprising: a first transistor of a first type, the first transistor comprising a first gate located on a first level; and a second transistor of a second type different from the first type, and the second transistor comprising a second gate, the second gate being located on a second level below the first level; a second transistor stack located on the substrate, the second transistor stack comprising: a third transistor of the first type, the third transistor comprising a third gate located on the first level and separated from the first gate in a first direction; and a fourth transistor of the second type, the fourth transistor comprising a fourth gate located on the second level and separated from the third gate in the first direction; a first input pin extending in a second direction, located above a front side of the substrate on a first metal layer and coupled to the first transistor and the second transistor; and a first conductor extending in the first direction, located below a back side of the substrate opposite to the front side of the substrate on a second metal layer, and the first conductor is coupled to the third gate and the fourth gate, wherein the first input pin is electrically coupled to the third gate from the back side of the substrate.

[0005] In some embodiments, the present utility model provides a method of manufacturing an integrated circuit, the method comprising: fabricating a first group of transistors and a second group of transistors in a front side of a substrate, the first group of transistors being stacked above the second group of transistors, the first group of transistors comprising a first transistor and a second transistor, the second group of transistors comprising a third transistor and a fourth transistor; and electrically coupling at least a first conductor on the front side of the substrate to at least a first gate of the first group of transistors through at least a back side of the substrate, wherein electrically coupling at least the first conductor on the front side of the substrate to at least the first gate of the first group of transistors through at least the back side of the substrate comprises: fabricating a first group of vias on the front side of the substrate, the first group of vias being electrically coupled to at least the first group of transistors; depositing a first conductive material on the front side of the substrate at a first metal level thereby forming a first group of conductors, the first group of conductors being electrically coupled to at least the first group of transistors through the first group of vias, the first group of conductors comprising at least the first conductor; fabricating a second group of vias on the thinned back side of the substrate, the second group of vias being electrically coupled to at least the second group of transistors; and depositing a second conductive material on the thinned back side of the substrate at a second metal level thereby forming a second group of conductors, the second group of conductors being electrically coupled to at least the second group of transistors through the second group of vias.

[0006] To make the above features and advantages of the present utility model more obvious and understandable, specific embodiments are given below and detailed descriptions are provided in conjunction with the accompanying drawings as follows. Description of the Drawings

[0007] By reading the following detailed description in conjunction with the accompanying drawings, various aspects of the present utility model will be best understood. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale. In fact, for the sake of clarity of discussion, the sizes of the various features can be arbitrarily increased or decreased.

[0008] Figure 1 is a circuit diagram of an integrated circuit according to some embodiments.

[0009] Figures 2A to 2B is a corresponding diagram of a corresponding part of the layout design of the corresponding integrated circuit according to some embodiments.

[0010] Figures 3A to 3E is a diagram of an integrated circuit according to some embodiments.

[0011] Figure 4A is a block diagram of an integrated circuit according to some embodiments.

[0012] Figure 4B is a circuit diagram of an integrated circuit according to some embodiments.

[0013] Figures 5A to 5B is a diagram of an integrated circuit according to some embodiments.

[0014] Figures 6A to 6D is a diagram of an integrated circuit according to some embodiments.

[0015] Figures 7A to 7B is a functional flowchart of a corresponding method for manufacturing an IC device according to some embodiments.

[0016] Figure 8 is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0017] Figure 9 is a flowchart of a method for generating a layout design of an integrated circuit according to some embodiments.

[0018] Figure 10 is a schematic diagram of a system for designing an IC layout design and manufacturing an IC circuit according to some embodiments.

[0019] Figure 11 is a block diagram of an IC manufacturing system and an associated IC manufacturing process according to at least one embodiment of the present utility model. Detailed Description of the Embodiments

[0020] The following disclosure provides different embodiments or examples for implementing the various features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like are set forth below to simplify the present utility model. Of course, these are merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like are also contemplated. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present utility model may reuse reference numerals and / or letters in various examples. Such reuse is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] In addition, for ease of illustration, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and similar terms may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0022] According to some embodiments, an integrated circuit includes a first gate and a second gate. In some embodiments, the first gate is located on a first level. In some embodiments, the second gate is located on a second level. In some embodiments, the second level is located below the first level. In some embodiments, the second gate is coupled to the first gate.

[0023] In some embodiments, the integrated circuit further includes a third gate located on the first level. In some embodiments, the third gate is separated from the first gate in a first direction.

[0024] In some embodiments, the integrated circuit further includes a fourth gate located on the second level.

[0025] In some embodiments, the fourth gate is separated from the second gate in a first direction. In some embodiments, the fourth gate is coupled to the third gate.

[0026] In some embodiments, the integrated circuit further includes a first input pin extending in a second direction. In some embodiments, the second direction is different from the first direction. In some embodiments, the first input pin is located on a first metal layer. In some embodiments, the first metal layer is located above the front side of the substrate. In some embodiments, the first input pin is coupled to at least a first gate. In some embodiments, the first input pin is configured to receive a first input signal.

[0027] In some embodiments, the integrated circuit further includes a first conductor extending in a first direction. In some embodiments, the first conductor is coupled to at least a second gate and a fourth gate. In some embodiments, the first conductor is located on a second metal layer. In some embodiments, the second metal layer is located below the back side of the substrate, and the back side of the substrate is opposite to the front side of the substrate.

[0028] In some embodiments, the first input pin is electrically coupled to a third gate through at least the first gate, the second gate, or the fourth gate. In some embodiments, the first input pin is electrically coupled to the third gate from the back side of the substrate through at least the second gate or the fourth gate.

[0029] In some embodiments, by electrically coupling the first input pin from the back side of the substrate to the third gate, one or more back-side metallization levels can be used as additional wiring resources, thereby enabling the integrated circuit to have at least one of a reduced pitch, a smaller area, or a smaller standard cell compared to other methods.

[0030] Figure 1 is a circuit diagram of an integrated circuit 100 according to some embodiments.

[0031] In some embodiments, the integrated circuit 100 is a 4-2 NOR logic gate circuit. The 4-2 NOR logic gate circuit is used for illustration, and other types of circuits are within the scope of the present invention. In some embodiments, other numbers of inputs or transistors of the integrated circuit 100 are within the scope of the present invention.

[0032] The integrated circuit 100 includes P field effect transistors (PFETs) P1-L, P2-L, P3-L, P4-L, P1-R, P2-R, P3-R, and P4-R, and N field effect transistors (NFETs) N1-L, N2-L, N3-L, N4-L, N1-R, N2-R, N3-R, and N4-R.

[0033] The gate terminal of PFET transistor P1-L is configured as an input node (not labeled) for receiving input signal A1. The gate terminal of NFET transistor N1-L is configured as an input node (not labeled) for receiving input signal A1.

[0034] The gate terminal of PFET transistor P1-R is configured as an input node (not labeled) for receiving input signal A1. The gate terminal of NFET transistor N1-R is configured as an input node (not labeled) for receiving input signal A1.

[0035] In some embodiments, at least one of the gate terminals of PFET transistor P1-L, NFET transistor N1-L, PFET transistor P1-R, or NFET transistor N1-R is coupled to another one of at least one of the gate terminals of PFET transistor P1-L, NFET transistor N1-L, PFET transistor P1-R, or NFET transistor N1-R.

[0036] The gate terminal of PFET transistor P2-L is configured as an input node (not labeled) for receiving input signal A2. The gate terminal of NFET transistor N2-L is configured as an input node (not labeled) for receiving input signal A2.

[0037] The gate terminal of PFET transistor P2-R is configured as an input node (not labeled) for receiving input signal A2. The gate terminal of NFET transistor N2-R is configured as an input node (not labeled) for receiving input signal A2.

[0038] In some embodiments, at least one of the gate terminals of PFET transistor P2-L, NFET transistor N2-L, PFET transistor P2-R, or NFET transistor N2-R is coupled to another one of at least one of the gate terminals of PFET transistor P2-L, NFET transistor N2-L, PFET transistor P2-R, or NFET transistor N2-R.

[0039] The gate terminal of PFET transistor P3-L is configured as an input node (not labeled) for receiving input signal A3. The gate terminal of NFET transistor N3-L is configured as an input node (not labeled) for receiving input signal A3.

[0040] The gate terminal of PFET transistor P3-R is configured as an input node (not labeled) for receiving input signal A3. The gate terminal of NFET transistor N3-R is configured as an input node (not labeled) for receiving input signal A3.

[0041] In some embodiments, at least one of the gate terminals of PFET transistor P3-L, NFET transistor N3-L, PFET transistor P3-R, or NFET transistor N3-R is coupled to another one of at least one of the gate terminals of PFET transistor P3-L, NFET transistor N3-L, PFET transistor P3-R, or NFET transistor N3-R.

[0042] The gate terminal of PFET transistor P4-L is configured as an input node (not labeled) for receiving input signal A4. The gate terminal of NFET transistor N4-L is configured as an input node (not labeled) for receiving input signal A4.

[0043] The gate terminal of PFET transistor P4-R is configured as an input node (not labeled) for receiving input signal A4. The gate terminal of NFET transistor N4-R is configured as an input node (not labeled) for receiving input signal A4.

[0044] In some embodiments, at least one of the gate terminals of PFET transistor P4-L, NFET transistor N4-L, PFET transistor P4-R, or NFET transistor N4-R is coupled to another one of at least one of the gate terminals of PFET transistor P4-L, NFET transistor N4-L, PFET transistor P4-R, or NFET transistor N4-R.

[0045] The source terminals of PFET transistor P4-L and PFET transistor P4-R are coupled to a voltage supply VDD. In some embodiments, the source terminal of PFET transistor P4-L is coupled together with the source terminal of PFET transistor P4-R.

[0046] The drain terminal of PFET transistor P4-L is coupled to the source terminal of PFET transistor P3-L. The drain terminal of PFET transistor P4-R is coupled to the source terminal of PFET transistor P3-R.

[0047] The drain terminal of PFET transistor P3-L is coupled to the source terminal of PFET transistor P2-L. The drain terminal of PFET transistor P3-R is coupled to the source terminal of PFET transistor P2-R.

[0048] The drain terminal of PFET transistor P2-L is coupled to the source terminal of PFET transistor P1-L. The drain terminal of PFET transistor P2-R is coupled to the source terminal of PFET transistor P1-R.

[0049] The source terminal of NFET transistor N1-L, the source terminal of NFET transistor N2-L, the source terminal of NFET transistor N3-L, the source terminal of NFET transistor N4-L, the source terminal of NFET transistor N1-R, the source terminal of NFET transistor N2-R, the source terminal of NFET transistor N3-R, and the source terminal of NFET transistor N4-R are each coupled to a reference voltage supply VSS.

[0050] In some embodiments, at least one of the source terminal of NFET transistor N1-L, the source terminal of NFET transistor N2-L, the source terminal of NFET transistor N3-L, the source terminal of NFET transistor N4-L, the source terminal of NFET transistor N1-R, the source terminal of NFET transistor N2-R, the source terminal of NFET transistor N3-R, or the source terminal of NFET transistor N4-R is coupled to at least one of the source terminal of NFET transistor N1-L, the source terminal of NFET transistor N2-L, the source terminal of NFET transistor N3-L, the source terminal of NFET transistor N4-L, the source terminal of NFET transistor N1-R, the source terminal of NFET transistor N2-R, the source terminal of NFET transistor N3-R, or the source terminal of NFET transistor N4-R.

[0051] The drain terminal of NFET transistor N1-L, the drain terminal of NFET transistor N2-L, the drain terminal of NFET transistor N3-L, the drain terminal of NFET transistor N4-L, the drain terminal of NFET transistor N1-R, the drain terminal of NFET transistor N2-R, the drain terminal of NFET transistor N3-R, the drain terminal of NFET transistor N4-R, the drain terminal of PFET transistor P1-L, and the drain terminal of PFET transistor P1-R are each coupled to each other and configured as an output node OUT.

[0052] Other circuits, other types of transistors, and / or other quantities of transistors are within the scope of various embodiments. For example, in some embodiments, integrated circuit 100 includes other types of NOR logic gate circuits, such as 4-11 NOR logic gates. Other values of at least input signals A1, A2, A3, or A4 are within the scope of various embodiments.

[0053] Figures 2A to 2B is a corresponding diagram of corresponding portions 200A to 200B of layout design 200 of corresponding integrated circuit 300 according to some embodiments.

[0054] Layout design 200 is Figure 1 the layout of the illustrated integrated circuit 100. Layout design 200 is Figures 3A to 3E the layout of the illustrated integrated circuit 300.

[0055] Portion 200A includes one or more features of layout design 200 of an active layer or an oxide diffusion (OD) layer, a gate (POLY) layer, a metal over diffusion (MD) layer, a metal over diffusion local interconnect (MDLI) layer, a metal 0 (M0) layer, a metal 1 (M1) layer, a via over gate (VG) layer, a via over diffusion (VD) layer, and a via over metal 0 (V0) layer.

[0056] Portion 200B includes one or more features of layout design 200 of an OD layer, a POLY layer, a backside metal over diffusion (BMD) layer, an MDLI layer, a backside metal 0 (BM0) layer, a backside via over gate (BVG) layer, and a backside via over diffusion (BVD) layer. In some embodiments, portion 200B further includes one or more features of layout design 200 of a backside metal 1 (BM1) layer or a backside via over metal 0 (BV0) layer.

[0057] Figures 2A to 2B is a corresponding diagram of corresponding portions 200A to 200B of layout design 200 (simplified for illustrative purposes).

[0058] For purposes of illustration, Figures 1 to 6D some of the marked components in one or more of the marked components in Figures 1 to 6D are not marked in one or more of Figures 2A to 2B In some embodiments, the layout design 200 includes additional components not shown in

[0059] The layout design 200 includes one or more features of an OD layer, a POLY layer, an MD layer, an MDLI layer, an M0 layer, a VG layer, a VD layer, an M1 layer, a V0 layer, a BMD layer, a BM0 layer, a BVG layer, and a BVD layer. In some embodiments, at least the layout design 200, or the integrated circuit 300, 400A, 400B, 500, or 600 includes Figures 2A to 2B , Figures 3A to 3E , Figures 5A to 5B or Figures 6A to 6D additional components not shown in

[0060] The layout design 200 can be used to fabricate Figures 3A to 3E the integrated circuit 300 shown in

[0061] Portion 200A is the layout of portion 300A of the integrated circuit 300 shown in Figure 3A and portion 200B is the layout of portion 300B of the integrated circuit 300 shown in Figure 3B and similar detailed descriptions are omitted for brevity.

[0062] The layout design 200 includes a cell 201. The cell 201 has cell boundaries 201a and 201b extending in a first direction X and cell boundaries 201c and 201d extending in a second direction Y. In some embodiments, at least one of the first direction X, the second direction Y, or the third direction Z is different from another of the first direction X, the second direction Y, or the third direction Z. In some embodiments, the layout design 200 is adjacent to other cell layout designs (not shown) along the cell boundaries 201c and 201d. In some embodiments, the layout design 200 is adjacent to other cell layout designs (not shown) along the cell boundaries 201a and 201b extending in the first direction X. In some embodiments, the layout design 200 is a single height standard cell. In some embodiments, the cell 201 can be used to fabricate a cell 301.

[0063] In some embodiments, the cell 201 is a standard cell, and the layout design 200 corresponds to the layout of a standard cell defined by the cell boundaries 201a, 201b, 201c, and 201d. In some embodiments, the cell 201 is a predefined portion of the layout design 200, the predefined portion including one or more transistors configured to perform one or more circuit functions and electrical connection portions. In some embodiments, the cell 201 is delimited by the cell boundaries 201a, 201b, 201c, and 201d, and thus corresponds to the area of a functional circuit component or device that is part of a standard cell. In some embodiments, the layout design 200 is the layout design of a memory cell (e.g., Figure 2A the memory cell 200A shown or Figure 2B the memory cell 200B shown).

[0064] The layout design 200 includes an active region layout pattern 202a (collectively referred to as the "active region pattern group 202") or an active region layout pattern 204a (collectively referred to as the "active region pattern group 204") that extends in a first direction X.

[0065] Embodiments of the present invention use the term "layout pattern". For the sake of brevity, in the remainder of the present invention, the term "layout pattern" is also referred to as "pattern" hereinafter.

[0066] The active region pattern group 202 is located above the active region pattern group 204.

[0067] Each active region pattern of the active region pattern group 202 is separated from each other in a second direction Y. Each active region pattern of the active region pattern group 204 is separated from each other in the second direction Y.

[0068] The active region patterns 202a and 204a are separated from each other in a third direction Z.

[0069] The active region pattern group 202 can be used to fabricate the corresponding active region group 302 of the integrated circuits 100, 300, 400A, 400B, 500, or 600. The active region pattern 204 can be used to fabricate the corresponding active region group 304 of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0070] In some embodiments, at least one of the active region groups 302 or 304 is located on the front side 303a of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, at least one of the active region groups 302 or 304 corresponds to the source regions and drain regions of one or more complementary FET (CFET) transistors. In some embodiments, at least one of the active region groups 302 or 304 corresponds to the source regions and drain regions of one or more nanosheet transistors or nanowire transistors. Other transistor types are within the scope of the present utility model. In some embodiments, at least one of the active region groups 302 or 304 corresponds to the source regions and drain regions of one or more fin-type field effect transistors (finFETs).

[0071] In some embodiments, the active region pattern 202a can be used to fabricate the corresponding active region 302a of the active region group 302 of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the active region pattern 204a can be used to fabricate the corresponding active region 304a of the active region group 304 of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0072] In some embodiments, the active region pattern groups 202 and 204 are referred to as oxide diffusion (OD) regions, which define the source diffusion regions or drain diffusion regions of at least the integrated circuits 100, 300, 400A, 400B, 500, or 600 or the layout design 200.

[0073] In some embodiments, the active region pattern 202a can be used to fabricate the source regions and drain regions of the NFET transistors of the integrated circuits 100, 300, 400A, 400B, 500, or 600, and the active region pattern 204a can be used to fabricate the source regions and drain regions of the PFET transistors of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0074] In some embodiments, the active region pattern 202a can be used to fabricate the source regions and drain regions of the PFET transistors of the integrated circuits 100, 300, 400A, 400B, 500, or 600, and the active region pattern 204a can be used to fabricate the source regions and drain regions of the NFET transistors of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0075] In some embodiments, the active region pattern sets 202 or 204 are located on the first layout level. In some embodiments, the first layout level corresponds to the active level or the OD level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the OD level is located above the BM0 level and the BM1 level.

[0076] Other layout levels or other configurations and arrangements of the number of patterns in the active region pattern sets 202 or 204 are within the scope of the present utility model.

[0077] The layout design 200 further includes one or more gate patterns 206a, 206b, 206c, 206d, 206e, 206f, 206g, 206h, 206i, or 206j (collectively referred to as "gate pattern set 206") extending in the second direction Y, and one or more gate patterns 208a, 208b, 208c, 208d, 208e, 208f, 208g, 208h, 208i, or 208j (collectively referred to as "gate pattern set 208").

[0078] The gate pattern set 206 is located above the gate pattern set 208.

[0079] Each gate pattern in the gate pattern set 206 is separated from each other in the first direction X. Each gate pattern in the gate pattern set 208 is separated from each other in the first direction X.

[0080] In some embodiments, each gate pattern in the gate pattern set 206 is separated from the corresponding gate pattern in the gate pattern set 208 in the third direction Z.

[0081] The gate pattern set 206 can be used to fabricate the corresponding gate set 306 of the integrated circuits 100, 300, 400A, 400B, 500, or 600. The gate pattern set 208 can be used to fabricate the corresponding gate set 308 of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0082] In some embodiments, the gate patterns 206a, 206b, 206c, 206d, 206e, 206f, 206g, 206h, 206i, or 206j may be used to fabricate the corresponding gates 306a, 306b, 306c, 306d, 306e, 306f, 306g, 306h, 306i, or 306j of the gate stack 306 of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the gate patterns 208a, 208b, 208c, 208d, 208e, 208f, 208g, 208h, 208i, or 208j may be used to fabricate the corresponding gates 308a, 308b, 308c, 308d, 308e, 308f, 308g, 308h, 308i, or 308j of the gate stack 308 of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0083] In some embodiments, at least one of the gate patterns 206a or 206j is a corresponding dummy gate pattern. In some embodiments, at least one of the gate patterns 208a or 208j is a corresponding dummy gate pattern. In some embodiments, the dummy gate pattern is also referred to as a continuous poly over diffusion edge (CPODE) pattern. In some embodiments, at least one of the gate patterns 206a or 206j overlaps with the corresponding cell boundary 201c or 201d. In some embodiments, at least one of the gate patterns 208a or 208j overlaps with the corresponding cell boundary 201c or 201d. Other gate patterns configured as dummy gates are within the scope of the present invention.

[0084] In some embodiments, at least one of the gate stacks 306 or 308 is located on the front side 303a of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0085] In some embodiments, each of the gate patterns in the gate pattern sets 206 and 208 is Figures 3A to 3B shown in with the labels "P1-L, P2-L, P3-L, P4-L, P1-R, P2-R, P3-R, P4-R, N1-L, N2-L, N3-L, N4-L, N1-R, N2-R, N3-R, and N4-R", and the labels identify the Figures 2A to 2B corresponding transistors fabricated from the corresponding gate patterns in and are omitted for brevity. Figure 1

[0086] In some embodiments, the gate pattern groups 206 or 208 encapsulate the active region pattern groups 202 and 204. In some embodiments, a portion of the gate pattern groups 206 or 208 is located above the active region pattern groups 202 and 204. In some embodiments, another portion of the gate pattern groups 206 or 208 is located below the active region pattern groups 202 and 204.

[0087] The gate pattern groups 206 or 208 are located on a second layout level. In some embodiments, the second layout level is different from the first layout level. In some embodiments, the second layout level corresponds to the POLY level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the POLY level is located above the BMD level and the BM0 level.

[0088] Other layout levels or other configurations and arrangements of the patterns in the gate pattern groups 206 or 208 are within the scope of the present invention.

[0089] The layout design 200 further includes one or more contact patterns 210a, 210b, 210c, 210d, 210e, 210f, 210g, 210h, or 210i (collectively referred to as "contact pattern group 210") extending in the second direction Y.

[0090] Each of the contact patterns in the contact pattern group 210 is separated from an adjacent contact pattern in the contact pattern group 210 in at least the first direction X.

[0091] The contact pattern group 210 can be used to fabricate the corresponding contact group 310 of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0092] In some embodiments, the contact patterns 210a, 210b, 210c, 210d, 210e, 210f, 210g, 210h, or 210i of the contact pattern group 210 can be used to fabricate the corresponding contacts 310a, 310b, 310c, 310d, 310e, 310f, 310g, 310h, or 310i of the contact group 310. In some embodiments, the contact pattern group 210 is also referred to as a metal on diffusion (MD) pattern.

[0093] In some embodiments, at least one of the contact patterns 210a, 210b, 210c, 210d, 210e, 210f, 210g, 210h, or 210i of the contact pattern group 210 can be used to fabricate a source terminal or a drain terminal of one of the NFET transistors or PFET transistors of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0094] In some embodiments, the contact pattern 210a can be used to fabricate the drain terminal of the NFET transistor N2-L, the contact pattern 210c can be used to fabricate the drain terminals of the NFET transistors N1-L and N1-R, the contact pattern 210e can be used to fabricate the drain terminals of the NFET transistors N2-R and N3-R, the contact pattern 210g can be used to fabricate the drain terminals of the NFET transistors N4-R and N4-L, and the contact pattern 210i can be used to fabricate the drain terminal of the NFET transistor N3-L.

[0095] In some embodiments, the contact pattern 210b can be used to fabricate the source terminals of the NFET transistors N2-L and N1-L, the contact pattern 210d can be used to fabricate the source terminals of the NFET transistors N1-R and N2-R, the contact pattern 210f can be used to fabricate the source terminals of the NFET transistors N3-R and N4-R, and the contact pattern 210h can be used to fabricate the source terminals of the NFET transistors N4-L and N3-L.

[0096] In some embodiments, the contact pattern group 210 overlaps with the active region pattern group 202 or 204. The contact pattern 210 is located on the third layout level. In some embodiments, the third layout level corresponds to the contact level or the MD level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the third layout level is different from at least one of the first layout level or the second layout level. Other configurations or arrangements of other layout levels or quantities of the patterns in the contact pattern group 210 are within the scope of the present invention.

[0097] The layout design 200 further includes one or more contact patterns 212a, 212b, 212c, 212d, 212e, 212f, 212g, 212h, or 212i (collectively referred to as "contact pattern group 212") extending in the second direction Y.

[0098] Each of the contact patterns in the contact pattern group 212 is separated from an adjacent contact pattern in the contact pattern group 212 in at least the first direction X.

[0099] The contact pattern sets 210 and 212 are separated from each other in the third direction Z. In some embodiments, the contact patterns 210a and 212a are separated from each other in the third direction Z. In some embodiments, the contact patterns 210b and 212b are separated from each other in the third direction Z. In some embodiments, the contact patterns 210d and 212d are separated from each other in the third direction Z. In some embodiments, the contact patterns 210e and 212e are separated from each other in the third direction Z. In some embodiments, the contact patterns 210f and 212f are separated from each other in the third direction Z. In some embodiments, the contact patterns 210g and 212g are separated from each other in the third direction Z. In some embodiments, the contact patterns 210h and 212h are separated from each other in the third direction Z. In some embodiments, the contact patterns 210i and 212i are separated from each other in the third direction Z. In some embodiments, the contact patterns 210c and 212c are separated from each other in the third direction Z.

[0100] The contact pattern set 212 can be used to fabricate a corresponding contact set 312 of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0101] In some embodiments, the contact patterns 212a, 212b, 212c, 212d, 212e, 212f, 212g, 212h, or 212i of the contact pattern set 212 can be used to fabricate the corresponding contacts 312a, 312b, 312c, 312d, 312e, 312f, 312g, 312h, or 312i of the contact set 312. In some embodiments, the contact set 312 is located on the front side 303a of the integrated circuit 300. In some embodiments, the back side 303b of the integrated circuit 300 is opposite to the front side of the integrated circuit 300. In some embodiments, the contact pattern set 212 is also referred to as the backside MD (BMD) pattern set.

[0102] In some embodiments, at least one of the contact patterns 212a, 212b, 212c, 212d, 212e, 212f, 212g, 212h, or 212i of the contact pattern set 212 can be used to fabricate a source terminal or a drain terminal of one of the NFET transistors or PFET transistors of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0103] In some embodiments, the contact pattern 212a can be used to fabricate the source terminal of the PFET transistor P2-L, the contact pattern 212b can be used to fabricate the drain terminal of the PFET transistor P2-L and the source terminal of the PFET transistor P1-L, the contact pattern 212c can be used to fabricate the drain terminal of the PFET transistor P1-L and the drain terminal of the PFET transistor P1-R, the contact pattern 212d can be used to fabricate the source terminal of the PFET transistor P1-R and the drain terminal of the PFET transistor P2-R, the contact pattern 212e can be used to fabricate the source terminal of the PFET transistor P2-R and the drain terminal of the PFET transistor P3-R, the contact pattern 212f can be used to fabricate the source terminal of the PFET transistor P3-R and the drain terminal of the PFET transistor P4-R, the contact pattern 212g can be used to fabricate the source terminal of the PFET transistor P4-R and the source terminal of the PFET transistor P4-L, the contact pattern 212h can be used to fabricate the drain terminal of the PFET transistor P4-L and the source terminal of the PFET transistor P3-L, and the contact pattern 212i can be used to fabricate the drain terminal of the PFET transistor P3-L.

[0104] In some embodiments, the contact pattern group 212 overlaps with the active region pattern group 202 or 204. The contact pattern group 212 is located on the fourth layout level. In some embodiments, the fourth layout level corresponds to the back contact level or the backside MD (BMD) level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the fourth layout level is different from at least one of the first layout level, the second layout level, or the third layout level.

[0105] In some embodiments, the BMD level is above the BM0 level. In some embodiments, the BMD level is above the backside 303b of the integrated circuit 300. In some embodiments, the BMD level is below the OD level, the POLY level, the MD level, and the M0 level.

[0106] Other layout levels or other configurations and arrangements of the patterns in the contact pattern group 212 are within the scope of the present invention.

[0107] The layout design 200 further includes contact patterns 214a (collectively referred to as "contact pattern group 214") extending in the second direction Y.

[0108] Each of the contact patterns in the contact pattern group 214 is separated from an adjacent contact pattern in the contact pattern group 214 in at least the first direction X or the second direction Y.

[0109] In some embodiments, the contact pattern group 214 is located between the contact pattern groups 210 and 212. The contact pattern 214a is located between the contact patterns 210c and 212c.

[0110] In some embodiments, the contact pattern 214a includes one or more separate discontinuous patterns.

[0111] The contact pattern group 214 can be used to fabricate the corresponding contact group 314 of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0112] In some embodiments, the contact pattern 214a of the contact pattern group 214 can be used to fabricate the corresponding contact 314a of the contact group 314. In some embodiments, the contact 314 is located on the front side 303a of the integrated circuit 300. In some embodiments, the contact pattern group 214 is also referred to as a group of local in-line (MDLI) patterns.

[0113] In some embodiments, at least one contact pattern 214a of the contact pattern group 214 can be used to fabricate an in-line structure that can be used to connect to the source or drain terminal of one of the NFET transistors or PFET transistors of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0114] In some embodiments, the contact pattern 214a can be used to fabricate the drain terminals of the NFET transistor N1-L, the NFET transistor N1-R, the PFET transistor P1-L, and the PFET transistor P1-R.

[0115] In some embodiments, at least a first portion of the contact pattern group 214 overlaps with one or more of the active region pattern groups 202 or 204. In some embodiments, at least a second portion of the contact pattern group 214 is located between the active region pattern groups 202 or 204. In some embodiments, at least a third portion of the contact pattern group 214 is coplanar with the contact pattern group 210 or the contact pattern group 212.

[0116] The contact pattern group 214 is located on the fifth layout level. In some embodiments, the fifth layout level corresponds to the MDLI level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the fifth layout level is different from at least one of the first layout level or the second layout level.

[0117] In some embodiments, the MDLI hierarchy includes an MD hierarchy and a BMD hierarchy. In some embodiments, the MDLI hierarchy is located below the M0 hierarchy. In some embodiments, the MDLI hierarchy is located above the BM0 hierarchy.

[0118] Other configurations and arrangements of other layout levels or numbers of patterns in the contact pattern group 214 are within the scope of the present invention.

[0119] The layout design 200 further includes one or more conductive feature patterns 230a, 230b, 230c, 230d, 230e (collectively referred to as the "conductive feature pattern group 230") extending in the first direction X.

[0120] Each conductive feature pattern in the conductive feature pattern group 230 is separated from another conductive feature pattern in the conductive feature pattern group 230 in the first direction X or the second direction Y.

[0121] The conductive feature pattern group 230 overlaps with at least one of the active region pattern groups 202 or 204, the gate pattern groups 206 or 208, or the contact pattern groups 210, 212, or 214.

[0122] The conductive feature pattern group 230 can be used to fabricate the corresponding conductor group 330 of the integrated circuits 100, 300, 400A, 400B, 500, or 600. The conductive feature patterns 230a, 230b, 230c, 230d, 230e can be used to fabricate the corresponding conductors 330a, 330b, 330c, 330d, 330e of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, at least one conductor of the conductor group 330 is located on the front side 303a of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0123] In some embodiments, the conductive feature pattern group 230 is located on the sixth layout level. In some embodiments, the sixth layout level is different from at least one of the first layout level, the second layout level, the third layout level, the fourth layout level, or the fifth layout level. In some embodiments, the sixth layout level corresponds to the M0 level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the M0 level is located above the OD level, the POLY level, the MD level, the BMD level, and the BM0 level.

[0124] In some embodiments, the conductive feature pattern group 230 corresponds to 2 M0 routing tracks. Other numbers of M0 routing tracks are within the scope of the present invention.

[0125] Other configurations or arrangements regarding other layout levels or quantities of the patterns in the conductive feature pattern group 230 are within the scope of the present utility model.

[0126] Other M0 path allocations are within the scope of the present utility model.

[0127] The layout design 200 further includes one or more conductive feature patterns 232a, 232b, 232c (collectively referred to as "conductive feature pattern group 232") extending in the first direction X.

[0128] Each conductive feature pattern in the conductive feature pattern group 232 is separated from another conductive feature pattern in the conductive feature pattern group 232 in the first direction X or the second direction Y.

[0129] The conductive feature pattern group 232 overlaps with at least one of the active region pattern groups 202 or 204, the gate pattern groups 206 or 208, or the contact pattern groups 210, 212, or 214.

[0130] The conductive feature pattern groups 230 and 232 are separated from each other in the third direction Z. In some embodiments, the conductive feature patterns 230e and 232a are separated from each other in the third direction Z.

[0131] The conductive feature pattern group 232 can be used to fabricate the corresponding conductor group 332 of the integrated circuits 100, 300, 400A, 400B, 500, or 600. The conductive feature patterns 232a, 232b, 232c can be used to fabricate the corresponding conductors 332a, 332b, 332c of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, at least one conductor of the conductor group 332 is located on the back side 303b of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0132] In some embodiments, the conductive feature pattern group 232 is located on the seventh layout level. In some embodiments, the seventh layout level is different from at least one of the first layout level, the second layout level, the third layout level, the fourth layout level, the fifth layout level, or the sixth layout level. In some embodiments, the seventh layout level corresponds to the BM0 level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the BM0 level is located below the OD level, the POLY level, the MD level, the BMD level, and the BM1 level.

[0133] In some embodiments, the conductive feature pattern group 232 corresponds to 2 BM0 routing paths. Other numbers of BM0 routing paths are within the scope of the present utility model.

[0134] Other BM0 path assignments are within the scope of the present invention.

[0135] Other configurations and arrangements of other layout levels or quantities of the patterns in the conductive feature pattern group 232 are within the scope of the present invention.

[0136] The layout design 200 further includes one or more power rail feature patterns 236a, 236b (collectively referred to as "power rail pattern group 236") extending in the first direction X.

[0137] Each power rail feature pattern in the power rail pattern group 236 is separated from another power rail feature pattern in the power rail pattern group 236 in the first direction X or the second direction Y.

[0138] The power rail pattern group 236 overlaps with at least one of the active region pattern groups 202 or 204, the gate pattern groups 206 or 208, or the contact pattern groups 210, 212, or 214.

[0139] The power rail pattern group 236 can be used to fabricate the corresponding power rail group 336 of the integrated circuits 100, 300, 400A, 400B, 500, or 600. The power rail patterns 236a, 236b can be used to fabricate the corresponding power rails 336a, 336b of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0140] In some embodiments, the power rail 336a of the power rail group 336 is located on the front side 303a of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the power rail 336b of the power rail group 336 is located on the back side 303b of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0141] In some embodiments, the power rail pattern group 236 is located on the sixth layout level or the seventh layout level. In some embodiments, the power rail pattern 236a of the power rail pattern group 236 is located on the sixth layout level. In some embodiments, the power rail pattern 236b of the power rail pattern group 236 is located on the seventh layout level.

[0142] Other configurations and arrangements of other layout levels or quantities of the patterns in the power rail pattern group 236 are within the scope of the present invention.

[0143] The layout design 200 further includes one or more via patterns 220a, 220b, 220c, 220d (collectively referred to as "via pattern group 220").

[0144] The via pattern group 220 can be used to fabricate corresponding via groups 320 of integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the via patterns 220a, 220b, 220c, 220d, 220e of the via pattern group 220 can be used to fabricate corresponding vias 320a, 320b, 320c, 320d, 320e of the group of vias 320 of integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0145] In some embodiments, the via pattern group 220 is located between at least the contact pattern group 210 or 214 and the conductive feature pattern group 230. The via pattern 220a is located between the contact pattern 210a and the conductive feature pattern 230e. The via pattern 220b is located between at least the contact pattern 210c or 214a and the conductive feature pattern 230e. The via pattern 220c is located between the contact pattern 210e and the conductive feature pattern 230e. The via pattern 220d is located between the contact pattern 210g and the conductive feature pattern 230e. The via pattern 220e is located between the contact pattern 210i and the conductive feature pattern 230e.

[0146] The via pattern group 220 is located at the diffusion via (VD) level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the VD level is above the OD level, POLY level, MD level, BMD level, and BM0 level. In some embodiments, the VD level is below the M0 level. In some embodiments, the VD level is between the MD level and the M0 level. In some embodiments, the VD level is at least between the third layout level or the fifth layout level and the sixth layout level. Other layout levels are within the scope of the present invention.

[0147] Other configurations or arrangements of other layout levels or the number of patterns in at least the via pattern group 220 are within the scope of the present invention.

[0148] The layout design 200 further includes one or more via patterns 222a, 222b (collectively referred to as "via pattern group 222").

[0149] The via pattern group 222 can be used to fabricate corresponding via groups 322 of integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the via patterns 222a, 222b of the via pattern group 222 can be used to fabricate corresponding vias 322a, 322b of the via group 322 of integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0150] In some embodiments, the via pattern group 222 is located between at least the contact pattern group 212 or 214 and the conductive feature pattern group 232. The via pattern 222a is located between the contact pattern 212a and the conductive feature pattern 232a. The via pattern 222b is located between the contact pattern 212i and the conductive feature pattern 232a.

[0151] The via pattern group 222 is located at the backside via diffusion (BVD) level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the BVD level is below the OD level, POLY level, MD level, BMD level, and M0 level. In some embodiments, the BVD level is above the BM0 level and the BM1 level. In some embodiments, the BVD level is between the BMD level and the BM0 level. In some embodiments, the BVD level is between at least the fourth layout level or the fifth layout level and the seventh layout level. Other layout levels are within the scope of the present invention.

[0152] Other layout levels or other configurations and arrangements of the number of the via pattern group 222 are within the scope of the present invention.

[0153] The layout design 200 further includes one or more via patterns 224a, 224b, 224c, 224d, 224e, 224f (collectively referred to as "via pattern group 224").

[0154] The via pattern group 224 can be used to fabricate the corresponding via group 324 of the integrated circuit 100, 300, 400A, 400B, 500, or 600. In some embodiments, the via patterns 224a, 224b, 224c, 224d, 224e, 224f of the via pattern group 224 can be used to fabricate the corresponding vias 324a, 324b, 324c, 324d, 324e, 324f of the via group 324 of the integrated circuit 100, 300, 400A, 400B, 500, or 600.

[0155] In some embodiments, the via pattern group 224 is located between the gate pattern group 206 and the conductive feature pattern group 230. The via pattern 224a is located between the gate pattern 206b and the conductive feature pattern 230a. The via pattern 224b is located between the gate pattern 206c and the conductive feature pattern 230b. The via pattern 224c is located between the gate pattern 206d and the conductive feature pattern 230b. The via pattern 224d is located between the gate pattern 206g and the conductive feature pattern 230c. The via pattern 224e is located between the gate pattern 206h and the conductive feature pattern 230c. The via pattern 224f is located between the gate pattern 206i and the conductive feature pattern 230d.

[0156] The via pattern group 224 is located at the via gate (VG) level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the VG level is above the OD level, POLY level, MD level, MDLI level, BMD level, BM0 level, and BM1 level. In some embodiments, the VG level is below the M0 level and M1 level. In some embodiments, the VG level is between the POLY level and the M0 level. In some embodiments, the VG level is between the second layout level and the sixth layout level. Other layout levels are within the scope of the present invention.

[0157] Other configurations or arrangements of other layout levels or the number of patterns in at least the via pattern group 224 are within the scope of the present invention.

[0158] The layout design 200 further includes one or more via patterns 226a, 226b, 226c, 226d (collectively referred to as "via pattern group 226").

[0159] The via pattern group 226 can be used to fabricate the corresponding via group 326 of the integrated circuit 100, 300, 400A, 400B, 500, or 600. In some embodiments, the via patterns 226a, 226b, 226c, 226d of the via pattern group 226 can be used to fabricate the corresponding vias 326a, 326b, 326c, 326d of the via group 326 of the integrated circuit 100, 300, 400A, 400B, 500, or 600.

[0160] In some embodiments, the via pattern group 226 is located between the gate pattern group 208 and the conductive feature pattern group 232. The via pattern 226a is located between the gate pattern 208b and the conductive feature pattern 232b. The via pattern 226b is located between the gate pattern 208e and the conductive feature pattern 232b. The via pattern 226c is located between the gate pattern 208f and the conductive feature pattern 232c. The via pattern 226d is located between the gate pattern 208i and the conductive feature pattern 232c.

[0161] The via pattern group 226 is located at the backside via gate (BVG) level on the gate of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the BVG level is below the OD level, POLY level, MD level, MDLI level, BMD level, M0 level, and M1 level. In some embodiments, the BVG level is above the BM0 level and BM1 level. In some embodiments, the BVG level is between the POLY level and the BM0 level. In some embodiments, the BVG level is between the second layout level and the seventh layout level. Other layout levels are within the scope of the present invention.

[0162] Other configurations and arrangements of other layout levels or the number of patterns in at least the via pattern group 226 are within the scope of the present invention.

[0163] The layout design 200 further includes one or more conductive feature patterns 250a, 250b, 250c, 250d, 250e (collectively referred to as "conductive feature pattern group 250") extending in the second direction Y.

[0164] Each conductive feature pattern in the conductive feature pattern group 250 is separated from another conductive feature pattern in the conductive feature pattern group 250 in the first direction X.

[0165] The conductive feature pattern group 250 overlaps with at least one of the active region pattern groups 202 or 204, gate pattern groups 206 or 208, contact pattern groups 210, 212, or 214, or conductive feature pattern groups 230 or 232.

[0166] The conductive feature pattern group 250 can be used to fabricate the corresponding conductor group 350 of the integrated circuits 100, 300, 400A, 400B, 500, or 600. The conductive feature patterns 250a, 250b, 250c, 250d, 250e can be used to fabricate the corresponding conductors 350a, 350b, 350c, 350d, 350e of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, at least one conductor of the conductor group 350 is located on the front side 303a of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0167] In some embodiments, the conductive feature pattern set 250 is located on the eighth layout level. In some embodiments, the eighth layout level is different from at least one of the first layout level, the second layout level, the third layout level, the fourth layout level, the fifth layout level, the sixth layout level, or the seventh layout level. In some embodiments, the eighth layout level corresponds to the M1 level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the M1 level is above the OD level, the POLY level, the MD level, the M0 level, the BMD level, the BM0 level, and the BM1 level.

[0168] In some embodiments, the conductive feature pattern set 250 corresponds to 5 M1 wiring paths. Other numbers of M1 wiring paths are within the scope of the present invention.

[0169] Other layout levels or other configurations and arrangements of the number of patterns in the conductive feature pattern set 250 are within the scope of the present invention.

[0170] In some embodiments, the layout design 200 further includes one or more conductive feature patterns similar to the conductor group 552 extending in the second direction Y ( Figure 5B ).

[0171] Each conductive feature pattern similar to the conductor 552a in the conductor group 552 is separated from another conductive feature pattern similar to the conductor group 552 in the first direction X.

[0172] The conductive feature pattern set similar to the conductor group 552 overlaps with at least one of the active region pattern sets 202 or 204, the gate pattern sets 206 or 208, the contact pattern sets 210, 212, or 214, the conductive feature pattern sets 230 or 232, or the conductive feature pattern set 250.

[0173] The conductive feature pattern set similar to the conductor group 552 can be used to fabricate a corresponding conductor group similar to the conductor group 552 of the integrated circuit 300.

[0174] In some embodiments, the conductive feature pattern set similar to the conductor group 552 is located on the ninth layout level. In some embodiments, the ninth layout level is different from at least one of the first layout level, the second layout level, the third layout level, the fourth layout level, the fifth layout level, the sixth layout level, the seventh layout level, or the eighth layout level. In some embodiments, the ninth layout level corresponds to the BM1 level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the BM1 level is below the OD level, the POLY level, the MD level, the BMD level, and the BM0 level.

[0175] Other configurations or arrangements of other layout levels or quantities of patterns in a group of conductive feature patterns similar to the conductor group 552 are within the scope of the present utility model.

[0176] The layout design 200 further includes one or more via patterns 240a, 240b, 240c, 240d, 240e (collectively referred to as "via pattern group 240").

[0177] The via pattern group 240 can be used to fabricate corresponding via groups 340 of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the via patterns 240a, 240b, 240c, 240d, 240e of the via pattern group 240 can be used to fabricate corresponding vias 340a, 340b, 340c, 340d, 340e of the via group 340 of the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0178] In some embodiments, the via pattern group 240 is located between the conductive feature pattern group 230 and the conductive feature pattern group 250. The via pattern 240a is located between the conductive feature pattern 230a and the conductive feature pattern 250a. The via pattern 240b is located between the conductive feature pattern 230b and the conductive feature pattern 250b. The via pattern 240c is located between the conductive feature pattern 230e and the conductive feature pattern 250c. The via pattern 240d is located between the conductive feature pattern 230c and the conductive feature pattern 250d. The via pattern 240e is located between the conductive feature pattern 230d and the conductive feature pattern 250e.

[0179] The via pattern group 240 is located at the M0 via (V0) level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the V0 level is above the OD level, POLY level, MD level, M0 level, BMD level, BM0 level, and BM1 level. In some embodiments, the V0 level is below the M1 level. In some embodiments, the V0 level is between the M0 level and the M1 level. In some embodiments, the V0 level is between the sixth layout level and the eighth layout level. Other layout levels are within the scope of the present utility model.

[0180] Other configurations or arrangements of other layout levels or quantities of patterns in at least the via pattern group 240 are within the scope of the present utility model.

[0181] In some embodiments, the layout design 200 further includes one or more via patterns similar to the via group 542 ( Figure 5B ).

[0182] In some embodiments, a via pattern group similar to via group 542 is located between the conductive feature pattern group 232 and a conductive feature pattern group similar to conductor group 552.

[0183] A via pattern group similar to via group 542 is located at the via (BV0) level on BM0 of layout design 200 or one or more of integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the BV0 level is below the OD level, POLY level, MD level, M0 level, M1 level, BMD level, and BM0 level. In some embodiments, the BV0 level is above the BM1 level. In some embodiments, the BV0 level is between the BM0 level and the BM1 level. In some embodiments, the BV0 level is between the seventh layout level and the ninth layout level. Other layout levels are within the scope of the present invention.

[0184] Other configurations or arrangements of other layout levels or numbers of patterns in at least the via pattern group similar to via group 542 are within the scope of the present invention.

[0185] In some embodiments, by positioning via patterns 224a and 226a between corresponding conductive feature patterns 230a and 232b and corresponding gate patterns 206b and 208b, layout design 200 can be used to fabricate integrated circuit 300 in which the front and back sides of integrated circuit 300 can be electrically connected together, and the conductive feature pattern group 232 can be used as additional wiring resources on the BM0 metallization level, such that layout design 200 has at least one of a reduced pitch, a smaller area, or a smaller standard cell compared to other methods.

[0186] In some embodiments, by positioning via patterns 224f and 226d between corresponding conductive feature patterns 230d and 232c and corresponding gate patterns 206i and 208i, layout design 200 can be used to fabricate integrated circuit 300 in which the front and back sides of integrated circuit 300 can be electrically connected together, and the conductive feature pattern group 232 can be used as additional wiring resources on the BM0 metallization level, such that layout design 200 has at least one of a reduced pitch, a smaller area, or a smaller standard cell compared to other methods.

[0187] Other configurations or arrangements of other layout levels or numbers of patterns in layout design 200 are within the scope of the present invention.

[0188] Figures 3A to 3E is a diagram of integrated circuit 300 according to some embodiments.

[0189] Figures 3A to 3BIt is a corresponding diagram (simplified for illustrative purposes) of corresponding parts 300A to 300B of integrated circuit 300.

[0190] Part 300A includes one or more features of integrated circuit 300 at the OD level, POLY level, MD level, MDLI level, M0 level, M1 level, VG level, VD level, and V0 level. Part 300A is fabricated from part 200A.

[0191] Part 300B includes one or more features of integrated circuit 300 at the OD level, POLY level, BMD level, MDLI level, BM0 level, BVG level, and BVD level. Part 300B is fabricated from part 200B. In some embodiments, part 300B further includes one or more features of integrated circuit 300 at the BM1 level or BV0 level.

[0192] Figures 3C to 3E It is a corresponding cross-sectional view of integrated circuit 300 according to some embodiments. Figure 3C It is a cross-sectional view of integrated circuit 300 cut by plane A - A′ according to some embodiments. Figure 3D It is a cross-sectional view of integrated circuit 300 cut by plane B - B′ according to some embodiments. Figure 3E It is a cross-sectional view of integrated circuit 300 cut by plane C - C′ according to some embodiments.

[0193] is the same as Figure 1 , Figures 2A to 2B , Figures 3A to 3E , Figures 4A to 4B , Figures 5A to 5B and Figures 6A to 6D Components that are the same or similar to those in one or more of

[0194] Integrated circuit 300 is fabricated from layout design 200. Integrated circuit 300 is cell 301. The structural relationships, including alignment, length, and width, as well as the configuration and layers of integrated circuits 300, 500, and 600 are similar to Figures 2A to 2B the structural relationships, as well as the configuration and layers of the layout design 200 shown, and for the sake of brevity, similar detailed descriptions will not be elaborated at least in Figures 3A to 3E For example, in some embodiments, at least one or more widths, lengths, or pitches of the layout design 200 are similar to the corresponding widths, lengths, or pitches of integrated circuits 300, 500, and 600, and similar detailed descriptions are omitted for the sake of brevity. For example, in some embodiments, at least cell boundaries 201a or 201b are similar to at least the corresponding cell boundaries 301a or 301b of integrated circuit 300, and similar detailed descriptions are omitted for the sake of brevity.

[0195] Integrated circuit 300 includes at least active region groups 302 and 304, gate groups 306 and 308, contact groups 310, contact groups 312, contact groups 314, conductor groups 330, conductor groups 332, power rail groups 336, via groups 320, via groups 322, via groups 324, via groups 326, conductor groups 350, via groups 340, substrate 390, and insulating regions 392.

[0196] Active region groups 302 and 304 are embedded in substrate 390. Substrate 390 has a front side 303a and a back side 303b opposite to the front side 303a. In some embodiments, at least active region groups 302 and 304, gate groups 306 and 308, or contact groups 310, 312, and 314 are formed in the front side 303a of substrate 390.

[0197] In some embodiments, active region groups 302 and 304 correspond to the active regions of CFET transistors. In some embodiments, active region groups 302 and 304 correspond to the nanosheet structures (not labeled) of nanosheet transistors. In some embodiments, active region group 302 or 304 includes drain regions and source regions grown by an epitaxial growth process. In some embodiments, active region group 302 or 304 includes drain regions and source regions grown with epitaxial materials at the corresponding drain regions and source regions.

[0198] Other transistor types are within the scope of the present utility model. For example, in some embodiments, active region group 302 or 304 corresponds to the nanowire structure (not shown) of a nanowire transistor. In some embodiments, active region group 302 or 304 corresponds to the planar structure (not shown) of a planar transistor. In some embodiments, active region group 302 or 304 corresponds to the fin structure (not shown) of a finFET.

[0199] In some embodiments, active region 302a corresponds to the source region and drain region of an NFET transistor of integrated circuits 100, 300, 400A, 400B, 500, or 600, and active region 304a corresponds to the source region and drain region of a PFET transistor of integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0200] In some embodiments, active region 302a corresponds to the source region and drain region of a PFET transistor of integrated circuits 100, 300, 400A, 400B, 500, or 600, and active region 304a corresponds to the source region and drain region of an NFET transistor of integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0201] In some embodiments, at least the active region 302a is an N-type doped S / D region, and at least the active region 304a is a P-type doped S / D region embedded in the dielectric material of the substrate 390. In some embodiments, at least the active region 302a is a P-type doped S / D region, and at least the active region 304a is an N-type doped S / D region embedded in the dielectric material of the substrate 390.

[0202] Other configurations and arrangements of other layout levels or numbers of structures in the active region groups 302 or 304 are within the scope of the present invention.

[0203] The insulating region 392 is configured to electrically isolate one or more components of the active region groups 302 and 304, the gate groups 306 and 308, the contact groups 310, 312, 314, the conductor groups 330, 332, the power rail group 336, the via groups 320, 322, 324, 326, the conductor group 350, and the via group 340 from each other. In some embodiments, the insulating region 392 includes a plurality of insulating regions deposited at different times during the methods 700A to 700B ( Figures 7A to 7B ). In some embodiments, the insulating region 392 is a dielectric material. In some embodiments, the dielectric material includes silicon dioxide, silicon oxynitride, or similar materials.

[0204] Other configurations and arrangements of other layout levels or other numbers of some portions in the insulating region 392 are within the scope of the present invention.

[0205] The gate groups 306 and 308 correspond to one or more gates of the transistors P1-L, P2-L, P3-L, P4-L, P1-R, P2-R, P3-R, P4-R, N1-L, N2-L, N3-L, N4-L, N1-R, N2-R, N3-R, and N4-R of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, each of the gates in the gate groups 306 and 308 is Figures 3A to 3C shown in with the labels "P1-L, P2-L, P3-L, P4-L, P1-R, P2-R, P3-R, P4-R, N1-L, N2-L, N3-L, N4-L, N1-R, N2-R, N3-R, and N4-R", and the labels identify the Figures 3A to 3E corresponding gates in and Figures 2A to 2B the corresponding transistors shown are omitted for brevity.

[0206] In some embodiments, gate 306b is the gate of NFET transistor N2-L, gate 306c is the gate of NFET transistor N1-L, gate 306d is the gate of NFET transistor N1-R, gate 306e is the gate of NFET transistor N2-R, gate 306f is the gate of NFET transistor N3-R, gate 306g is the gate of NFET transistor N4-R, gate 306h is the gate of NFET transistor N4-L, and gate 306i is the gate of NFET transistor N3-L.

[0207] In some embodiments, gate 306a is the dummy gate of a dummy transistor. In some embodiments, the dummy transistor is a non-functional transistor. In some embodiments, gate 306j is the dummy gate of a dummy transistor.

[0208] In some embodiments, gate 308b is the gate of PFET transistor P2-L, gate 308c is the gate of PFET transistor P1-L, gate 308d is the gate of PFET transistor P1-R, gate 308e is the gate of PFET transistor P2-R, gate 308f is the gate of PFET transistor P3-R, gate 308g is the gate of PFET transistor P4-R, gate 308h is the gate of PFET transistor P4-L, and gate 308i is the gate of PFET transistor P3-L.

[0209] In some embodiments, gate 308a is the dummy gate of a dummy transistor. In some embodiments, gate 308j is the dummy gate of a dummy transistor.

[0210] In some embodiments, gate 306a and gate 308a are coupled together. In some embodiments, gate 306a and gate 308a are part of the same continuous structure.

[0211] In some embodiments, gate 306b and gate 308b are coupled together. In some embodiments, gate 306b and gate 308b are part of the same continuous structure.

[0212] In some embodiments, gate 306c and gate 308c are coupled together. In some embodiments, gate 306c and gate 308c are part of the same continuous structure.

[0213] In some embodiments, gate 306d and gate 308d are coupled together. In some embodiments, gate 306d and gate 308d are part of the same continuous structure.

[0214] In some embodiments, gate 306e and gate 308e are coupled together. In some embodiments, gate 306e and gate 308e are part of the same continuous structure.

[0215] In some embodiments, gate 306f and gate 308f are coupled together. In some embodiments, gate 306f and gate 308f are part of the same continuous structure.

[0216] In some embodiments, gate 306g and gate 308g are coupled together. In some embodiments, gate 306g and gate 308g are part of the same continuous structure.

[0217] In some embodiments, gate 306h and gate 308h are coupled together. In some embodiments, gate 306h and gate 308h are part of the same continuous structure.

[0218] In some embodiments, gate 306i and gate 308i are coupled together. In some embodiments, gate 306i and gate 308i are part of the same continuous structure.

[0219] In some embodiments, gate 306j and gate 308j are coupled together. In some embodiments, gate 306j and gate 308j are part of the same continuous structure.

[0220] In some embodiments, gate group 306 or 308 encapsulates active region group 302 or 304.

[0221] Other configurations and arrangements of other layout levels or numbers of gates in gate groups 306 and 308 are within the scope of the present invention.

[0222] Each contact of contact group 310 or 312 corresponds to one or more drain terminals or source terminals of transistors P1-L, P2-L, P3-L, P4-L, P1-R, P2-R, P3-R, P4-R, N1-L, N2-L, N3-L, N4-L, N1-R, N2-R, N3-R, and N4-R of integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, one or more contacts of contact group 310 or 312 overlap a pair of active regions of active region groups 302 and 304, thereby electrically coupling a pair of active regions of active region groups 302 and 304 to the source or drain of the corresponding transistors.

[0223] In some embodiments, contact group 310 or 312 encapsulates active region group 302 or 304.

[0224] In some embodiments, the contact 310a corresponds to the drain terminal of the NFET transistor N2-L, the contact 310c corresponds to the drain terminals of the NFET transistors N1-L and N1-R, the contact 310e corresponds to the drain terminals of the NFET transistors N2-R and N3-R, the contact 310g corresponds to the drain terminals of the NFET transistors N4-R and N4-L, and the contact 310i corresponds to the drain terminal of the NFET transistor N3-L.

[0225] In some embodiments, the contact 310b corresponds to the source terminals of the NFET transistors N2-L and N1-L, the contact 310d corresponds to the source terminals of the NFET transistors N1-R and N2-R, the contact 310f corresponds to the source terminals of the NFET transistors N3-R and N4-R, and the contact 310h corresponds to the source terminals of the NFET transistors N4-L and N3-L.

[0226] In some embodiments, the contact 312a corresponds to the source terminal of the PFET transistor P2-L.

[0227] In some embodiments, the contact 312b corresponds to the drain terminal of the PFET transistor P2-L and the source terminal of the PFET transistor P1-L.

[0228] In some embodiments, the contact 312c corresponds to the drain terminals of the PFET transistors P1-L and P1-R.

[0229] In some embodiments, the contact 312d corresponds to the source terminal of the PFET transistor P1-R and the drain terminal of the PFET transistor P2-R.

[0230] In some embodiments, the contact 312e corresponds to the source terminal of the PFET transistor P2-R and the drain terminal of the PFET transistor P3-R.

[0231] In some embodiments, the contact 312f corresponds to the source terminal of the PFET transistor P3-R and the drain terminal of the PFET transistor P4-R.

[0232] In some embodiments, the contact 312g corresponds to the source terminals of the PFET transistors P4-R and P4-L.

[0233] In some embodiments, the contact 312h corresponds to the drain terminal of the PFET transistor P4-L and the source terminal of the PFET transistor P3-L.

[0234] In some embodiments, the contact 312i corresponds to the drain terminal of the PFET transistor P3-L.

[0235] In some embodiments, the contact 314a corresponds to the drain terminals of the NFET transistors N1-L and N1-R, the drain terminal of the PFET transistor P1-L, and the drain terminal of the PFET transistor P1-R.

[0236] Other configurations and arrangements of other layout levels or numbers of contacts in the contact sets 310, 312, and 314 are within the scope of the present utility model.

[0237] The conductor set 330 is an M0 wiring path. In some embodiments, the conductor sets 330 and 332 are wiring paths in other layers. In some embodiments, the conductor set 330 corresponds to 2 M0 wiring paths.

[0238] The conductor set 332 is a BM0 wiring path. In some embodiments, the conductor set 332 corresponds to 2 BM0 wiring paths.

[0239] Other configurations and arrangements of other layout levels or numbers of conductors in the conductor sets 330 and 332 are within the scope of the present utility model.

[0240] In some embodiments, the power rail 336a of the power rail set 336 is located on the front side 303a of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the power rail 336a of the power rail set 336 is configured to supply voltage VDD or reference voltage VSS.

[0241] In some embodiments, the power rail 336b of the power rail set 336 is located on the back side 303b of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the power rail 336b of the power rail set 336 is configured to supply reference voltage VSS or voltage VDD.

[0242] The via set 320 is configured to electrically couple the corresponding source or drain regions of the active region set 302 to the conductor set 330 through the contact set 310, and vice versa. The via set 320 is located between the contact set 310 and the conductor set 330.

[0243] The via set 322 is configured to electrically couple the corresponding source or drain regions of the active region set 304 to the conductor set 332 through the contact set 312, and vice versa. The via set 322 is located between the contact set 312 and the conductor set 332.

[0244] The via group 324 is configured to electrically couple one or more gates of the gate group 306 to the conductor group 330, and vice versa. The via group 324 is located between the gate group 306 and the conductor group 330.

[0245] The via group 326 is configured to electrically couple one or more gates of the gate group 308 to the conductor group 332, and vice versa. The via group 326 is located between the gate group 308 and the conductor group 332.

[0246] The via 320a electrically couples the conductor 330e to the contact 310a. The via 320b electrically couples the conductor 330e to at least one of the contacts 310c or 314a. The via 320c electrically couples the conductor 330e to the contact 310e. The via 320d electrically couples the conductor 330e to the contact 310g. The via 320e electrically couples the conductor 330e to the contact 310i.

[0247] The via 322a electrically couples the conductor 332a to the contact 312a. The via 322b electrically couples the conductor 332a to the contact 312i.

[0248] The via 324a electrically couples the conductor 330a to the gate 306b. The via 324b electrically couples the conductor 330b to the gate 306c. The via 324c electrically couples the conductor 330b to the gate 306d. The via 324d electrically couples the conductor 330c to the gate 306g. The via 324e electrically couples the conductor 330c to the gate 306h. The via 324f electrically couples the conductor 330d to the gate 306i.

[0249] The via 326a electrically couples the conductor 332b to the gate 308b. The via 326b electrically couples the conductor 332b to the gate 308e. The via 326c electrically couples the conductor 332c to the gate 308f. The via 326d electrically couples the conductor 332c to the gate 308i.

[0250] Other configurations and arrangements of other layout levels or numbers of vias in the via groups 320, 322, 324, and 326 are within the scope of the present invention.

[0251] The conductor group 350 corresponds to 5 M1 wiring paths. Other numbers of M1 wiring paths are within the scope of the present invention. In some embodiments, the conductor group 350 is a wiring path in other metal layers.

[0252] In some embodiments, conductor 350a is an input pin configured to receive signal A2, conductor 350b is an input pin configured to receive signal A1, conductor 350d is an input pin configured to receive signal A4, and conductor 350e is an input pin configured to receive signal A3.

[0253] In some embodiments, conductor 350c is an output pin configured to output output signal OUT at node ZN.

[0254] Other configurations and arrangements of other layout levels or numbers of conductors in conductor group 350 are within the scope of the present invention.

[0255] Via group 340 is configured to electrically couple conductor group 350 to conductor group 330, and vice versa. Via group 340 is located between conductor group 350 and conductor group 330.

[0256] Via 340a electrically couples conductor 350a to conductor 330a.

[0257] Via 340b electrically couples conductor 350b to conductor 330b.

[0258] Via 340c electrically couples conductor 350c to conductor 330e.

[0259] Via 340d electrically couples conductor 350d to conductor 330c.

[0260] Via 340e electrically couples conductor 350e to conductor 330d.

[0261] In some embodiments, gate groups 306 and 308 electrically couple the front side 303a and the back side 303b of integrated circuit 300.

[0262] An input pin (e.g., conductor 350a) is electrically coupled to gates 306b, 308b, 308e, and 306e. For example, conductor 350a is electrically coupled to conductor 330a via via 340a. Conductor 330a is electrically coupled to gate 306b via via 324a. Gate 306b is directly coupled to gate 308b, and thus gate 306b is electrically coupled to gate 308b. Gate 308b is electrically coupled to conductor 332b via via 326a. Conductor 332b is electrically coupled to gate 308e via via 326b. Gate 308e is directly coupled to gate 306e, and thus gate 308e is electrically coupled to gate 306e.

[0263] In some embodiments, by providing electrical connections between an input pin (e.g., conductor 350a) and each of gate 306b, gate 308b, gate 308e, and gate 306e, the BM0 metallization level can be used as an additional routing resource, such that integrated circuit 300 has at least one of a reduced pitch, a smaller area, or a smaller standard cell as compared to other methods.

[0264] An input pin (e.g., conductor 350e) is electrically coupled to gate 306i, gate 308i, gate 308f, and gate 306f. For example, conductor 350e is electrically coupled to conductor 330d by via 340e. Conductor 330d is electrically coupled to gate 306i by via 324f. Gate 306i is directly coupled to gate 308i, and thus gate 306i is electrically coupled to gate 308i. Gate 308i is electrically coupled to conductor 332c by via 326d. Conductor 332c is electrically coupled to gate 308f by via 326c. Gate 308f is directly coupled to gate 306f, and thus gate 308f is electrically coupled to gate 306f.

[0265] In some embodiments, by providing electrical connections between an input pin (e.g., conductor 350e) and each of gate 306i, gate 308i, gate 308f, and gate 306f, the BM0 metallization level can be used as an additional routing resource, such that integrated circuit 300 has at least one of a reduced pitch, a smaller area, or a smaller standard cell as compared to other methods.

[0266] In some embodiments, gate groups 306 and 308 electrically couple the front side 303a and the back side 303b of integrated circuit 300, thereby using the BM0 metallization level as an additional routing resource, and further such that integrated circuit 300 has at least one of a reduced pitch, a smaller area, or a smaller standard cell as compared to other methods.

[0267] Other layout levels of the vias in via group 340 or other configurations and arrangements of the number are within the scope of the present utility model.

[0268] In some embodiments, at least one gate in gate groups 306, 308, 506, 508, 606, or 608 is formed using doped or undoped polysilicon (or polycrystalline silicon). In some embodiments, at least one gate of gate groups 306, 308, 506, 508, 606, or 608 comprises a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0269] In some embodiments, at least one contact of the contact sets 310, 312, 314, 510, 512, 514, at least one conductor of the conductor sets 330, 332, 350, 530, 532, 550, 552, 630, 632, 650, 652 or 670, or at least one via of the via sets 320, 322, 324, 326, 340, 520, 524, 526, 540, 542, 624, 626, 640, 642 or 660 includes one or more layers of a conductive material, a metal, a metal compound, or a doped semiconductor. In some embodiments, the conductive material includes tungsten, cobalt, ruthenium, copper, or similar materials or combinations thereof. In some embodiments, the metal includes at least copper (Cu), Co, W, Ru, Al, or similar materials. In some embodiments, the metal compound includes at least AlCu, W-TiN, TiSix, NiSix, TiN, TaN, or similar materials. In some embodiments, the doped semiconductor includes at least doped silicon or similar materials.

[0270] Other configurations or arrangements of the integrated circuit 300 are within the scope of the present invention.

[0271] Figure 4A is a block diagram of an integrated circuit 400A according to some embodiments.

[0272] The integrated circuit 400A includes a flip-flop 402a and a flip-flop 402b.

[0273] In some embodiments, the integrated circuit 400A is a flip-flop. In some embodiments, the integrated circuit 400A is a multi-bit flip-flop (MBFF). In some embodiments, the integrated circuit 400A is a two-bit flip-flop. In other words, the integrated circuit 400A includes two flip-flops (e.g., flip-flops 402a and 402b). Other numbers of bits or corresponding flip-flops in the integrated circuit 400A are within the scope of the present invention. In some embodiments, the integrated circuit 400A is a single-bit flip-flop and does not include the flip-flop 402b.

[0274] In some embodiments, the integrated circuit 400A is part of an integrated circuit (not shown) that includes other flip-flops similar to the flip-flop 400A, or one or more other flip-flops.

[0275] The integrated circuit 400A is configured to receive input signals IN1 and IN2.

[0276] The integrated circuit 400A is configured to generate output signals OUT1 and OUT2.

[0277] In some embodiments, one or more of triggers 402a or 402b are level triggered triggers. In some embodiments, one or more of triggers 402a or 402b are edge triggered triggers. In some embodiments, one or more of triggers 402a or 402b include DQ triggers, SR triggers, T triggers, JK triggers, or similar triggers. Other types of triggers or configurations of at least triggers 402a or 402b are within the scope of the present utility model.

[0278] In some embodiments, other numbers of inputs or outputs of integrated circuit 400A are within the scope of the present utility model.

[0279] Other configurations or arrangements of integrated circuit 400A are within the scope of the present utility model.

[0280] Figure 4B is a circuit diagram of integrated circuit 400B according to some embodiments.

[0281] In some embodiments, integrated circuit 400B is an embodiment of a part of integrated circuit 400A.

[0282] Integrated circuit 400B includes PFET transistors P1, P2, P3, P4, and P5 and NFET transistors N1, N2, N3, N4, and N5.

[0283] The gate terminal of PFET transistor P1 is configured as an input node (not labeled) for receiving input signal IN1. The gate terminal of NFET transistor N1 is configured as an input node (not labeled) for receiving input signal IN1.

[0284] In some embodiments, at least one of the gate terminals of PFET transistor P1 and NFET transistor N1 is coupled together.

[0285] The gate terminal of PFET transistor P4 is configured as an input node (not labeled) for receiving input signal IN2. The gate terminal of NFET transistor N4 is configured as an input node (not labeled) for receiving input signal IN2.

[0286] In some embodiments, at least one of the gate terminals of PFET transistor P4 and NFET transistor N4 is coupled together.

[0287] At least the drain terminal of PFET transistor P1 is coupled to the drain terminal of NFET transistor N1 and is configured as an output node for outputting output signal OUT1.

[0288] The source terminals of PFET transistor P1 and PFET transistor P2 are coupled together and further coupled to voltage supply VDD. In some embodiments, the drain terminals of PFET transistor P2 and PFET transistor P3 are coupled together.

[0289] The source terminals of NFET transistor N1 and NFET transistor N2 are coupled together and further coupled to reference voltage supply VSS. In some embodiments, the drain terminals of NFET transistor N2 and NFET transistor N3 are coupled together. In some embodiments, NFET transistor N1 and PFET transistor P1 are configured as an inverter. In some embodiments, NFET transistors N4 and N5 and PFET transistors P4 and P5 are configured as stacked gates.

[0290] Each of the gate terminals of PFET transistor P5, NFET transistor N5, PFET transistor P3, and NFET transistor N3 is configured as an input node (not labeled) for receiving output signal OUT1. Each of the gate terminals of PFET transistor P5, NFET transistor N5, PFET transistor P3, NFET transistor N3, the drain terminal of PFET transistor P1, and the drain terminal of NFET transistor N1 are coupled together.

[0291] At least the drain terminals of PFET transistor P5 and NFET transistor N5 are coupled together and configured as an output node for outputting output signal OUT2.

[0292] Each of the gate terminals of PFET transistor P2 and NFET transistor N2 is configured as an input node (not labeled) for receiving output signal OUT2. Each of the gate terminals of PFET transistor P2, NFET transistor N2, the drain terminal of PFET transistor P5, and the drain terminal of NFET transistor N5 are coupled together.

[0293] The source terminal of PFET transistor P5 is coupled to the drain terminal of PFET transistor P4. The source terminal of PFET transistor P4 is coupled to the source terminal of PFET transistor P3 and further coupled to voltage supply VDD.

[0294] The source terminal of NFET transistor N5 is coupled to the drain terminal of NFET transistor N4. The source terminal of NFET transistor N4 is coupled to the source terminal of NFET transistor N3 and further coupled to reference voltage supply VSS.

[0295] Other circuits, other types of transistors, and / or other quantities of transistors are within the scope of various embodiments. For example, in some embodiments, integrated circuit 400B includes at least one of a voltage supply node VDD or a reference voltage supply node VSS, and at least one of the voltage supply node VDD or the reference voltage supply node VSS replaces a connection between one or more drain / source terminals.

[0296] Figures 5A to 5B is a diagram of an integrated circuit 500 according to some embodiments.

[0297] Figures 5A to 5B are corresponding diagrams (simplified for ease of illustration) of corresponding portions 500A to 500B of integrated circuit 500.

[0298] Portion 500A includes one or more features of integrated circuit 500 of the OD level, POLY level, MD level, MDLI level, M0 level, M1 level, VG level, VD level, and V0 level.

[0299] Portion 500B includes one or more features of integrated circuit 500 of the OD level, POLY level, BMD level, MDLI level, BM0 level, BVG level, BVD level, BM1 level, and BV0 level.

[0300] Integrated circuit 500 is manufactured by a corresponding layout design similar to that of integrated circuit 500. Integrated circuit 500 is an embodiment of integrated circuit 400A or 400B, and similar detailed descriptions are omitted. For the sake of brevity, Figures 5A to 5B is described as integrated circuit 500, but in some embodiments, Figures 5A to 5B also corresponds to a layout design similar to layout design 200. The structural components of integrated circuit 500 also correspond to layout patterns, and the structural relationships including alignment, length, and width, as well as the configuration and layers of the corresponding layout design of integrated circuit 500 are similar to the structural relationships, configuration, and layers of integrated circuit 500, and similar detailed descriptions will not be elaborated for the sake of brevity.

[0301] In some embodiments, integrated circuit 500 is manufactured by a layout design similar to layout design 200, and similar detailed descriptions are omitted for the sake of brevity.

[0302] Integrated circuit 500 includes at least active region groups 302 and 304, gate groups 506, 508, contact groups 510, 512, 514, via groups 520, 524, 526, conductor groups 530, 532, power rail group 336, via group 540, conductor group 550, via group 542, conductor group 552, substrate 390, and insulating region 392.

[0303] Integrated circuit 500 is a variant of integrated circuit 300 ( Figures 3A to 3E ). Compared with the Figures 3A to 3E illustrated integrated circuit 300, in integrated circuit 500, gate group 506 replaces gate group 306, gate group 508 replaces gate group 308, contact group 510 replaces contact group 310, contact group 512 replaces contact group 312, contact group 514 replaces contact group 314, via group 520 replaces via group 320, via group 524 replaces via group 324, via group 526 replaces via group 326, conductor group 530 replaces conductor group 330, conductor group 532 replaces conductor group 332, via group 540 replaces via group 340, and conductor group 550 replaces conductor group 350, and thus similar detailed descriptions are omitted.

[0304] Compared with the Figures 3A to 3E illustrated integrated circuit 300, integrated circuit 500 further includes via group 542 and conductor group 552.

[0305] Gate group 506 includes at least gates 506a, 506b, …, 506f or 506g.

[0306] Compared with the Figures 3A to 3E illustrated integrated circuit 300, at least one or more of gates 506a, 506b, …, 506f or 506g replace at least one or more of gates 306a, 306b, …, 306i or 306j of gate group 306, and thus similar detailed descriptions are omitted.

[0307] Gate groups 506 and 508 correspond to one or more gates of transistors P1, P2, P3, P4, P5, N1, N2, N3, N4, and N5 of integrated circuit 400B or 500. In some embodiments, each of the gates in gate groups 506 and 508 is Figures 5A to 5B shown in with the label "P1, P2, P3, P4, P5, N1, N2, N3, N4, and N5", and the label identifies those having Figures 5A to 5Bcorresponding to the gate in Figure 4B the corresponding transistor shown and is omitted for simplicity.

[0308] In some embodiments, gate 506b is the gate of NFET transistor N1, gate 506c is the gate of NFET transistor N2, gate 506d is the gate of NFET transistor N3, gate 506e is the gate of NFET transistor N4, and gate 506f is the gate of NFET transistor N5.

[0309] In some embodiments, gate 506a is the dummy gate of a dummy transistor. In some embodiments, gate 506g is the dummy gate of a dummy transistor.

[0310] The gate group 508 includes at least gates 508a, 508b, …, 508f or 508g.

[0311] Compared with Figures 3A to 3E the integrated circuit 300 shown, at least one or more of the gates 508a, 508b, …, 508f or 508g replace at least one or more of the gates 308a, 308b, …, 308i or 308j of the gate group 308, and thus similar detailed descriptions are omitted.

[0312] In some embodiments, gate 508b is the gate of PFET transistor P1, gate 508c is the gate of PFET transistor P2, gate 508d is the gate of PFET transistor P3, gate 508e is the gate of PFET transistor P4, and gate 508f is the gate of PFET transistor P5.

[0313] In some embodiments, gate 508a is the dummy gate of a dummy transistor. In some embodiments, gate 508g is the dummy gate of a dummy transistor.

[0314] Other configurations or arrangements of other layout levels or numbers of the gates in the gate groups 506 and 508 are within the scope of the present invention.

[0315] The contact group 510 includes at least contacts 510a, 510b, …, 510e or 510f.

[0316] Compared with Figures 3A to 3E the integrated circuit 300 shown, at least one or more of the contacts 510a, 510b, …, 510e or 510f replace at least one or more of the contacts 310a, 310b, …, 310h or 310i of the contact group 310, and thus similar detailed descriptions are omitted.

[0317] Each contact of contact group 510 or 512 corresponds to one or more drain terminals or source terminals of transistors P1, P2, P3, P4, P5, N1, N2, N3, N4, and N5 of integrated circuit 400B or 500.

[0318] In some embodiments, contact 510a corresponds to the drain terminal of NFET transistor N1, contact 510b corresponds to the source terminal of NFET transistor N1 and the drain terminal of NFET transistor N2, contact 510c corresponds to the source terminal of NFET transistor N2 and the source terminal of NFET transistor N3, contact 510d corresponds to the drain terminal of NFET transistor N3 and the source terminal of NFET transistor N4, contact 510e corresponds to the drain terminal of NFET transistor N4 and the source terminal of NFET transistor N5, and contact 510f corresponds to the drain terminal of NFET transistor N5.

[0319] Contact group 512 includes at least contacts 512a, 512b,..., 512e or 512f.

[0320] And Figures 3A to 3E Compared with the illustrated integrated circuit 300, at least one or more of contacts 512a, 512b,..., 512e or 512f replace at least one or more of contacts 312a, 312b,..., 312h or 312i of contact group 312, and thus similar detailed descriptions are omitted.

[0321] In some embodiments, contact 512a corresponds to the drain terminal of PFET transistor P1, contact 512b corresponds to the source terminal of PFET transistor P1 and the drain terminal of PFET transistor P2, contact 512c corresponds to the source terminal of PFET transistor P2 and the source terminal of PFET transistor P3, contact 512d corresponds to the drain terminal of PFET transistor P3 and the source terminal of PFET transistor P4, contact 512e corresponds to the drain terminal of PFET transistor P4 and the source terminal of PFET transistor P5, and contact 512f corresponds to the drain terminal of PFET transistor P5.

[0322] Contact group 514 includes at least contacts 514a or 514b.

[0323] And Figures 3A to 3E Compared with the illustrated integrated circuit 300, at least one or more of contacts 514a or 514b replace at least one or more of contacts 314a of contact group 314, and thus similar detailed descriptions are omitted.

[0324] In some embodiments, the contact 514a corresponds to the drain terminal of the NFET transistor N1 and the drain terminal of the PFET transistor P1.

[0325] In some embodiments, the contact 514b corresponds to the drain terminal of the NFET transistor N5 and the drain terminal of the PFET transistor P5.

[0326] Other configurations and arrangements of other layout levels or quantities of the contacts in the contact sets 510, 512, and 514 are within the scope of the present invention.

[0327] The conductor set 530 includes at least conductors 530a, 530b, or 530c.

[0328] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of the conductors 530a, 530b, or 530c replace at least one or more of the conductors 330a, 330b, 330c, 330d, or 330e of the conductor set 330, and thus similar detailed descriptions are omitted.

[0329] The conductor set 532 includes at least conductors 532a or 532b.

[0330] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of the conductors 532a or 532b replace at least one or more of the conductors 332a, 332b, or 332c of the conductor set 332, and thus similar detailed descriptions are omitted.

[0331] The conductor set 530 is an M0 wiring path. In some embodiments, the conductor sets 530 and 532 are wiring paths in other layers. In some embodiments, the conductor set 530 corresponds to 2 M0 wiring paths.

[0332] The conductor set 532 is a BM0 wiring path. In some embodiments, the conductor set 532 corresponds to 2 BM0 wiring paths.

[0333] Other configurations and arrangements of other layout levels or quantities of the conductors in the conductor sets 530 and 532 are within the scope of the present invention.

[0334] The via set 520 includes at least vias 520a or 520b.

[0335] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of the vias 520a or 520b replace at least one or more of the vias 320a, 320b,..., 320e of the via set 320, and thus similar detailed descriptions are omitted.

[0336] The via group 524 includes at least vias 524a, 524b, or 524c.

[0337] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of the vias 524a, 524b, or 524c replace at least one or more of the vias 324a, 324b, …, 324f of the via group 324, and thus similar detailed descriptions are omitted.

[0338] The via group 526 includes at least vias 526a, 526b, or 526c.

[0339] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of the vias 526a, 526b, or 526c replace at least one or more of the vias 326a, 326b, …, 326d of the via group 326, and thus similar detailed descriptions are omitted.

[0340] The via 520a electrically couples the conductor 530b to at least one of the contacts 510a or 514a.

[0341] The via 520b electrically couples the conductor 530a to the contact 510f.

[0342] The via 524a electrically couples the conductor 530a to the gate 506c.

[0343] The via 524b electrically couples the conductor 530b to the gate 506d.

[0344] The via 524c electrically couples the conductor 530c to the gate 506e.

[0345] The via 526a electrically couples the conductor 532a to the gate 508b.

[0346] The via 526b electrically couples the conductor 532b to the gate 508d.

[0347] The via 526c electrically couples the conductor 532b to the gate 508f.

[0348] Other configurations and arrangements of other layout levels or quantities of the vias in the via groups 520, 524, and 526 are within the scope of the present utility model.

[0349] The conductor group 550 includes at least the conductor 550a.

[0350] Compared with Figures 3A to 3EAs compared with the illustrated integrated circuit 300, at least one or more of the conductors 550a replace at least one or more of the conductors 350a, 350b, 350c, 350d, or 350e of the conductor group 350, and thus similar detailed descriptions are omitted.

[0351] The conductor group 550 corresponds to an M1 wiring path. Other numbers of M1 wiring paths are within the scope of the present invention. In some embodiments, the conductor group 550 is a wiring path in other metal layers.

[0352] In some embodiments, the conductor 550a is an input pin configured to receive the signal IN2.

[0353] The conductor group 552 includes at least the conductor 552a extending in the second direction Y.

[0354] Compared with Figures 3A to 3E As compared with the illustrated integrated circuit 300, at least one or more of the conductors 552a are similar to at least one or more of the conductors 350a, 350b, 350c, 350d, or 350e of the conductor group 350, and thus similar detailed descriptions are omitted.

[0355] The conductor group 552 corresponds to a BM1 wiring path. Other numbers of BM1 wiring paths are within the scope of the present invention. In some embodiments, the conductor group 552 is a wiring path in other metal layers.

[0356] In some embodiments, the conductor 552a is an input pin configured to receive the signal IN1.

[0357] In some embodiments, the conductor group 552 is located on the ninth layout level.

[0358] Other configurations and arrangements of other layout levels or numbers of conductors in the conductor group 550 or 552 are within the scope of the present invention.

[0359] The via group 540 includes at least the via 540a.

[0360] Compared with Figures 3A to 3E As compared with the illustrated integrated circuit 300, at least one or more of the vias 540a replace at least one or more of the vias 340a, 340b, …, 340e of the via group 340, and thus similar detailed descriptions are omitted.

[0361] The via 540a electrically couples the conductor 550a and the conductor 530c together.

[0362] The via group 542 includes at least the via 542a.

[0363] Compared with Figures 3A to 3ECompared with the integrated circuit 300 shown, at least one or more of the vias 542a are similar to at least one or more of the vias 340a, 340b, …, 340e of the via group 340, and thus the similar detailed description is omitted.

[0364] The via 542a electrically couples the conductor 552a and the conductor 532a together.

[0365] Other configurations and arrangements of other layout levels or numbers of vias in the via groups 540 and 542 are within the scope of the present utility model.

[0366] In some embodiments, the gate groups 506 and 508 electrically couple the front side 303a and the back side 303b of the integrated circuit 500.

[0367] The output node (e.g., the conductor 532b) is electrically coupled to the gates 506d, 508d, 508f, and 506f. In some embodiments, the drain terminals of the NFET transistor N1 and the PFET transistor P1 are electrically coupled to the gate 506d of the NFET transistor N3, the gate 508d of the PFET transistor P3, the gate 508f of the PFET transistor P5, and the gate 506f of the NFET transistor N5. For example, the contact 512a is electrically coupled to the contact 510a through the contact 514a. The contact 510a is electrically coupled to the conductor 530b through the via 520a. The conductor 530b is electrically coupled to the gate 506d through the via 524b. The gate 506d is directly coupled to the gate 508d, and thus the gate 506d is electrically coupled to the gate 508d. The gate 508d is electrically coupled to the conductor 532b through the via 526b. The conductor 532b is electrically coupled to the gate 508f through the via 526c. The gate 508f is directly coupled to the gate 506f, and thus the gate 508f is electrically coupled to the gate 506f.

[0368] In some embodiments, by providing electrical connections between the output node (e.g., the conductor 532b) and each of the gates 506d, 508d, 508f, and 506f, the BM0 metallization layer can be used as an additional wiring resource, such that the integrated circuit 500 has at least one of a reduced pitch, a smaller area, or a smaller standard cell compared to other methods.

[0369] In some embodiments, the gate groups 506 and 508 electrically couple the front side 303a and the back side 303b of the integrated circuit 500.

[0370] The output node (e.g., conductor 530a) is electrically coupled to gate 506c and gate 506d. In some embodiments, the drain terminals of NFET transistor N5 and PFET transistor P5 are electrically coupled to gate 506c of NFET transistor N2 and gate 508c of PFET transistor P2. For example, contact 512f is electrically coupled to contact 510f via contact 514b. Contact 510f is electrically coupled to conductor 530a via via 520b. Conductor 530a is electrically coupled to gate 506c via via 524a. Gate 506c is directly coupled to gate 508c, and thus gate 506c is electrically coupled to gate 508c.

[0371] In some embodiments, gate sets 506 and 508 electrically couple the front side 303a and the back side 303b of integrated circuit 500, such that the BM0 metallization layer is used as an additional routing resource, thereby enabling integrated circuit 500 to have at least one of a reduced pitch, a smaller area, or a smaller standard cell as compared to other methods.

[0372] In some embodiments, by using the output node (e.g., conductor 530a) to provide electrical connections between the drain terminals of NFET transistor N5 and PFET transistor P5 and each of gate 506c and gate 508c, the BM0 metallization layer can be used as an additional routing resource, thereby enabling integrated circuit 500 to have at least one of a reduced pitch, a smaller area, or a smaller standard cell as compared to other methods.

[0373] In some embodiments, gate sets 506 and 508 electrically couple the front side 303a and the back side 303b of integrated circuit 500, such that there are no vias in via set 526 on the back side 303b directly located above active regions 302 or 304, thus reducing mask costs, thereby enabling integrated circuit 500 to have a lower process cost as compared to other methods.

[0374] In some embodiments, gate sets 506 and 508 electrically couple the front side 303a and the back side 303b of integrated circuit 500, such that the vias adjacent to the V0 vias in via set 540 are located in adjacent M0 paths, thus reducing mask costs, thereby enabling integrated circuit 500 to have a lower process cost as compared to other methods.

[0375] Other configurations or arrangements of integrated circuit 500 are within the scope of the present invention.

[0376] Figures 6A to 6D is a diagram of an integrated circuit 600 according to some embodiments.

[0377] Figures 6A to 6BIt is a corresponding diagram (simplified for ease of illustration) of corresponding parts 600A to 600B of integrated circuit 600.

[0378] Figures 6C to 6D It is a corresponding diagram (simplified for ease of illustration) of corresponding parts 690a to 690b of integrated circuit 600.

[0379] Part 600A includes one or more features of integrated circuit 600 of POLY layer, MD layer, MDLI layer, M0 layer, M1 layer, VG layer, VD layer, V0 layer, metal 2 (M2) layer, and via over metal 1 (V1) layer.

[0380] Part 600B includes one or more features of integrated circuit 600 of POLY layer, BMD layer, MDLI layer, BM0 layer, BVG layer, BVD layer, BM1 layer, and BV0 layer.

[0381] Part 690a includes Figure 6A The enlarged part 600C of the shown part 600A, and for the sake of brevity, similar detailed descriptions will not be elaborated.

[0382] Part 690b includes Figure 6B The enlarged part 600D of the shown part 600B, and for the sake of brevity, similar detailed descriptions will not be elaborated.

[0383] Integrated circuit 600 is manufactured by a corresponding layout design similar to integrated circuit 600. Integrated circuit 600 is an embodiment of integrated circuit 400A or 400B, and similar detailed descriptions are omitted. For the sake of brevity, Figures 6A to 6D is described as integrated circuit 600, but in some embodiments, Figures 6A to 6D also corresponds to a layout design similar to layout design 200. The structural components of integrated circuit 600 also correspond to layout patterns, and the structural relationships including alignment, length, and width, as well as the configuration and layers of the corresponding layout design of integrated circuit 600 are similar to the structural relationships, as well as the configuration and layers of integrated circuit 600, and similar detailed descriptions will not be elaborated for the sake of brevity.

[0384] In some embodiments, integrated circuit 600 is manufactured by a layout design similar to layout design 200, and similar detailed descriptions are omitted for the sake of brevity.

[0385] In some embodiments, at least signal IN2a or IN1a corresponds to Figure 4A signal IN1 in, and similar detailed descriptions are omitted for the sake of brevity. In some embodiments, signal IN3a corresponds to Figure 4Athe signal IN2 therein, and similar detailed descriptions are omitted for the sake of brevity.

[0386] Integrated circuit 600 includes at least gate group 606, gate group 608, via group 624, via group 626, conductor group 630, conductor group 632, via group 640, conductor group 650, via group 642, conductor group 652, via group 660, conductor group 670, substrate 390, and insulating region 392.

[0387] Integrated circuit 600 is a variant of integrated circuit 300 ( Figures 3A to 3E ) or 500 ( Figures 5A to 5B ). Compared with Figures 3A to 3E the illustrated integrated circuit 300 or Figures 5A to 5B the illustrated integrated circuit 500, in integrated circuit 600, gate group 606 replaces gate group 306, gate group 608 replaces gate group 308, via group 624 replaces via group 324, via group 626 replaces via group 326, conductor group 630 replaces conductor group 330, conductor group 632 replaces conductor group 332, via group 640 replaces via group 340, conductor group 650 replaces conductor group 350, and similar detailed descriptions are thus omitted.

[0388] Compared with Figures 5A to 5B the illustrated integrated circuit 500, integrated circuit 600 further includes via group 660 and conductor group 670.

[0389] Gate group 606 includes at least gates 606a, 606b, 606c, or 606d.

[0390] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of gates 606a, 606b, 606c, or 606d replace at least one or more of gates 306a, 306b, …, 306i, or 306j of gate group 306, and similar detailed descriptions are thus omitted.

[0391] Gate groups 606 and 608 correspond to one or more gates of transistors P1-6, P2-6, P3-6, P4-6, P5-6, N1-6, N2-6, N3-6, and N4-6 of integrated circuit 600. In some embodiments, each of the gates in gate groups 606 and 608 is shown in Figures 6A to 6D using the labels "P1-6, P2-6, P3-6, P4-6, P5-6, N1-6, N2-6, N3-6, and N4-6", and the labels identify the Figures 6A to 6D corresponding gates in Figure 4AThe corresponding transistors shown are omitted for simplicity.

[0392] In some embodiments, gate 606a is the gate of NFET transistor N1-6, gate 606b is the gate of NFET transistor N2-6 and the gate of NFET transistor N4-6, and gate 606c is the gate of NFET transistor N3-6.

[0393] Gate group 608 includes at least gate 608a, 608b, 608c or 608d.

[0394] Compared with Figures 3A to 3E the integrated circuit 300 shown, at least one or more of gates 608a, 608b, 608c or 608d replace at least one or more of gates 308a, 308b, …, 308i or 308j of gate group 308, and thus similar detailed descriptions are omitted.

[0395] In some embodiments, gate 608a is the gate of PFET transistor P1-6, gate 608b is the gate of PFET transistor P2-6 and the gate of PFET transistor P4-6, gate 608c is the gate of PFET transistor P3-6, and gate 608d is the gate of PFET transistor P5-6.

[0396] Other configurations and arrangements of other layout levels or quantities of the gates in gate groups 606 and 608 are within the scope of the present utility model.

[0397] Conductor group 630 includes at least conductor 630a, 630b, 630c or 630d.

[0398] Compared with Figures 3A to 3E the integrated circuit 300 shown, at least one or more of conductors 630a, 630b, 630c or 630d replace at least one or more of conductors 330a, 330b, 330c, 330d or 330e of conductor group 330, and thus similar detailed descriptions are omitted.

[0399] Conductor group 632 includes at least conductor 632a or 632b.

[0400] Compared with Figures 3A to 3E the integrated circuit 300 shown, at least one or more of conductors 632a or 632b replace at least one or more of conductors 332a, 332b or 332c of conductor group 332, and thus similar detailed descriptions are omitted.

[0401] Conductor group 630 is an M0 wiring path. In some embodiments, conductor groups 630 and 632 are wiring paths in other layers. In some embodiments, conductor group 630 corresponds to 2 M0 wiring paths.

[0402] The conductor group 632 is the BM0 wiring path. In some embodiments, the conductor group 632 corresponds to two BM0 wiring paths.

[0403] Other configurations and arrangements of other layout levels or numbers of conductors in the conductor groups 630 and 632 are within the scope of the present utility model.

[0404] The via group 624 includes at least vias 624a, 624b, or 624c.

[0405] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of the vias 624a, 624b, or 624c replace at least one or more of the vias 324a, 324b,..., 324f of the via group 324, and thus similar detailed descriptions are omitted.

[0406] The via group 626 includes at least vias 626a or 626b.

[0407] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of the vias 626a or 626b replace at least one or more of the vias 326a, 326b,..., 326d of the via group 326, and thus similar detailed descriptions are omitted.

[0408] The via 624a electrically couples the conductor 630a to the gate 606a.

[0409] The via 624b electrically couples the conductor 630b to the gate 606b.

[0410] The via 624c electrically couples the conductor 630c to the gate 606c.

[0411] The via 626a electrically couples the conductor 632a to the gate 608b.

[0412] The via 626b electrically couples the conductor 632b to the gate 608d.

[0413] Other configurations and arrangements of other layout levels or numbers of vias in the via groups 624 and 626 are within the scope of the present utility model.

[0414] The conductor group 650 includes at least conductors 650a, 650b, 650c, or 650d.

[0415] Compared with Figures 3A to 3ECompared with the illustrated integrated circuit 300, at least one or more of the conductors 650a, 650b, 650c, or 650d replace at least one or more of the conductors 350a, 350b, 350c, 350d, or 350e of the conductor group 350, and thus similar detailed descriptions are omitted.

[0416] The conductor group 650 corresponds to the M1 routing path. Other numbers of M1 routing paths are within the scope of the present invention. In some embodiments, the conductor group 650 is a routing path in other metal layers.

[0417] In some embodiments, the conductor 650a is an input pin configured to receive the signal IN3a.

[0418] In some embodiments, the conductor 650b is an input pin configured to receive the signal IN2a.

[0419] In some embodiments, the conductor 650c is an input pin configured to receive the signal IN1a.

[0420] In some embodiments, the conductor 650d is an input pin configured to receive the signal IN2a.

[0421] The conductor group 652 includes at least the conductor 652a.

[0422] Compared with Figures 5A to 5B the illustrated integrated circuit 500, at least one or more of the conductors 652a replace at least one or more of the conductors 552a of the conductor group 552, and thus similar detailed descriptions are omitted.

[0423] The conductor group 652 corresponds to the BM1 routing path. Other numbers of BM1 routing paths are within the scope of the present invention. In some embodiments, the conductor group 652 is a routing path in other metal layers.

[0424] In some embodiments, the conductor 652a is a node configured to electrically couple the gate 608b and the gate 608d together.

[0425] Other configurations and arrangements of other layout levels or quantities of the conductors in the conductor group 650 or 652 are within the scope of the present invention.

[0426] The via group 640 includes at least the vias 640a, 640b, 640c, or 640d.

[0427] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of the vias 640a, 640b, 640c, or 640d replace at least one or more of the vias 340a, 340b, …, 340e of the via group 340, and thus similar detailed descriptions are omitted.

[0428] The via hole 640a electrically couples the conductor 650a to the conductor 630a together.

[0429] The via hole 640b electrically couples the conductor 650b to the conductor 630b together.

[0430] The via hole 640c electrically couples the conductor 650c to the conductor 630c together.

[0431] The via hole 640d electrically couples the conductor 650d to the conductor 630d together.

[0432] The via hole group 642 includes at least the via hole 642a or 642b.

[0433] and Figures 3A to 3E Compared with the illustrated integrated circuit 300, at least one or more of the via holes 642a or 642b are similar to at least one or more of the via holes 340a, 340b, …, 340e of the via hole group 340, and thus the similar detailed description is omitted.

[0434] The via hole 642a electrically couples the conductor 652a to the conductor 632a together.

[0435] The via hole 642b electrically couples the conductor 652a to the conductor 632b together.

[0436] Other configurations and arrangements of other layout levels or numbers of the via holes in the via hole groups 640 and 642 are within the scope of the present utility model.

[0437] The conductor group 670 includes at least the conductor 670a extending in the first direction X.

[0438] and Figures 3A to 3E Compared with the illustrated integrated circuit 300, at least one or more of the conductors 670a are similar to at least one or more of the conductors 350a, 350b, 350c, 350d or 350e of the conductor group 350, and thus the similar detailed description is omitted.

[0439] Each conductor in the conductor group 670 is separated from another conductor in the conductor group 670 in the second direction Y.

[0440] The conductor group 670 overlaps with at least one of the active region groups 302 or 304, the gate groups 606 or 608, or the conductor groups 630, 632, 650 or 652.

[0441] The conductor group 670 corresponds to an M2 wiring path. Other numbers of M2 wiring paths are within the scope of the present utility model. In some embodiments, the conductor group 670 is a wiring path in other metal layers.

[0442] In some embodiments, the conductor group 670 is located on the tenth layout level.

[0443] In some embodiments, the tenth layout level is different from at least one of the first layout level, the second layout level, the third layout level, the fourth layout level, the fifth layout level, the sixth layout level, the seventh layout level, the eighth layout level, or the ninth layout level. In some embodiments, the tenth layout level corresponds to the M2 level of the layout design 200 or one or more of the integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the M2 level is above the OD level, the POLY level, the MD level, the M0 level, the M1 level, the BMD level, the BM0 level, and the BM1 level.

[0444] Other configurations or arrangements of other layout levels or quantities of the conductors in the conductor group 670 are within the scope of the present utility model.

[0445] The via group 660 includes at least via 660a or 660b.

[0446] The via group 660 is located at the M1 via (V1) level of the integrated circuit 600.

[0447] Compared with Figures 3A to 3E the illustrated integrated circuit 300, at least one or more of the vias 660a or 660b are similar to at least one or more of the vias 340a, 340b, …, 340e of the via group 340, and thus the similar detailed descriptions are omitted.

[0448] Via 660a electrically couples conductor 670a and conductor 650b together.

[0449] Via 660b electrically couples conductor 670a and conductor 650d together.

[0450] Other configurations or arrangements of other layout levels or quantities of the vias in the via group 660 are within the scope of the present utility model.

[0451] In some embodiments, the gate groups 606 and 608 electrically couple the front side 303a and the back side 303b of the integrated circuit 600.

[0452] An input pin (e.g., conductor 670a) is electrically coupled to gates 606b, 608b, 608d, and 606d. In some embodiments, each of the gates 606b of the NFET transistors N2-6 and N4-6, the gate 608b of the PFET transistor P2-6, the gate 606d of the NFET transistor N5-6, and the gate 608d of the PFET transistor P5-6 are electrically coupled together.

[0453] For example, conductor 670a is electrically coupled to conductor 650b through via 660a. Conductor 650b is electrically coupled to conductor 630b through via 640b. Conductor 630b is electrically coupled to gate 606b through via 624b. Gate 606b is directly coupled to gate 608b, and thus gate 606b is electrically coupled to gate 608b. Gate 608b is electrically coupled to conductor 632a through via 626a. Conductor 632a is electrically coupled to conductor 652a through via 642a. Conductor 652a is electrically coupled to conductor 632b through via 642b. Conductor 632b is electrically coupled to gate 608d through via 626b.

[0454] Conductor 670a is further electrically coupled to conductor 650d through via 660b. Conductor 650d is electrically coupled to conductor 630d through via 640d. Conductor 630d is electrically coupled to gate 606d through via 624d.

[0455] In some embodiments, gate groups 606 and 608 electrically couple the front side 303a and the back side 303b of integrated circuit 600, thereby using the BM0 metallization layer as an additional wiring resource, and thus enabling integrated circuit 600 to have at least one of a reduced pitch, a smaller area, or a smaller standard cell as compared to other methods.

[0456] In some embodiments, gate groups 606 and 608 electrically couple the front side 303a and the back side 303b of integrated circuit 600, thereby reducing the number of M2 cutting processes for cutting conductor group 670 along cell boundaries 301c or 301d, and thus enabling integrated circuit 600 to have a lower process cost as compared to other methods.

[0457] In some embodiments, by providing electrical connections between input pins (e.g., conductor 670a) and each of gates 606b, 608b, 608d, and 606d, the BM0 metallization layer can be used as an additional wiring resource, and thus enabling integrated circuit 600 to have at least one of a reduced pitch, a smaller area, or a smaller standard cell as compared to other methods.

[0458] In some embodiments, integrated circuit 600 achieves one or more of the benefits described herein.

[0459] Other configurations or arrangements of integrated circuit 600 are within the scope of the present invention.

[0460] Figures 7A to 7B is a functional flowchart of corresponding methods 700A to 700B for manufacturing an IC device according to some embodiments. It should be understood that it can be in Figures 7A to 7BAdditional operations are performed before, during, and / or after the methods 700A to 700B illustrated, and some other processes may be briefly described herein only.

[0461] In some embodiments, other operation sequences of the methods 700A to 900 are within the scope of the present utility model. The methods 700A to 900 include exemplary operations, but the operations are not necessarily performed in the order shown. Operations can be appropriately added, replaced, the operation order can be changed, and / or operations can be deleted according to the spirit and scope of the disclosed embodiments. In some embodiments, at least one or more of the operations of the methods 700A, 700B, 800, or 900 are not performed.

[0462] In some embodiments, the methods 700A to 700B are embodiments of operation 804 of the method 800. In some embodiments, the methods 700A to 900 can be used to manufacture or fabricate at least the integrated circuits 100, 300, 400A, 400B, 500, or 600, or integrated circuits having similar features to at least the layout design 200.

[0463] In operation 702 of the method 700A, a first set of transistors and a second set of transistors are fabricated on the front side 303a of a semiconductor wafer or substrate. In some embodiments, the first set of transistors or the second set of transistors of the methods 700A to 700B include one or more transistors located in at least one of the active region sets 302 or 304. In some embodiments, the first set of transistors or the second set of transistors of the methods 700A to 700B include one or more transistors described herein.

[0464] In some embodiments, operation 702 includes fabricating source and drain regions of a transistor group in a first well. In some embodiments, the first well contains a p-type dopant. In some embodiments, the p-type dopant includes boron, aluminum, or other suitable p-type dopants. In some embodiments, the first well includes an epi-layer grown on the substrate. In some embodiments, the epi-layer is doped by adding a dopant during the epitaxial process. In some embodiments, after the epi-layer is formed, the epi-layer is doped by ion implantation. In some embodiments, the first well is formed by doping the substrate. In some embodiments, doping is performed by ion implantation. In some embodiments, the first well has a dopant concentration ranging from 1×10 12 atoms / cm³ to 1×10 14 atoms / cm³.

[0465] In some embodiments, the first well contains an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopants. In some embodiments, the range of the n-type dopant concentration is between about 1×1012 atoms per cubic centimeter to about 1×10 14 atoms per cubic centimeter.

[0466] In some embodiments, forming source / drain features includes: removing a portion of the substrate to form a recess at the edge of the spacer; and then performing a filling process by filling the recess in the substrate. In some embodiments, after removing the pad oxide layer or the sacrificial oxide layer, the recess is etched, for example, by wet etching or dry etching. In some embodiments, an etching process is performed to remove the top surface portion of the active region adjacent to the isolation region (such as a shallow trench isolation (STI) region). In some embodiments, the filling process is performed by an epitaxy / epitaxial (epi) process. In some embodiments, a growth process that is concurrent with the etching process is used to fill the recess, wherein the growth rate of the growth process is greater than the etching rate of the etching process. In some embodiments, a combination of a growth process and an etching process is used to fill the recess. For example, a layer of material is grown in the recess, and then the grown material is subjected to an etching process to remove a portion of the material. Then, a subsequent growth process is performed on the etched material until the desired thickness of the material in the recess is achieved. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by an isotropic etching process or an anisotropic etching process. The etching process selectively etches the first well without etching the gate structure and any spacers. In some embodiments, the etching process is performed using reactive ion etch (RIE), wet etching, or other suitable techniques. In some embodiments, a semiconductor material is deposited in the recess to form the source / drain features. In some embodiments, an epitaxy process is performed to deposit the semiconductor material in the recess. In some embodiments, the epitaxy process includes a selective epitaxy growth (SEG) process, a chemical vapor deposition (CVD) process, molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epitaxy process uses gas precursors and / or liquid precursors that interact with the composition of the substrate. In some embodiments, the source / drain features include epitaxially grown silicon (epitaxial Si), silicon carbide, or silicon germanium. In some cases, during the epitaxy process, the source / drain features of the IC device associated with the gate structure are in-situ doped or undoped.When the source / drain features are not doped during the epitaxial process, in some cases, the source / drain features are doped during subsequent processes. The subsequent doping process is achieved by ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, after forming the source / drain features and / or after the subsequent doping process, the source / drain features are further exposed to an annealing process.

[0467] In some embodiments, operation 702 further includes operation 702a. In some embodiments, operation 702a includes forming a first gate region of a first set of transistors. In some embodiments, the first gate region of the first set of transistors of methods 700A to 700B includes gate sets 306, 308, 506, 508, 606, or 608.

[0468] In some embodiments, operation 702 further includes operation 702b. In some embodiments, operation 702b includes forming a second gate region of a second set of transistors. In some embodiments, the second gate region of the second set of transistors of methods 700A to 700B includes gate sets 306, 308, 506, 508, 606, or 608.

[0469] In some embodiments, the first gate region and the second gate region are located between the drain region and the source region. In some embodiments, the first gate region and the second gate region are located over the first well and the substrate. In some embodiments, fabricating the first gate region and the second gate region of operations 702a and 702b includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition process includes chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, fabricating the first gate region and the second gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, fabricating the first gate region and the second gate region includes forming a gate electrode or a dummy gate electrode. In some embodiments, fabricating the gate region includes depositing or growing at least one dielectric layer, such as a gate dielectric. In some embodiments, the gate region is formed using doped or undoped polysilicon (or polycrystalline silicon). In some embodiments, the first gate region and the second gate region contain a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0470] In some embodiments, forming a first insulating material on a first gate structure of a first set of transistors in operation 702b includes performing one or more deposition processes to form one or more dielectric material layers and / or insulating material layers. In some embodiments, the one or more deposition processes for forming one or more dielectric material layers and / or insulating material layers include CVD, PECVD, ALD, or other processes suitable for depositing one or more material layers. In some embodiments, forming a first insulating material on a first gate structure of a first set of transistors includes performing one or more deposition processes to form one or more insulating material layers. In some embodiments, the first insulating material is a dielectric material. In some embodiments, the dielectric material includes silicon dioxide, silicon oxynitride, or similar materials.

[0471] In some embodiments, operations 702a and 702b are replaced by the following method: forming one or more first gate regions of a first set of transistors and one or more second gate regions of a second set of transistors; removing a portion of the first gate regions of the first set of transistors and the second gate regions of the second set of transistors; and forming an insulating material between the first gate structure of the first set of transistors and the second gate structure of the second set of transistors. In some embodiments, the gate removal process is a POLY cut process including one or more etching processes. In some embodiments, the gate removal process includes one or more etching processes suitable for removing a portion of the gate structure. In some embodiments, a mask is used to specify the portion of the gate structure to be cut or removed. In some embodiments, the mask is a hard mask. In some embodiments, the mask is a soft mask. In some embodiments, the etching corresponds to plasma etching, reactive ion etching, chemical etching, dry etching, wet etching, other suitable processes, any combination thereof, or similar processes.

[0472] In some embodiments, operation 702 further includes operation 702c. In some embodiments, operation 702c includes depositing a first conductive material on at least one of a first level, a second level, or a third level thereby forming at least one of a corresponding first set of contacts, a second set of contacts, or a third set of contacts.

[0473] In some embodiments, the first set of contacts, the second set of contacts, and the third set of contacts are part of the first set of transistors and the second set of transistors.

[0474] In some embodiments, the first set of contacts includes contact group 310 or 510.

[0475] In some embodiments, the second set of contacts includes contact group 312 or 512.

[0476] In some embodiments, the third set of contacts includes contact group 314 or 514.

[0477] In operation 703 of method 700B, at least a first conductor located on the front side of the substrate is electrically coupled to at least a first gate of the first set of transistors via at least a back side 303b of the substrate.

[0478] In some embodiments, the first conductor located on the front side of the substrate in methods 700A to 700B includes one or more conductors from conductor sets 330, 530, or 630, conductor sets 332, 532, or 632, conductor sets 350, 550, or 650, conductor sets 552 or 652, or conductor set 670.

[0479] Figure 7B is a functional flowchart of method 700B for manufacturing an IC device according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after method 700B shown in Figure 7B and some other processes may be briefly described herein only.

[0480] In some embodiments, method 700B is an embodiment of operation 703 of method 700A, and thus similar detailed descriptions are omitted.

[0481] In operation 704 of method 700B, a first set of vias is formed on the front side 303a of the wafer or substrate at a VD level or a VG level (e.g., VD or VG). In some embodiments, the first set of vias of method 700B includes one or more portions of at least via groups 320, 324, 520, 524, or 624.

[0482] In some embodiments, operation 704 includes forming a first set of self - aligned contacts (SAC) in an insulating layer above the front side 303a of the wafer. In some embodiments, the first set of vias is electrically coupled to at least the first set of transistors.

[0483] In operation 706 of method 700B, a second conductive material is deposited on the front side 303a of the substrate at a first metal level, thereby forming a first set of conductors on the front side 303a of the wafer or substrate at the first metal level (e.g., M0).

[0484] In some embodiments, operation 706 includes depositing at least a first set of conductive regions above the front side 303a of the integrated circuit. In some embodiments, the first set of conductors of method 700B includes one or more portions of at least conductor sets 330, 530, or 630.

[0485] In operation 708 of method 700B, the backside 303b of the wafer or substrate is thinned. In some embodiments, operation 708 includes a thinning process performed on the backside 303b of the semiconductor wafer or substrate. In some embodiments, the thinning process includes grinding operations and polishing operations (such as chemical mechanical polishing (CMP)) or other suitable processes. In some embodiments, after the thinning process, a wet etching operation is performed to remove defects formed on the backside 303b of the semiconductor wafer or substrate.

[0486] In operation 710 of method 700B, a second set of vias is formed on the thinned backside 303b of the wafer or substrate at the BVD level or the BVG level (e.g., BVD or BVG). In some embodiments, the second set of vias of method 700B includes one or more portions of at least via groups 322, 326, 526, or 626.

[0487] In some embodiments, operation 710 includes forming a second set of SACs in an insulating layer over the backside 303b of the wafer. In some embodiments, the second set of vias is electrically coupled to at least a second set of transistors.

[0488] In operation 712 of method 700B, a third conductive material is deposited on the backside 303b of the substrate at the second metal level, thereby forming a second set of conductors on the backside 303b of the wafer or substrate at the second metal level (e.g., BM0).

[0489] In some embodiments, operation 712 includes depositing at least a second set of conductive regions over the backside 303b of the integrated circuit. In some embodiments, the second set of conductors of method 700B includes one or more portions of at least conductor groups 332, 532, or 632.

[0490] In operation 714 of method 700B, a third set of vias is formed on the front side 303a of the wafer or substrate at the V0 level (e.g., V0). In some embodiments, the third set of vias of method 700B includes one or more portions of at least via groups 340, 540, or 640.

[0491] In some embodiments, operation 714 includes forming a third set of SACs in an insulating layer over the front side 303a of the wafer. In some embodiments, the third set of vias is electrically coupled to at least a first set of transistors.

[0492] In operation 716 of method 700B, a fourth set of vias is formed on the thinned backside 303b of the wafer or substrate at the BV0 level (e.g., BV0). In some embodiments, the fourth set of vias of method 700B includes one or more portions of at least via groups 542 or 642.

[0493] In some embodiments, operation 716 includes forming a fourth set of SACs in an insulating layer over the backside 303b of the wafer. In some embodiments, the fourth set of vias is electrically coupled to at least a second set of transistors.

[0494] In operation 718 of method 700B, a fourth conductive material is deposited on the front side 303a of the substrate over a third metal level, thereby forming a third set of conductors on the front side 303a of the wafer or substrate over the third metal level (e.g., M1).

[0495] In some embodiments, operation 718 includes depositing at least a third set of conductive regions over the front side 303a of the integrated circuit. In some embodiments, the third set of conductors of method 700B includes one or more portions of at least conductor sets 350, 550, or 650.

[0496] In operation 720 of method 700B, a fifth conductive material is deposited on the backside 303b of the substrate over a fourth metal level, thereby forming a fourth set of conductors on the backside 303b of the wafer or substrate over the fourth metal level (e.g., BM1).

[0497] In some embodiments, operation 720 includes depositing at least a fourth set of conductive regions over the backside 303b of the integrated circuit. In some embodiments, the fourth set of conductors of method 700B includes one or more portions of at least conductor sets 552 or 652.

[0498] In operation 722 of method 700B, a fifth set of vias is formed on the front side 303a of the wafer or substrate over a V1 level (e.g., V1). In some embodiments, the fifth set of vias of method 700B includes one or more portions of at least via set 660.

[0499] In some embodiments, operation 722 includes forming a fifth set of SACs in an insulating layer over the front side 303a of the wafer. In some embodiments, the fifth set of vias is electrically coupled to at least a first set of transistors.

[0500] In operation 724 of method 700B, a sixth conductive material is deposited on the front side 303a of the substrate over a fifth metal level, thereby forming a fifth set of conductors on the front side 303a of the wafer or substrate over the fifth metal level (e.g., M2).

[0501] In some embodiments, operation 724 includes depositing at least a fifth set of conductive regions over the front side 303a of the integrated circuit. In some embodiments, the fifth set of conductors of method 700B includes one or more portions of at least conductor set 670.

[0502] In some embodiments, one or more of operations 702, 703, 704, 706, 710, 712, 714, 716, 718, 720, 722, or 724 of methods 700A to 700B include forming an opening in an insulating layer (not shown) over a substrate using a combination of a lithography and a material removal process. In some embodiments, the lithography process includes patterning a photoresist (e.g., a positive photoresist or a negative photoresist). In some embodiments, the lithography process includes forming a hard mask, an anti-reflective structure, or another suitable lithography structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, a RIE process, laser drilling, or another suitable etching process. The opening is then filled with a conductive material (e.g., copper, aluminum, titanium, nickel, tungsten, or other suitable conductive material). In some embodiments, the opening is filled using CVD, physical vapor deposition (PVD), sputtering, ALD, or other suitable forming processes.

[0503] In some embodiments, at least one or more operations of methods 700A to 700B are performed by Figure 11 the illustrated system 1100. In some embodiments, at least one method (e.g., methods 700A to 700B discussed above) is performed, in whole or in part, by at least one manufacturing system that includes system 1100. One or more of the operations of methods 700A to 700B are performed by an IC fabrication facility (fab) 1140 ( Figure 11 ) to fabricate an IC device 1160. In some embodiments, one or more of the operations of methods 700A to 700B are performed by a fabrication tool 1152 to fabricate a wafer 1142.

[0504] In some embodiments, the conductive material includes copper, aluminum, titanium, nickel, tungsten, or other suitable conductive material. In some embodiments, the opening and the trench are filled using CVD, PVD, sputtering, ALD, or other suitable forming processes. In some embodiments, after depositing the conductive material in one or more of operations 702c, 704, 706, 710, 712, 714, 716, 718, 720, 722, or 724, the conductive material is planarized to provide a level surface for subsequent steps.

[0505] In some embodiments, one or more of the operations of methods 700A to 700B, 800, or 900 are not performed.

[0506] One or more of the operations of methods 800 to 900 are implemented by a processing device configured to execute instructions for manufacturing an integrated circuit (e.g., at least integrated circuits 100, 300, 400A, 400B, 500, or 600). In some embodiments, one or more operations of methods 800 to 900 are implemented using the same processing device as that used in one or more different operations of methods 800 to 900. In some embodiments, one or more operations of methods 800 to 900 are implemented using different processing devices from those used for one or more different operations of methods 800 to 900. In some embodiments, other orders of operations of methods 700A to 700B, 800, or 900 are within the scope of the present invention. Methods 700A to 700B, 800, or 900 include exemplary operations, but the operations are not necessarily implemented in the order shown. According to the spirit and scope of the disclosed embodiments, operations in methods 700A to 700B, 800, or 900 can be appropriately added, replaced, the order of operations in methods 700A to 700B, 800, or 900 can be changed, and / or operations in methods 700A to 700B, 800, or 900 can be deleted.

[0507] Figure 8 is a flowchart of method 800 for forming or manufacturing an integrated circuit according to some embodiments. It should be understood that additional operations can be implemented before, during, and / or after method 800 depicted in Figure 8 and some other operations are only briefly described herein. In some embodiments, method 800 can be used to form an integrated circuit, such as at least integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, method 800 can be used to form an integrated circuit having similar features and similar structural relationships to one or more of layout design 200.

[0508] In operation 802 of method 800, a layout design of the integrated circuit is generated. Operation 802 is implemented by a processing device (e.g., processor 1002( Figure 10 )) configured to execute instructions for generating the layout design. In some embodiments, the layout design of method 800 includes at least one or more patterns of layout design 200, or includes one or more features similar to at least integrated circuits 100, 300, 400A, 400B, 500, or 600. In some embodiments, the layout design of the present application is in the graphic database system (GDSII) file format. In some embodiments, operation 802 corresponds to Figure 9 the method 900 shown.

[0509] In operation 804 of method 800, an integrated circuit is fabricated based on a layout design. In some embodiments, operation 804 of method 800 includes: fabricating at least one mask based on the layout design; and fabricating the integrated circuit based on the at least one mask. In some embodiments, operation 804 corresponds to Figures 7A to 7B the methods 700A to 700B shown.

[0510] Figure 9 is a flowchart of a method 900 for generating a layout design of an integrated circuit according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 900 depicted in Figure 9 and some other processes may only be briefly described herein. In some embodiments, method 900 is an embodiment of operation 802 of method 800. In some embodiments, method 900 may be used to generate one or more layout patterns of at least layout design 200, or to generate one or more features similar to at least integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0511] In some embodiments, method 900 may be used to generate one or more layout patterns having structural relationships, configurations, and layers including alignment, length, and width of at least layout design 200, or to generate one or more features similar to at least integrated circuits 100, 300, 400A, 400B, 500, or 600, and for the sake of brevity, similar detailed descriptions will not be repeated in Figure 9 the following.

[0512] In operation 902 of method 900, a set of active region patterns is generated or placed on the layout design. In some embodiments, the set of active region patterns of method 900 includes at least some portions of one or more patterns of active region pattern sets 202 or 204. In some embodiments, the set of active region patterns of method 900 includes one or more regions similar to active region sets 302 or 304. In some embodiments, the set of active region patterns of method 900 includes one or more patterns or similar patterns in the OD layer.

[0513] In operation 904 of method 900, a set of gate patterns is generated or placed on the layout design. In some embodiments, the set of gate patterns of method 900 includes at least some portions of one or more patterns of gate pattern sets 206 or 208. In some embodiments, the set of active gate patterns of method 900 includes one or more regions similar to gate sets 306, 308, 506, 508, 606, or 608. In some embodiments, the set of gate patterns of method 900 includes one or more patterns or similar patterns in the POLY layer.

[0514] In operation 906 of method 900, a first set of conductive patterns is generated or placed in a layout design. In some embodiments, the first set of conductive patterns of method 900 includes at least some portions of one or more patterns of contact pattern group 210. In some embodiments, the first set of conductive patterns of method 900 includes one or more patterns similar to contact group 310 or 510. In some embodiments, the first set of conductive patterns of method 900 includes one or more patterns in the MD layer or similar patterns.

[0515] In operation 908 of method 900, a second set of conductive patterns is generated or placed in a layout design. In some embodiments, the second set of conductive patterns of method 900 includes at least some portions of one or more patterns of contact pattern group 212. In some embodiments, the second set of conductive patterns of method 900 includes one or more patterns similar to contact group 312 or 512. In some embodiments, the second set of conductive patterns of method 900 includes one or more patterns in the BMD layer or similar patterns.

[0516] In operation 910 of method 900, a third set of conductive patterns is generated or placed in a layout design. In some embodiments, the third set of conductive patterns of method 900 includes at least some portions of one or more patterns of contact pattern group 214. In some embodiments, the third set of conductive patterns of method 900 includes one or more patterns similar to contact group 314 or 514. In some embodiments, the third set of conductive patterns of method 900 includes one or more patterns in the MDLI layer or similar patterns.

[0517] In operation 912 of method 900, a first set of via patterns is generated or placed in a layout design. In some embodiments, the first set of via patterns of method 900 includes at least some portions of one or more patterns of via pattern group 220 or 224. In some embodiments, the first set of via patterns of method 900 includes one or more via patterns similar to at least via groups 320, 324, 520, 524, or 624. In some embodiments, the first set of via patterns of method 900 includes one or more patterns or similar vias in the VG or VD layer.

[0518] In operation 914 of method 900, a second set of via patterns is generated or placed in a layout design. In some embodiments, the second set of via patterns of method 900 includes at least some portions of one or more patterns of via pattern group 222 or 226. In some embodiments, the second set of via patterns of method 900 includes one or more via patterns similar to at least via groups 322, 326, 526, or 626. In some embodiments, the second set of via patterns of method 900 includes one or more patterns or similar vias in the BVG or BVD layer.

[0519] In operation 916 of method 900, a fourth set of conductive patterns is generated or placed in the layout design. In some embodiments, the fourth set of conductive patterns of method 900 includes at least a portion of one or more patterns of at least conductive pattern set 230. In some embodiments, the fourth set of conductive patterns of method 900 includes one or more conductive patterns similar to at least conductor sets 330, 530, or 630. In some embodiments, the fourth set of conductive patterns of method 900 includes one or more patterns or similar conductors in the M0 layer.

[0520] In operation 918 of method 900, a fifth set of conductive patterns is generated or placed in the layout design. In some embodiments, the fifth set of conductive patterns of method 900 includes at least some portions of one or more patterns of at least conductive pattern set 232. In some embodiments, the fifth set of conductive patterns of method 900 includes one or more conductive patterns similar to at least conductor sets 332, 532, or 632. In some embodiments, the fifth set of conductive patterns of method 900 includes one or more patterns or similar conductors in the BM0 layer.

[0521] In operation 920 of method 900, a third set of via patterns is generated or placed in the layout design. In some embodiments, the third set of via patterns of method 900 includes at least some portions of one or more patterns of via pattern set 240. In some embodiments, the third set of via patterns of method 900 includes one or more via patterns similar to at least via sets 340, 540, or 640. In some embodiments, the third set of via patterns of method 900 includes one or more patterns or similar vias in the V0 layer.

[0522] In operation 922 of method 900, a fourth set of via patterns is generated or placed in the layout design. In some embodiments, the fourth set of via patterns of method 900 includes one or more via patterns similar to at least via sets 542 or 642. In some embodiments, the fourth set of via patterns of method 900 includes one or more patterns or similar vias in the BV0 layer.

[0523] In operation 924 of method 900, a sixth set of conductive patterns is generated or placed in the layout design. In some embodiments, the sixth set of conductive patterns of method 900 includes at least some portions of one or more patterns of at least conductive pattern set 250. In some embodiments, the sixth set of conductive patterns of method 900 includes one or more conductive patterns similar to at least conductor sets 350, 550, or 650. In some embodiments, the sixth set of conductive patterns of method 900 includes one or more patterns or similar conductors in the M1 layer.

[0524] In operation 926 of method 900, a seventh set of conductive patterns is generated or placed in the layout design. In some embodiments, the seventh set of conductive patterns of method 900 includes one or more conductive patterns similar to at least conductor group 552 or 652. In some embodiments, the seventh set of conductive patterns of method 900 includes one or more patterns in the BM1 layer or a conductor similar thereto.

[0525] In operation 928 of method 900, a fifth set of via patterns is generated or placed in the layout design. In some embodiments, the fifth set of via patterns of method 900 includes one or more via patterns similar to at least via group 660. In some embodiments, the fifth set of via patterns of method 900 includes one or more patterns in the V1 layer or a via similar thereto.

[0526] In operation 930 of method 900, an eighth set of conductive patterns is generated or placed in the layout design. In some embodiments, the eighth set of conductive patterns of method 900 includes one or more conductive patterns similar to at least conductor group 670. In some embodiments, the eighth set of conductive patterns of method 900 includes one or more patterns in the M2 layer or a conductor similar thereto.

[0527] Figure 10 is a schematic diagram of a system 1000 for designing an IC layout design and manufacturing an IC circuit according to some embodiments.

[0528] In some embodiments, system 1000 generates or places one or more of the IC layout designs described herein. System 1000 includes a hardware processor 1002 and a non-transitory computer-readable storage medium 1004 (e.g., memory 1004) encoded with (i.e., storing) computer program code 1006 (i.e., a set of executable instructions 1006). The computer-readable storage medium 1004 is configured to interface with a manufacturing machine for producing the integrated circuit. The processor 1002 is electrically coupled to the computer-readable storage medium 1004 via a bus 1008. The processor 1002 is also electrically coupled to an input / output (I / O) interface 1010 via the bus 1008. A network interface 1012 is also electrically connected to the processor 1002 via the bus 1008. The network interface 1012 is connected to a network 1014 such that the processor 1002 and the computer-readable storage medium 1004 can be connected to external components via the network 1014. The processor 1002 is configured to execute the computer program code 1006 encoded in the computer-readable storage medium 1004 such that the system 1000 can be used to perform some or all of the operations described in methods 800 to 900.

[0529] In some embodiments, the processor 1002 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0530] In some embodiments, the computer-readable storage medium 1004 is an electronic system, a magnetic system, an optical system, an electromagnetic system, an infrared system, and / or a semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1004 includes semiconductor or solid state memory, magnetic tape, removable computer disks, random access memory (RAM), read-only memory (ROM), hard disks, and / or optical disks. In some embodiments using optical disks, the computer-readable storage medium 1004 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0531] In some embodiments, the storage medium 1004 stores computer program code 1006 configured to cause the system 1000 to implement methods 800 to 900. In some embodiments, the storage medium 1004 also stores the information required to implement methods 800 to 900 and the information generated during the implementation of methods 800 to 900, such as layout design 1016, user interface 1018, and fabrication unit 1020 and / or an executable instruction set for operating to implement methods 800 to 900. In some embodiments, the layout design 1016 includes at least one or more of the layout patterns of the layout design 200, or includes features similar to at least the integrated circuits 100, 300, 400A, 400B, 500, or 600.

[0532] In some embodiments, the storage medium 1004 stores instructions (e.g., computer program code 1006) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 1006) enable the processor 1002 to generate manufacturing instructions readable by the manufacturing machine to effectively implement methods 800 to 900 during a manufacturing process.

[0533] System 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to external circuitry. In some embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for transmitting information and commands to the processor 1002.

[0534] System 1000 also includes a network interface 1012 coupled to the processor 1002. The network interface 1012 enables the system 1000 to communicate with a network 1014 that is connected to one or more other computer systems. The network interface 1012 includes, for example, wireless network interfaces such as BLUETOOTH, wireless fidelity (WIFI), World Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or wideband code division multiple access (WCDMA); or wired network interfaces such as ETHERNET, universal serial bus (USB), or Institute of Electrical and Electronics Engineers (IEEE)-2094. In some embodiments, methods 800 to 900 are implemented in two or more systems 1000, and information such as layout designs and user interfaces is exchanged between different systems 1000 via the network 1014.

[0535] System 1000 is configured to receive information related to a layout design via I / O interface 1010 or network interface 1012. The information is transmitted via bus 1008 to processor 1002 to determine a layout design for manufacturing at least integrated circuits 100, 300, 400A, 400B, 500, or 600. The layout design is then stored as layout design 1016 in computer-readable medium 1004. System 1000 is configured to receive information related to a user interface via I / O interface 1010 or network interface 1012. The information is stored as user interface 1018 in computer-readable medium 1004. System 1000 is configured to receive information related to fabrication unit 1020 via I / O interface 1010 or network interface 1012. The information is stored as fabrication unit 1020 in computer-readable medium 1004. In some embodiments, fabrication unit 1020 includes fabrication information utilized by system 1000. In some embodiments, fabrication unit 1020 corresponds to Figure 11 the mask fabrication 1134 shown.

[0536] In some embodiments, methods 800 to 900 are implemented as stand-alone software applications executed by a processor. In some embodiments, methods 800 to 900 are implemented as software applications that are part of an additional software application. In some embodiments, methods 800 to 900 are implemented as plug-ins of software applications. In some embodiments, methods 800 to 900 are implemented as software applications that are part of an electronic design automation (EDA) tool. In some embodiments, methods 800 to 900 are implemented as software applications used by an EDA tool. In some embodiments, an EDA tool is used to generate a layout of an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer-readable medium. In some embodiments, tools such as those available from CADENCE DESIGN SYSTEMS, Inc. or other suitable layout generation tools are used to generate the layout. In some embodiments, the layout is generated based on a netlist that is created based on a schematic design. In some embodiments, methods 800 to 900 are implemented by a manufacturing apparatus to manufacture an integrated circuit using a set of masks fabricated based on one or more layout designs generated by system 1000. In some embodiments, system 1000 is a manufacturing apparatus configured to manufacture an integrated circuit using a set of masks fabricated based on one or more layout designs of the present invention. In some embodiments, Figure 10 the system 1000 shown generates a layout design of an integrated circuit that is smaller than in other ways. In some embodiments, Figure 10The illustrated system 1000 provides a layout design of an integrated circuit structure that occupies less area and offers better wiring resources compared to other approaches.

[0537] Figure 11 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and an IC manufacturing process associated with the integrated circuit (IC) manufacturing system 1100 according to at least one embodiment of the present disclosure. In some embodiments, based on a layout diagram, the manufacturing system 1100 is used to fabricate at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0538] In Figure 11 IC manufacturing system 1100 (hereinafter "system 1100") includes entities such as, for example, a design house 1120, a mask house 1130, and an IC manufacturer / fabricator ("fab") 1140 that interact with each other in a design, development, and manufacturing cycle and / or services related to manufacturing an IC device 1160. The entities in system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks (e.g., an internal network and the Internet). The communication network includes wired channels and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and / or receives services from one or more of the other entities. In some embodiments, one or more of the design house 1120, the mask house 1130, and the IC fab 1140 are owned by a single larger company. In some embodiments, one or more of the design house 1120, the mask house 1130, and the IC fab 1140 coexist in a shared facility and use shared resources.

[0539] A design organization (or design team) 1120 generates an IC design layout 1122. The IC design layout 1122 includes various geometric patterns designed for an IC device 1160. The geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers of various components that make up the IC device 1160 to be fabricated. The various layers are combined to form various IC features. For example, a part of the IC design layout 1122 includes various IC features such as active regions, gate electrodes, source electrodes, and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads to be formed in a semiconductor substrate (e.g., a silicon wafer), as well as various material layers disposed on the semiconductor substrate. The design organization 1120 implements an appropriate design process to form the IC design layout 1122. The design process includes one or more of logic design, physical design, or place and route. The IC design layout 1122 exists in one or more data files having information of the geometric patterns. For example, the IC design layout 1122 can be expressed in the GDSII file format or the Design Framework II (DFII) file format.

[0540] The mask organization 1130 includes data preparation 1132 and mask fabrication 1134. The mask organization 1130 uses the IC design layout 1122 to fabricate one or more masks 1145 for the various layers to be used in fabricating the IC device 1160 according to the IC design layout 1122. The mask organization 1130 performs mask data preparation 1132, in which the IC design layout 1122 is translated into a representative data file (RDF). The mask data preparation 1132 provides the RDF to the mask fabrication 1134. The mask fabrication 1134 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask (reticle) 1145 or a semiconductor wafer 1142). The IC design layout 1122 is manipulated by the mask data preparation 1132 to comply with the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 1140. In Figure 11 it, the mask data preparation 1132 and the mask fabrication 1134 are shown as separate components. In some embodiments, the mask data preparation 1132 and the mask fabrication 1134 can be collectively referred to as mask data preparation.

[0541] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors (e.g., image errors that may be caused by diffraction, interference, other process effects, and the like). OPC adjusts the IC design layout 1122. In some embodiments, mask data preparation 1132 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0542] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC), which uses a set of mask creation rules that include specific geometric and / or connectivity restrictions to check the IC design layout that has undergone each process in the OPC to ensure that there is sufficient margin to account for variability and the like in the semiconductor manufacturing process. In some embodiments, the MRC modifies the IC design layout to compensate for the limitations during mask fabrication 1134, which may undo a portion of the modifications implemented by the OPC to meet the mask creation rules.

[0543] In some embodiments, mask data preparation 1132 includes lithography process checking (LPC), which simulates the processes to be performed by the IC foundry 1140 to fabricate the IC device 1160. LPC simulates this process based on the IC design layout 1122 to create a simulated fabricated device (e.g., IC device 1160). The process parameters in the LPC simulation can include parameters associated with the various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar factors or combinations thereof. In some embodiments, after a simulated fabricated device has been created by LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are reused to further refine the IC design layout 1122.

[0544] It should be understood that the above description of mask data preparation 1132 has been simplified for clarity. In some embodiments, data preparation 1132 includes additional features such as logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 1122 during data preparation 1132 can be performed in a variety of different orders.

[0545] After mask data preparation 1132 and during mask fabrication 1134, a mask 1145 or a group of masks 1145 is fabricated based on the modified IC design layout 1122. In some embodiments, mask fabrication 1134 includes performing one or more lithographic exposures based on the IC design layout 1122. In some embodiments, based on the modified IC design layout 1122, an electron-beam (e-beam) or multiple electron-beam mechanism is used to form a pattern on the mask (photomask or reticle) 1145. The mask 1145 can be formed using various techniques. In some embodiments, the mask 1145 is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) for exposing an image-sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary version of the mask 1145 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1145 is formed using phase-shift technology. In the phase-shift mask (PSM) version of the mask 1145, various features in the pattern formed on the mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The one or more masks produced by mask fabrication 1134 are used in various processes. For example, such masks are used in ion implantation processes for forming various doped regions in a semiconductor wafer, etching processes for forming various etched regions in a semiconductor wafer, and / or other suitable processes.

[0546] IC fabrication facility 1140 is an IC fabrication entity that includes one or more manufacturing facilities for fabricating various different IC products. In some embodiments, IC fabrication facility 1140 is a semiconductor foundry. For example, there can be a manufacturing facility for front-end-of-line (FEOL) fabrication of multiple IC products, while a second manufacturing facility can provide back-end-of-line (BEOL) fabrication for the interconnect and packaging of IC products, and a third manufacturing facility can provide other services for the foundry entity.

[0547] IC fabrication facility 1140 includes a wafer fabrication tool 1152 (hereinafter referred to as "fabrication tool 1152"), which is configured to perform various manufacturing operations on a semiconductor wafer 1142, thereby enabling an IC device 1160 to be fabricated according to a mask (e.g., mask 1145). In various embodiments, fabrication tool 1152 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or a low pressure CVD (LPCVD) furnace), a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes discussed herein.

[0548] IC fabrication facility 1140 uses mask 1145 fabricated by mask mechanism 1130 to fabricate IC device 1160. Thus, IC fabrication facility 1140 at least indirectly uses IC design layout 1122 to fabricate IC device 1160. In some embodiments, IC fabrication facility 1140 uses mask 1145 to fabricate semiconductor wafer 1142 to form IC device 1160. In some embodiments, IC fabrication includes performing at least one or more photolithographic exposures indirectly based on IC design layout 1122. Semiconductor wafer 1142 includes a silicon substrate or other suitable substrate with material layers formed thereon. Semiconductor wafer 1142 also includes one or more of various doped regions, dielectric features, multilevel interconnects, and similar components (formed at subsequent manufacturing steps).

[0549] System 1100 is shown with design agency 1120, mask agency 1130, or IC fabrication facility 1140 as separate components or entities. However, it should be understood that one or more of design agency 1120, mask agency 1130, or IC fabrication facility 1140 are part of the same component or entity.

[0550] One aspect of the present description relates to an integrated circuit. In some embodiments, the integrated circuit includes a first gate located on a first level. In some embodiments, the integrated circuit further includes a second gate located on a second level below the first level and coupled to the first gate. In some embodiments, the integrated circuit further includes a third gate located on the first level and separated from the first gate in a first direction. In some embodiments, the integrated circuit further includes a fourth gate located on the second level, separated from the second gate in the first direction, and coupled to the third gate. In some embodiments, the integrated circuit further includes a first input pin that extends in a second direction different from the first direction, is located on a first metal layer above the front side of the substrate, is coupled to at least the first gate, and is configured to receive a first input signal. In some embodiments, the integrated circuit further includes a first conductor that extends in the first direction, is located on a second metal layer below the back side of the substrate opposite to the front side of the substrate, and the first conductor is coupled to at least the second gate and the fourth gate. In some embodiments, the first input pin is electrically coupled to the third gate through at least the first gate, the second gate, or the fourth gate.

[0551] In some embodiments, the first input pin includes: a second conductor that extends in a second direction and is located on a first metal layer, and the second conductor is adjacent to the first gate. In some embodiments, the integrated circuit further includes a third conductor and a first via. The third conductor extends in a first direction and is located on a third metal layer above the front side of the substrate, the third metal layer being different from the first metal layer and the second metal layer, and the third conductor overlaps with the first gate and the second gate. The first via electrically couples the third conductor and the second conductor together, and the first via is located between the third conductor and the second conductor. In some embodiments, the integrated circuit further includes a second via that electrically couples the third conductor and the first gate together, and the second via is located between the third conductor and the first gate. In some embodiments, the integrated circuit further includes a third via that electrically couples the first conductor and the second gate together, and the third via is located between the first conductor and the second gate. In some embodiments, the integrated circuit further includes a fourth via that electrically couples the first conductor and the fourth gate together, and the fourth via is located between the first conductor and the fourth gate. In some embodiments, the integrated circuit further includes a fifth gate, a sixth gate, and a second input pin. The fifth gate is located on a first level and is separated from the first gate and the third gate in the first direction. The sixth gate is located on a second level, is separated from the second gate and the fourth gate in the first direction, and is coupled to the fifth gate. The second input pin extends in the second direction, is located on the first metal layer, is coupled to at least the fifth gate or the sixth gate, and is configured to receive a second input signal. In some embodiments, the second input pin includes a second conductor that extends in the second direction and is located on the first metal layer, and the second conductor is located between the fifth gate and the third gate. In some embodiments, the integrated circuit further includes a third conductor that extends in the first direction and is located on a third metal layer above the front side of the substrate, the third metal layer being different from the first metal layer and the second metal layer, and the third conductor overlaps with the fifth gate and the sixth gate. In some embodiments, the integrated circuit further includes a first via and a second via. The first via electrically couples the third conductor and the second conductor together, and the first via is located between the third conductor and the second conductor. The second via electrically couples the third conductor and the fifth gate together, and the second via is located between the third conductor and the fifth gate. In some embodiments, the integrated circuit further includes a seventh gate and an eighth gate. The seventh gate is located on the first level and is located between the fifth gate and the third gate in the first direction. The eighth gate is located on the second level, is located between the sixth gate and the fourth gate in the first direction, and is coupled to the seventh gate. In some embodiments, the integrated circuit further includes a third via that electrically couples the third conductor and the seventh gate together, and the third via is located between the third conductor and the seventh gate.

[0552] Another aspect of the present description relates to an integrated circuit. In some embodiments, the integrated circuit includes a first transistor stack located on a substrate. In some embodiments, the first transistor stack includes a first transistor of a first type, the first transistor including a first gate located on a first level. In some embodiments, the first transistor stack further includes a second transistor of a second type different from the first type, and the second transistor includes a second gate located on a second level below the first level. In some embodiments, the integrated circuit further includes a second transistor stack located on the substrate. In some embodiments, the second transistor stack includes a third transistor of the first type, the third transistor including a third gate located on the first level and separated from the first gate in a first direction. In some embodiments, the second transistor stack further includes a fourth transistor of the second type, the fourth transistor including a fourth gate located on the second level and separated from the third gate in the first direction. In some embodiments, the integrated circuit further includes a first input pin that extends in a second direction, is located on a first metal layer above the front side of the substrate, and is coupled to the first transistor and the second transistor. In some embodiments, the integrated circuit further includes a first conductor that extends in the first direction, is located on a second metal layer below the back side of the substrate opposite to the front side of the substrate, and the first conductor is coupled to the third gate and the fourth gate. In some embodiments, the first input pin is electrically coupled to the third gate from the back side of the substrate.

[0553] In some embodiments, the first input pin includes a second conductor that extends in a second direction and lies on a first metal layer. The second conductor is adjacent to the first gate and is coupled to the first transistor and the second transistor. In some embodiments, the integrated circuit further includes a third conductor that extends in a first direction, lies on a third metal layer above the front side of the substrate, the third metal layer being different from the first metal layer and the second metal layer. The third conductor overlaps with the second conductor, and the third conductor overlaps with the first gate and the second gate. In some embodiments, the integrated circuit further includes a first via hole and a second via hole. The first via hole electrically couples the third conductor and the second conductor together, and the first via hole is located between the third conductor and the second conductor. The second via hole electrically couples the third conductor and the first gate together, and the second via hole is located between the third conductor and the first gate. In some embodiments, the integrated circuit further includes a third via hole and a fourth via hole. The third via hole electrically couples the first conductor and the second gate together, and the third via hole is located between the first conductor and the second gate. The fourth via hole electrically couples the first conductor and the fourth gate together, and the fourth via hole is located between the first conductor and the fourth gate. In some embodiments, the first transistor, the second transistor, the third transistor, and the fourth transistor are part of a NOR logic gate circuit. In some embodiments, the first gate extends in the second direction and overlaps with the first conductor; the second gate extends in the second direction and overlaps with the first conductor; the third gate extends in the second direction and overlaps with the first conductor; and the fourth gate extends in the second direction and overlaps with the first conductor.

[0554] Another aspect of this description relates to a method of fabricating an integrated circuit. In some embodiments, the method includes fabricating a first set of transistors and a second set of transistors in a front side of a substrate, the first set of transistors being stacked above the second set of transistors, the first set of transistors including a first transistor and a second transistor, and the second set of transistors including a third transistor and a fourth transistor. In some embodiments, the method includes electrically coupling at least a first conductor on the front side of the substrate to at least a first gate of the first set of transistors via at least a back side of the substrate. In some embodiments, electrically coupling at least a first conductor on the front side of the substrate to at least a first gate of the first set of transistors via at least a back side of the substrate includes fabricating a first set of vias on the front side of the substrate, the first set of vias being electrically coupled to at least the first set of transistors. In some embodiments, electrically coupling at least a first conductor on the front side of the substrate to at least a first gate of the first set of transistors via at least a back side of the substrate includes depositing a first conductive material on the front side of the substrate at a first metal level thereby forming a first set of conductors, the first set of conductors being electrically coupled to at least the first set of transistors via the first set of vias, the first set of conductors including at least the first conductor. In some embodiments, electrically coupling at least a first conductor on the front side of the substrate to at least a first gate of the first set of transistors via at least a back side of the substrate further includes fabricating a second set of vias on a back side of the thinned substrate, the second set of vias being electrically coupled to at least the second set of transistors. In some embodiments, electrically coupling at least a first conductor on the front side of the substrate to at least a first gate of the first set of transistors via at least a back side of the substrate further includes depositing a second conductive material on the back side of the thinned substrate at a second metal level thereby forming a second set of conductors, the second set of conductors being electrically coupled to at least the second set of transistors via the second set of vias.

[0555] The features of several embodiments are outlined above so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit, characterized in that, Comprising: A first gate, located on a first level; A second gate, located on a second level below the first level and coupled to the first gate; A third gate, located on the first level and separated from the first gate in a first direction; A fourth gate, located on the second level, separated from the second gate in the first direction and coupled to the third gate; A first input pin, extending in a second direction different from the first direction, on a first metal layer above the front side of the substrate, coupled to at least the first gate and configured to receive a first input signal; And A first conductor, extending in the first direction, on a second metal layer below the back side of the substrate opposite to the front side of the substrate, and the first conductor is coupled to at least the second gate and the fourth gate, Wherein the first input pin is electrically coupled to the third gate through at least the first gate, the second gate or the fourth gate.

2. The integrated circuit according to claim 1, wherein, The first input pin comprises: A second conductor, extending in the second direction, located on the first metal layer, and the second conductor is adjacent to the first gate.

3. The integrated circuit according to claim 2, wherein Further comprising: A third conductor, extending in the first direction, on a third metal layer above the front side of the substrate, the third metal layer being different from the first metal layer and the second metal layer, and the third conductor overlaps with the first gate and the second gate; and A first via hole, electrically coupling the third conductor and the second conductor together, and the first via hole is located between the third conductor and the second conductor.

4. The integrated circuit according to claim 1, wherein Further comprising: A fifth gate, located on the first level and separated from the first gate and the third gate in the first direction; A sixth gate, located on the second level, separated from the second gate and the fourth gate in the first direction and coupled to the fifth gate; And A second input pin, extending in the second direction, located on the first metal layer, coupled to at least the fifth gate or the sixth gate and configured to receive a second input signal.

5. The integrated circuit according to claim 4, characterized in that, Further comprising: A third conductor, extending in the first direction, on a third metal layer above the front side of the substrate, the third metal layer being different from the first metal layer and the second metal layer, and the third conductor overlaps with the fifth gate and the sixth gate.

6. The integrated circuit according to claim 5, wherein Further comprising: A seventh gate, located on the first level and between the fifth gate and the third gate in the first direction; And An eighth gate, located on the second level, between the sixth gate and the fourth gate in the first direction and coupled to the seventh gate.

7. The integrated circuit according to claim 6, wherein, Further comprising: A third via hole, electrically coupling the third conductor and the seventh gate together, and the third via hole is located between the third conductor and the seventh gate.

8. An integrated circuit, characterized in that, Comprising: A first transistor stack, located on a substrate, the first transistor stack comprising: A first transistor of a first type, the first transistor comprising a first gate located on a first level; and A second transistor of a second type different from the first type, and the second transistor includes a second gate, and the second gate is located on a second level below the first level; A second transistor stack located on the substrate, and the second transistor stack includes: A third transistor of the first type, and the third transistor includes a third gate, and the third gate is located on the first level and separated from the first gate in a first direction; and A fourth transistor of the second type, and the fourth transistor includes a fourth gate, and the fourth gate is located on the second level and separated from the third gate in the first direction; a first input pin extending in a second direction, located above the front side of the substrate on a first metal layer, and coupled to the first transistor and the second transistor; and A first conductor extending in the first direction, located below a back side of the substrate opposite to the front side of the substrate on a second metal layer, and the first conductor is coupled to the third gate and the fourth gate, wherein the first input pin is electrically coupled to the third gate from the back side of the substrate.

9. The integrated circuit according to claim 8, characterized in that, Further included are: A third through hole electrically coupling the first conductor and the second gate together, and the third through hole is located between the first conductor and the second gate; And A fourth through hole electrically coupling the first conductor and the fourth gate together, and the fourth through hole is located between the first conductor and the fourth gate.

10. The integrated circuit according to claim 8, wherein The first transistor, the second transistor, the third transistor, and the fourth transistor are part of a NOR logic gate circuit.

Images