Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel, the array substrate comprises a substrate, a first thin film transistor and a second thin film transistor, a first active layer of the first thin film transistor is low temperature polycrystalline silicon, and a second active layer of the second thin film transistor is an oxide semiconductor; the first thin film transistor is of a bottom gate structure, the second thin film transistor is of a top gate structure, a first gate of the first thin film transistor and a second gate of the second thin film transistor are arranged on the same layer, and a first source-drain electrode of the first thin film transistor and a second source-drain electrode of the second thin film transistor are arranged on the same layer. The number of photomasks required for preparing the array substrate can be reduced, and the production cost can be saved.

Description

Technical Field

[0001] The utility model relates to the field of display technology, in particular to an array substrate and a display panel. Background Art

[0002] LTPO (Low Temperature Polycrystalline Oxide) technology combines

[0003] (Low Temperature Poly-Silicon, LTPS) technology and Low Temperature Poly-Oxide (LTPO) technology. The LTPO display panel not only has advantages such as high resolution, high response speed, high brightness, and high aperture ratio, but also has the advantages of low production cost and low power consumption. However, the current film layer structure of the LTPO array substrate is complex and the production cost is relatively high, so it urgently needs to be improved. Summary of the Utility Model

[0004] The embodiments of the utility model provide an array substrate and a display panel, which can solve the technical problems of the complex film layer structure and high production cost of the existing LTPO array substrate.

[0005] The utility model provides an array substrate, including a substrate, a first thin film transistor and a second thin film transistor disposed on the substrate. The first active layer of the first thin film transistor is low temperature polycrystalline silicon, and the second active layer of the second thin film transistor is an oxide semiconductor.

[0006] The first thin film transistor is a top-gate structure, the second thin film transistor is a bottom-gate structure, the first gate of the first thin film transistor and the second gate of the second thin film transistor are arranged in the same layer, and the first source-drain electrode of the first thin film transistor and the second source-drain electrode of the second thin film transistor are arranged in the same layer.

[0007] According to the array substrate provided by the utility model, the array substrate further includes:

[0008] An interlayer dielectric layer covering the first active layer and the second active layer;

[0009] A first planarization layer covering the first source-drain electrode and the second source-drain electrode;

[0010] A first electrode located on the first planarization layer;

[0011] Wherein, the first electrode is electrically connected to the second active layer through a first opening penetrating the interlayer dielectric layer and the first planarization layer.

[0012] According to the array substrate provided by the present utility model, the first source-drain electrode includes a first source electrode and a first drain electrode, and the second source-drain electrode includes a second source electrode and a second drain electrode;

[0013] The first source electrode and the first drain electrode are electrically connected to the first active layer, the second source electrode and the second drain electrode are electrically connected to the second active layer, and the second drain electrode is located on the inner wall of the first opening and is electrically connected to the first electrode.

[0014] According to the array substrate provided by the present utility model, the array substrate further includes:

[0015] A passivation layer covering the first electrode, and a portion of the passivation layer corresponding to the first opening sinks towards the side close to the substrate to form a second opening;

[0016] A second electrode located on the passivation layer, and a portion of the second electrode corresponding to the second opening sinks towards the side close to the substrate to form a third opening;

[0017] A second planarization layer filled in the third opening.

[0018] According to the array substrate provided by the present utility model, the surface of the second planarization layer away from the substrate is flush with the surface of the second electrode away from the substrate.

[0019] According to the array substrate provided by the present utility model, the orthographic projection of the first opening on the substrate falls within the orthographic projection of the second gate on the substrate.

[0020] According to the array substrate provided by the present utility model, the second active layer includes a channel portion and doping portions located on opposite sides of the channel portion, and the orthographic projection of the channel portion on the substrate is located on the side close to the second source electrode within the orthographic projection of the second gate on the substrate.

[0021] According to the array substrate provided by the present utility model, in a top view perspective, the distance between the edge of the channel portion away from the second drain electrode and the edge of the second gate away from the second drain electrode is 0 micrometer - 1 micrometer; the distance between the edge of the channel portion close to the second drain electrode and the edge of the second gate close to the second drain electrode is 2 micrometers - 5 micrometers.

[0022] According to the array substrate provided by the present utility model, the array substrate further includes:

[0023] A first gate insulating layer covering the first active layer, and the first gate and the second gate are located on the first gate insulating layer;

[0024] The second gate insulating layer covers the first gate and the second gate, and the second active layer is located on the second gate insulating layer;

[0025] The first source electrode and the first drain electrode are respectively electrically connected to the first active layer through a first contact hole penetrating through the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer, and the second source electrode is electrically connected to the second active layer through a second contact hole penetrating through the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer.

[0026] According to the array substrate provided by the present invention, the array substrate includes a display area and gate circuit areas located on opposite sides of the display area. The first thin film transistor is located in the gate circuit area, and the second thin film transistor is located in the display area.

[0027] The present invention provides a display panel including the above-mentioned array substrate.

[0028] Beneficial effects: In the array substrate and the display panel provided by the present invention, a first thin film transistor and a second thin film transistor are included. The first active layer of the first thin film transistor is low-temperature polysilicon, and the second active layer of the second thin film transistor is an oxide; the first thin film transistor has a top-gate structure, and the second thin film transistor has a bottom-gate structure; by setting the first gate of the first thin film transistor and the second gate of the second thin film transistor on the same layer, and the first source-drain electrodes of the first thin film transistor and the second source-drain electrodes of the second thin film transistor on the same layer, the present invention can reduce the number of photomasks required for preparing the array substrate, which is beneficial to saving production costs. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 It is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present invention;

[0031] Figure 2 It is a schematic plan structure diagram of a pixel unit of the array substrate provided by an embodiment of the present invention;

[0032] Figures 3A - 3F It is a schematic structure diagram of a preparation method of an array substrate provided by an embodiment of the present invention.

[0033] 1. First thin film transistor; 2. Second thin film transistor;

[0034] 11. Substrate; 12. Buffer layer; 13. First active layer; 14. First gate insulating layer; 15. First gate; 16. Second gate; 17. Second gate insulating layer; 18. Second active layer; 19. Interlayer dielectric layer; 20. First source electrode; 21. First drain electrode; 22. Second source electrode; 23. Second drain electrode; 24. First planarization layer; 25. First electrode; 26. Passivation layer; 27. Second electrode; 28. Second planarization layer; 29. First contact hole; 30. Second contact hole; 31. First opening; 32. Second opening; 33. Third opening. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0036] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "thickness", "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention. In the description of the present invention, "a plurality of" means two or more, unless otherwise specifically defined.

[0037] In the present invention, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include that the first and second features are not in direct contact but are in contact through other features therebetween.

[0038] The embodiments of the present invention provide an array substrate and a display panel. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0039] Please refer to Figure 1, an embodiment of the present utility model provides an array substrate, which includes a substrate 11 and a first thin film transistor 1 and a second thin film transistor 2 disposed on the substrate 11. The first active layer 13 of the first thin film transistor 1 is made of low-temperature polycrystalline silicon, and the second active layer 18 of the second thin film transistor 2 is made of oxide. The first thin film transistor 1 is a top-gate structure, and the second thin film transistor 2 is a bottom-gate structure. The first gate 15 of the first thin film transistor 1 and the second gate 16 of the second thin film transistor 2 are arranged on the same layer, and the first source-drain of the first thin film transistor 1 and the second source-drain of the second thin film transistor 2 are arranged on the same layer, which can reduce the number of photomasks required for preparing the array substrate and is beneficial to saving production costs.

[0040] Specifically, the array substrate includes a display area and gate circuit areas located on opposite sides of the display area. The first thin film transistor 1 is located in the gate circuit area, and the second thin film transistor 2 is located in the display area. It should be noted that the first thin film transistor 1 is a low-temperature polycrystalline silicon thin film transistor, which has the advantages of high mobility, small size, fast charging, and fast switching speed. When used in a gate driving circuit, it can increase the driving current in the gate driving circuit of the display device. The second thin film transistor 2 is an oxide thin film transistor. Specifically, the second thin film transistor 2 is a metal oxide thin film transistor, which has the advantages of good uniformity and low leakage current. When used to drive display pixels, it can reduce the leakage current when the display pixels of the display device are driven.

[0041] Of course, the display panel applying the array substrate can be a liquid crystal display panel or an organic light emitting diode display panel. When the display panel is an organic light emitting diode display panel, the first thin film transistor 1 and the second thin film transistor 2 can be both located in the display area of the array substrate.

[0042] It can be understood that when an oxide thin film transistor and a low-temperature polycrystalline silicon thin film transistor are prepared by mixing in the prior art, multiple additional photomasks will be added, resulting in a complex manufacturing process and an increase in production costs. Specifically, in the prior art, in order to improve the control ability of the gate over the oxide semiconductor device, the oxide thin film transistor is usually set as a top-bottom double-gate structure, and two manufacturing processes are required for the top gate and the bottom gate respectively, and the manufacturing process is complex.

[0043] In the present utility model, by adopting a bottom-gate structure for both the oxide thin-film transistor and the low-temperature polysilicon thin-film transistor, the first gate 15 of the first thin-film transistor 1 and the second gate 16 of the second thin-film transistor 2 are arranged on the same layer, and the first gate 15 and the second gate 16 are formed through the same photomask, which is conducive to saving the photomask. At the same time, the first source-drain electrode of the first thin-film transistor 1 and the second source-drain electrode of the second thin-film transistor 2 are arranged on the same layer, and the first source-drain electrode and the second source-drain electrode are formed through the same photomask, which is conducive to further saving the photomask.

[0044] Optionally, the substrate 11 may be a rigid substrate 11 or a flexible substrate 11. The composition material of the rigid substrate 11 may include at least one of glass and quartz, and the composition material of the flexible substrate 11 may include a polymer resin, such as polyimide.

[0045] Furthermore, a buffer layer 12 may be provided between the substrate 11, the first thin-film transistor 1 and the second thin-film transistor 2 for buffering.

[0046] Optionally, the material of the first active layer 13 includes low-temperature polysilicon, and the material of the second active layer 18 includes indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), indium gallium tin oxide (Indium Gallium Tin Oxide, IGTO), indium gallium oxide (Indium Gallium Oxide, IGO), indium zinc oxide (Indium Zinc Oxide, IZO), aluminum indium zinc oxide (Aluminum Indium Zinc Oxide, AIZO), indium gallium zinc tin oxide (Indium Gallium Zinc Tin Oxide, IGZTO), which may be a single-layer structure or a multi-layer structure.

[0047] Specifically, the array substrate further includes an interlayer dielectric layer 19, a first planarization layer 24 and a first electrode 25. The interlayer dielectric layer 19 covers the first active layer 13 and the second active layer 18, the first planarization layer 24 covers the first source-drain electrode and the second source-drain electrode, and the first electrode 25 is located on the first planarization layer 24. Among them, the first electrode 25 is electrically connected to the second active layer 18 through a first opening 31 penetrating through the interlayer dielectric layer 19 and the first planarization layer 24.

[0048] Specifically, the first electrode 25 is a pixel electrode, and the pixel electrode is electrically connected to the second thin-film transistor 2.

[0049] It can be understood that in the prior art, there are usually at least three insulating layers between the first electrode 25 and the second active layer 18, and the thickness is relatively large. In order to avoid the disconnection of the first electrode 25 in the deep hole, usually two vias (including deep holes and shallow holes) are provided to realize the electrical connection between the first electrode 25 and the second active layer 18, and a relatively large number of photomasks are required. In the present invention, since there are only two insulating layers, namely the first planarization layer 24 and the interlayer dielectric layer 19, between the first electrode 25 and the second active layer 18, and the thickness is relatively small, therefore, the first electrode 25 in the present invention is directly electrically connected to the second active layer 18 through an opening, which is beneficial to saving one manufacturing process.

[0050] Specifically, the first source-drain electrode includes a first source electrode 20 and a first drain electrode 21, and the second source-drain electrode includes a second source electrode 22 and a second drain electrode 23; the first source electrode 20 and the first drain electrode 21 are electrically connected to the first active layer 13, and the second source electrode 22 and the second drain electrode 23 are electrically connected to the second active layer 18.

[0051] Based on the design that the first electrode 25 and the second active layer 18 are directly electrically connected to save photomasks, the first electrode 25 and the drain electrode in the second source-drain electrode in the present invention adopt an integrated design, that is, the first electrode 25 is located on the first planarization layer 24, and the second drain electrode 23 is located on the inner wall of the first opening 31 and is electrically connected to the first electrode 25. At this time, the first electrode 25 and the second drain electrode 23 are prepared through the same photomask.

[0052] It can be understood that since the second active layer 18 and the first electrode 25 have a high light transmittance, the second drain electrode 23 and the first electrode 25 are integrally designed, so that the second drain electrode 23 can have a large light transmittance to avoid the second drain electrode 23 blocking too much light in the vertical direction, which is equivalent to placing the second drain electrode 23 in the pixel opening area, and is beneficial to improving the aperture ratio of the corresponding sub-pixel in the array substrate.

[0053] Specifically, since the first opening 31 is located on the second gate 16, in order to cover the first opening 31, in the embodiment of the present invention, the orthographic projection of the first opening 31 on the substrate 11 falls within the orthographic projection of the second gate 16 on the substrate 11.

[0054] Specifically, the array substrate further includes a passivation layer 26, a second electrode 27, and a second planarization layer 28. The passivation layer 26 covers the first electrode 25 layer, and a portion of the passivation layer 26 corresponding to the first opening 31 is sunken toward the substrate 11 to form a second opening 32. The second electrode 27 is located on the passivation layer 26, and a portion of the second electrode 27 corresponding to the second opening 32 is sunken toward the substrate 11 to form a third opening 33. The second planarization layer 28 is filled in the third opening 33.

[0055] Specifically, the second electrode 27 can be a common electrode, and a storage capacitor can be formed between the pixel electrode and the common electrode.

[0056] In the present utility model, a surface of the second planarization layer 28 away from the substrate 11 is flush with a surface of the second electrode 27 away from the substrate 11. The second planarization layer 28 functions to level the surface. When it is a liquid crystal display panel, a liquid crystal layer is provided above the array substrate, thereby preventing the liquid crystal molecules in the liquid crystal layer from being disorderly arranged due to the uneven surface of the array substrate.

[0057] In the present utility model, as Figure 2 shown, the array substrate includes a plurality of pixel units, each pixel unit includes a plurality of sub-pixel units, and each sub-pixel unit includes the first electrode 25 and the second thin film transistor 2 for driving the first electrode 25. Among them, the second active layer 18 includes a channel portion and doping portions located on opposite sides of the channel portion. A positive projection of the channel portion on the substrate 11 is located on a side of a positive projection of the second gate 16 on the substrate 11 closer to the second source 22.

[0058] Specifically, in a top view perspective, a distance between an edge of the channel portion away from the second drain 23 and an edge of the second gate 16 away from the second drain 23 is 0 micrometer - 1 micrometer; a distance between an edge of the channel portion close to the second drain 23 and an edge of the second gate close to the second drain 23 is 2 micrometers - 5 micrometers.

[0059] Specifically, the array substrate further includes a first gate insulating layer 14 and a second gate insulating layer 17. The first gate insulating layer 14 covers the first active layer 13, and the first gate 15 and the second gate 16 are located on the first gate insulating layer 14. The second gate insulating layer 17 covers the first gate 15 and the second gate 16, and the second active layer 18 is located on the second gate insulating layer 17. The first source electrode 20 and the first drain electrode 21 are respectively electrically connected to the first active layer 13 through a first via hole 29 penetrating through the interlayer dielectric layer 19, the second gate insulating layer 17, and the first gate insulating layer 14, and the second source electrode 22 is electrically connected to the second active layer 18 through a second via hole 30 penetrating through the interlayer dielectric layer 19, the second gate insulating layer 17, and the first gate insulating layer 14.

[0060] An embodiment of the present invention further provides a display panel. The display panel includes the array substrate in the above embodiment. The display panel can be a liquid crystal display panel or an organic light emitting diode display panel. The liquid crystal display panel further includes a color filter substrate disposed opposite to the array substrate and a liquid crystal layer disposed between the array substrate and the color filter substrate. The liquid crystal layer includes a plurality of liquid crystal molecules.

[0061] Please refer to Figures 3A - 3F , an embodiment of the present invention further provides a method for manufacturing an array substrate, including the following steps:

[0062] S1: Provide a substrate 11, and form a buffer layer 12 on the substrate;

[0063] S2, use a first photomask to form a first active layer 13 on the substrate 11;

[0064] S3, form a first gate insulating layer 14 covering the first active layer 13;

[0065] S4, use a second photomask to form a first gate 15 and a second gate 16 on the first gate insulating layer 14;

[0066] S5, form a second gate insulating layer 17 covering the first gate 15 and the second gate 16;

[0067] S6, use a third photomask to form a second active layer 18 on the second gate insulating layer 17;

[0068] S7, use a fourth photomask to conduct the second active layer 18 to form a channel region and two doping regions respectively located on opposite sides of the channel region;

[0069] S8, form an interlayer dielectric layer 19 covering the second active layer 18;

[0070] S9, a first contact hole 29 penetrating through the interlayer dielectric layer 19, the second gate insulating layer 17, and the first gate insulating layer 14 is formed using a fifth photomask;

[0071] S10, a second contact hole 30 penetrating through the interlayer dielectric layer 19 is formed using a sixth photomask;

[0072] S11, a first source electrode 20, a first drain electrode 21, and a second source electrode 22 are formed on the interlayer dielectric layer 19 using a seventh photomask. The first source electrode 20 and the first drain electrode 21 are respectively electrically connected to the first active layer 13 through the first contact hole 29, and the second source electrode 22 is electrically connected to the doped region of the second active layer 18 through the second contact hole 30;

[0073] S12, a first planarization layer 24 covering the first source electrode 20, the first drain electrode 21, and the second source electrode 22 is formed;

[0074] S13, a first opening 31 penetrating through the interlayer dielectric layer 19 and the first planarization layer 24 is formed using an eighth photomask;

[0075] S14, a first electrode 25 is formed on the first planarization layer 24 using a ninth photomask, and a second drain electrode 23 is formed in the first opening 31. The first electrode 25 is electrically connected to the doped region of the second active layer 18 through the first opening 31;

[0076] S15, a passivation layer 26 covering the first electrode 25 is formed using a tenth photomask. The portion of the passivation layer 26 corresponding to the first opening 31 is recessed toward the side close to the substrate 11 to form a second opening 32;

[0077] S16, a second electrode 27 is formed on the passivation layer 26 using an eleventh photomask. The portion of the second electrode 27 corresponding to the second opening 32 is recessed toward the side close to the substrate 11 to form a third opening 33;

[0078] S17, a second planarization layer 28 is formed in the third opening 33 using a twelfth photomask.

[0079] Among them, steps S1 - S4 can be referred to Figure 3A , steps S5 - S6 can be referred to Figure 3B , step S7 can be referred to Figure 3C , steps S8 - S10 can be referred to Figure 3D , step S11 can be referred to Figure 3E , steps S12 - S17 can be referred to Figure 3F .

[0080] It can be seen that, by adopting the method for manufacturing an array substrate provided by the present utility model, a total of twelve photomasks are required for manufacturing the array substrate. Compared with at least fourteen photomasks required for manufacturing the array substrate in the prior art, the number of photomasks is reduced, which is beneficial to saving production costs.

[0081] Advantageous effects: In the array substrate and display panel provided by the present utility model, a first thin film transistor and a second thin film transistor are included. The first active layer of the first thin film transistor is low-temperature polycrystalline silicon, and the second active layer of the second thin film transistor is an oxide; the first thin film transistor is a top-gate structure, and the second thin film transistor is a bottom-gate structure; by setting the first gate of the first thin film transistor and the second gate of the second thin film transistor on the same layer, and setting the first source / drain of the first thin film transistor and the second source / drain of the second thin film transistor on the same layer, the present utility model can reduce the number of photomasks required for manufacturing the array substrate, which is beneficial to saving production costs.

[0082] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] The above has introduced in detail an array substrate and a display panel provided by an embodiment of the present utility model. Specific examples are used herein to elaborate on the principle and implementation manner of the present utility model. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present utility model; those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present utility model.

Claims

1. An array substrate, characterized in that, It includes a substrate, a first thin-film transistor and a second thin-film transistor disposed on the substrate. The first active layer of the first thin-film transistor is low-temperature polycrystalline silicon, and the second active layer of the second thin-film transistor is an oxide semiconductor; The first thin-film transistor is a top-gate structure, and the second thin-film transistor is a bottom-gate structure. The first gate of the first thin-film transistor and the second gate of the second thin-film transistor are arranged on the same layer, and the first source-drain of the first thin-film transistor and the second source-drain of the second thin-film transistor are arranged on the same layer; The array substrate further includes a first gate insulating layer, a second gate insulating layer, an interlayer dielectric layer, a first planarization layer and a first electrode; the first active layer is on one side of the substrate, the first gate insulating layer covers the side of the first active layer away from the substrate, the first gate and the second gate are on the side of the first gate insulating layer away from the substrate, the second gate insulating layer covers the side of the first gate and the second gate away from the substrate, the second active layer is on the side of the second gate insulating layer away from the substrate, the interlayer dielectric layer covers the side of the second active layer away from the substrate, the first source-drain and the second source-drain are on the side of the interlayer dielectric layer away from the substrate, the first planarization layer covers the side of the first source-drain and the second source-drain away from the substrate, the first electrode is on the side of the first planarization layer away from the substrate, and the first electrode is electrically connected to the second active layer through a first opening penetrating the first planarization layer and the interlayer dielectric layer; Wherein, the positive projection of the first opening on the substrate falls within the positive projection of the second gate on the substrate. The second active layer includes a channel portion and doping portions on opposite sides of the channel portion. The positive projection of the channel portion on the substrate is on the side of the second source of the second gate in the positive projection of the second gate on the substrate close to the second source-drain; The first electrode is a pixel electrode. The first electrode and the second drain of the second source-drain are integrally designed. The first electrode is on the first planarization layer. A part of the second drain is on the inner wall of the first opening and is electrically connected to the first electrode, and another part of the second drain is on the bottom wall of the first opening and is electrically connected to the second active layer.

2. The array substrate according to claim 1, wherein The first source-drain includes a first source and a first drain, and the second source-drain includes the second source and the second drain; The first source and the first drain are electrically connected to the first active layer, and the second source and the second drain are electrically connected to the second active layer.

3. The array substrate according to claim 2, wherein The array substrate further includes: A passivation layer covering the first electrode, and a part of the passivation layer corresponding to the first opening sinks towards the substrate side to form a second opening; A second electrode on the passivation layer, and a part of the second electrode corresponding to the second opening sinks towards the substrate side to form a third opening; A second planarization layer filling the third opening.

4. The array substrate according to claim 3, wherein One side surface of the second flat layer away from the substrate is flush with one side surface of the second electrode away from the substrate.

5. The array substrate according to claim 1, wherein In a top view perspective, the distance between one side edge of the channel portion away from the second drain and one side edge of the second gate away from the second drain is 0 μm - 1 μm; the distance between one side edge of the channel portion close to the second drain and one side edge of the second gate close to the second drain is 2 μm - 5 μm.

6. The array substrate according to claim 2, wherein The first source electrode and the first drain electrode are respectively electrically connected to the first active layer through a first contact hole penetrating through the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer, and the second source electrode is electrically connected to the second active layer through a second contact hole penetrating through the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer.

7. The array substrate according to claim 1, wherein The array substrate includes a display area and gate circuit areas located on opposite sides of the display area. The first thin film transistor is located in the gate circuit area, and the second thin film transistor is located in the display area.

8. A display panel, characterized in that, An array substrate including any one of claims 1 - 7.

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